JP4685997B2 - Pipelined dual-port integrated circuit memory - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates generally to memories, and more particularly to dual port memories.
[0002]
[Prior art]
Dual port memory is useful in a variety of applications. Dual port memory is particularly useful in the field of communications and multiprocessor systems. In a multiprocessor system, one processor can write data to the array and the other processor can read data. In particular, the dual port RAM is particularly suitable for a communication application called an asynchronous transfer mode (ATM). With ATM switches, large amounts of data must be transferred between two processing devices. Another communication application is the standard IEEE 802.3 (commonly known as the trademark “Ethernet” manufactured by Digital Equipment Corporation). These types of applications require dual port memories that are inexpensive but contain large arrays.
[0003]
[Problems to be solved by the invention]
Traditionally, dual port random access memory (RAM) has been constructed using one of two methods. In the first method, each memory cell was a true dual port and therefore required 8 transistors. Integrated circuit memories based on this method are expensive because large dual port memory cells make the array itself very large. The second method utilizes standard single port static RAM cells in a partitioned array. If both ports attempt to access the same partition, one of these accesses must be delayed. As the number of partitions increases, the likelihood of collisions decreases, but costs increase due to extra decoding and collision detection circuitry. Thus, what is needed is a large dual-port RAM that is inexpensive and fast, while utilizing conventional single-port SRAM cells. These needs are met by the present invention, whose features and advantages are further described with reference to the drawings and the following description.
[0004]
【Example】
FIG. 1 shows a memory 20 according to the invention in the form of a partial block diagram and a partial logic diagram. The memory 20 is an integrated circuit dual port static random access memory (SRAM), a single port SRAM array 21, an arbitration circuit 24, bonding pads 26 and 28, an input 30 and an output. Part 50 is generally included. The array 21 has an input terminal that receives an N-bit address, a control input terminal that receives a signal inversion W, a clock input terminal that receives clock signals labeled “CLKX” and “CLKY”, and “D _IN ], A data input terminal for receiving an M-bit data value labeled “ _OUT ] Marked M And an output terminal for providing a bit data value. The array 21 also includes a decoder block 22 and a write control circuit 23.
[0005]
The memory 20 is responsive to two clock signals labeled “CLOCK (X)” and “CLOCK (Y)” received on the bonding pads 26 and 28, respectively. Arbitration circuit 24 includes a first input terminal connected to bonding pad 26 for receiving CLOCK (X), a second input terminal connected to bonding pad 28 for receiving CLOCK (Y), and a signal An output terminal for supplying CLKX and CLKY to the array 21, an output terminal for supplying a control signal labeled "XYSEL", an output terminal for supplying a signal labeled "QCLKX", and a signal labeled "QCLKY" Output terminal.
[0006]
Input 30 generally includes bonding pads 31-36, D-type flip-flops 40-45, and multiplexers (MUX) 46-48. Bonding pad 31 receives an N-bit address signal labeled “ADD (X)”. Bonding pad 32 receives an N-bit address signal labeled “ADD (Y)”. Bonding pad 33 receives a write control signal labeled “inverted W (X)”. Bonding pad 34 receives a write control signal labeled “Inverted W (Y)”. The bonding pad 35 is “D _IN An M-bit input data signal labeled (X) ”is received. The bonding pad 36 is “D _IN Receives an M-bit data input signal labeled (Y). As will be apparent, each of the bonding pads 31, 32 represents N bonding pads for receiving an address signal, respectively, and each of the bonding pads 35, 36 is D respectively. _IN 1 represents M bonding pads for receiving signals, but is shown as a single bonding pad in FIG. 1 for clarity.
[0007]
The flip-flop 40 has a D input terminal connected to the bonding pad 31, a clock input terminal for receiving a signal CLOCK (X), and a Q output terminal, and receives each address signal of ADD (X). Each represents one of N D-type flip-flops that provide a latched address signal. The flip-flop 41 has a D input terminal connected to the bonding pad 32, a clock input terminal for receiving the signal CLOCK (Y), and a Q output terminal, and receives each address signal of ADD (Y). And represents one of the N flip-flops that provide the latched address signal. Flip-flop 42 has a D input terminal connected to bonding pad 33, a clock input terminal for receiving signal CLOCK (X), and a Q output terminal. Flip-flop 43 has a D input terminal connected to bonding pad 34, a clock input terminal for receiving signal CLOCK (Y), and a Q output terminal. The flip-flop 44 has a D input terminal connected to the bonding pad 35, a clock input terminal for receiving CLOCK (X), and a Q output terminal. _IN (X) represents one of M flip-flops received respectively. The flip-flop 45 has a D input terminal connected to the bonding pad 36, a clock input terminal for receiving the signal CLOCK (Y), and a Q output terminal. _IN (Y) represents one of M flip-flops receiving the corresponding signal.
[0008]
The MUX 46 includes a first input terminal connected to the Q output terminal of the flip-flop 40, a second input terminal connected to the Q output terminal of the flip-flop 41, a control input terminal that receives the signal XYSEL, and an output terminal. 1 represents one of N MUXs which receive the address signals of ADD (X) and ADD (Y) and provide the corresponding output to the array 21 as the signal ADD. The MUX 47 has a first input terminal connected to the Q output terminal of the flip-flop 42, a second input terminal connected to the Q output terminal of the flip-flop 43, a control input terminal that receives the signal XYSEL, and a signal inversion W. And an output terminal provided to the array 21. The MUX 48 includes a first input terminal connected to the Q output terminal of the flip-flop 44, a second input terminal connected to the Q output terminal of the flip-flop 45, a control input terminal for receiving the signal XYSEL, and a signal D _IN Output to the array 21 and a signal D _IN (X) and D _IN Each signal of (Y) is received and signal D _IN Represents one of the M MUXs that provide the corresponding output to the array 21.
[0009]
The output unit 50 includes D-type flip-flops 51 to 54, three-state buffers 55 and 56, and bonding pads 60 to 6 3 In general. Flip-flop 51 has a D input terminal connected to the output terminal of array 21, a clock input terminal for receiving QCLKX, and an output terminal. _OUT Represents one of the M flip-flops that each receive and provide a corresponding output. The flip-flop 52 has a D input terminal connected to the Q output terminal of the flip-flop 51, a clock input terminal that receives the signal CLOCK (X), and an output terminal. One of M flip-flops corresponding to one of the flip-flops. Flip-flop 53 has a D input terminal connected to the D output terminal of array 21, a clock input terminal for receiving signal QCLKY, and an output terminal. _OUT Represents one of the M flip-flops that each receive and provide a corresponding output. The flip-flop 54 has a D input terminal connected to the Q output terminal of the flip-flop 53, a clock input terminal that receives the signal CLOCK (Y), and an output terminal. One of M flip-flops corresponding to one of the flip-flops. The buffer 55 has a data input terminal connected to the Q output terminal of the flip-flop 52, a data output terminal, and a control terminal connected to the bonding pad 60, and is connected to a corresponding one of the flip-flop 52. Represents one of the M buffers. The buffer 56 has a data input terminal connected to the Q output terminal of the flip-flop 54, an output terminal, and a control input terminal connected to the bonding pad 63, and M buffers corresponding to each of the flip-flops 54. Represents one of the buffers. Bonding pad 60 receives an output enable signal labeled “Inverted OE (X)” connected to the control input terminal of buffer 55. The bonding pad 61 is “DATA _OUT (X) "is connected to the output terminal of the buffer 55 to provide an output signal labeled" X "" and represents one of M bonding pads corresponding to each buffer such as the buffer 55. The bonding pad 62 is “DATA _OUT (Y) represents one of the M bonding pads connected to the output terminal of the buffer 56 to provide a signal labeled "" and connected to the corresponding output of the buffer 56. Bonding pad 63 receives an output enable signal labeled “Inverted OE (Y)” and is connected to the control terminal of buffer 56.
[0010]
In operation, the memory 20 functions as a full dual-port static random access memory (SRAM). There is no situation in the memory 20 that is not accessible within a single cycle of each clock signal. In addition, the memory 20 utilizes a standard 6-transistor SRAM cell, thus eliminating the need for special dual port cells associated with other dual port schemes.
[0011]
The memory 20 achieves these effects by allowing access to the array 21 on each port asynchronously, where each access is low to high for each clock signal. Start with a transition to. Thus, as long as signals CLOCK (X) and CLOCK (Y) have a frequency lower than the specified maximum frequency, memory 20 ensures that both accesses are each completed within one clock cycle. To do. In particular, the dual port SRAM 20 ensures that access on the X port is given priority when CLOCK (X) and CLOCK (Y) have low to high transitions that occur almost simultaneously. Arbitration circuit 24 is used. Further, the arbitration circuit 24 ensures that no metastability problem occurs when there is a small amount of skew between CLOCK (X) and CLOCK (Y).
[0012]
Array 21 is a single port memory core that can be accessed at twice the speed of either signal CLOCK (X) or CLOCK (Y). In general, the memory 20 generates an access request to the array 21 in response to the external access request. Arbitration circuit 24 ensures that the earlier of the two access requests is provided to array 21, unless the two access requests are received substantially simultaneously. If access requests are received simultaneously, the arbitration circuit 24 prioritizes the X port.
[0013]
More specifically, the arbitration circuit 24 outputs a signal XYSEL to indicate whether access to the array 21 is given to the X port or the Y port. In this particular embodiment, a logic high level represents access on the X port, while a logic low level represents access on the Y port. Therefore, when the signal XYSEL is a logic high, the MUX 46 selects the first input and provides the signal ADD (X) to the array 21 as the N-bit signal ADD. The array 21 then performs conventional matrix decoding using the decoder 22 to produce the signal D _OUT (Assuming the access is a read cycle). Similarly, if arbitration circuit 24 provides a logic low XYSEL signal, MUX 46 selects the second input. The signal XYSEL selects the inputs of the MUXs 47 and 48 corresponding to the ports to which the arbitration circuit 24 has given priority. Further, the arbitration circuit 24 supplies the clock signals CLKX and XLKY to the write control circuit 23 of the array 21. It should be noted that in another embodiment, the clock signals CLKX and CLKY may be replaced with a single clock signal.
[0014]
Signal QC L KX and QCLKY control the read data path for the X and Y ports, respectively. The signal QCLKX is input to the clock input terminal of the flip-flop 51, and the signal QCLKY is input to the clock input terminal of the flip-flop 53. It should be noted that the data output path also includes additional flip-flops 52 and 54 to synchronize incoming data with the next rising edge of signals CLOCK (X) and CLOCK (Y), respectively. Buffers 55 and 56 are connected to signal DATA. _OUT (X) and DATA _OUT Conventional three-state control is performed for (Y).
[0015]
FIG. 2 shows a portion 70 of the array 21 of FIG. 1 that includes a single port memory cell 80 in the form of a partial schematic and partial block diagram. Memory cell 80 is a static RAM cell that is accessed by activation of a signal labeled "WL" that conducts on word line 72, on a complementary pair of bit lines 74 and 76, respectively. Conducting differential data signals labeled "BL" and "Inverted BL". Memory cell 80 includes N-channel MOS (metal oxide semiconductor) transistors 82 and 84 and inverters 86 and 88. Transistor 82 has a first current electrode connected to bit line 74, a gate connected to word line 72, and a second current electrode. Transistor 84 has a first current electrode connected to bit line 76, a gate connected to word line 72, and a second current electrode. Inverter 86 has an input terminal connected to the second current electrode of transistor 82, and an output terminal connected to the second current electrode of transistor 84. Inverter 88 has an input terminal connected to the output terminal of inverter 86, and an output terminal connected to the input terminal of inverter 86.
[0016]
In operation, memory cell 80 is a standard single-port 6-transistor memory cell whose logic state is stored by the operation of back-to-back inverters 86,88. It should be noted that as described herein, the number of transistors in a memory cell includes access transistors in addition to the storing transistors. Memory cell 80 is accessed conventionally by activation of word line 72. When word line 72 is active, transistors 82 and 84 are conductive, coupling the contents of the memory cell to bit lines 74 and 76 as a relatively small differential voltage. This voltage is then detected and output. During the write cycle, the external circuit applies a relatively large differential voltage between BL and inverted BL to overwrite the content stored in memory 80.
[0017]
Memory cell 80 is different from a standard 8-transistor dual port memory cell. First of all, the memory cell 80 has only six transistors instead of eight transistors. Second, the memory cell 80 is connected to only one complementary pair of bit lines, not two separate pairs of bit lines, saving two extra access transistors. Furthermore, there is only one word line that can access the memory cell 80 as compared to the two word lines in the case of a dual port memory cell. In addition to saving two transistors, the connection of only one word line and one bit line pair reduces the amount of metal wiring for the memory cell 80. Due to these effects, the array 21 can be configured by using a relatively inexpensive conventional SRAM cell. It should be noted that an array constructed using a single port memory cell, such as memory cell 80, is approximately 25% of the size of an array based on a corresponding 8-transistor true dual port memory cell. is there.
[0018]
FIG. 3 illustrates the arbitration circuit 24 of FIG. 1 in the form of a partial block diagram and a partial logic diagram. The arbitration circuit 24 includes one-shot 100 and 101, SR type flip-flops 102 and 103, inverters 104 and 105, NOR latch 110, NAND latch 120, inverters 130 and 131, one-shot 132 and 133, inverters 134 and 135, and SR type. A flip-flop 136 is included. One shot 100 has an input terminal connected to bonding pad 26 for receiving signal CLOCK (X), and an output terminal. One shot 101 has an input terminal connected to bonding pad 28 for receiving signal CLOCK (Y), and an output terminal. The flip-flop 102 has an S input terminal connected to the output terminal of the one-shot 100, an R input terminal, and a Q output terminal. The flip-flop 103 has an S input terminal connected to the output terminal of the one-shot 101, an R input terminal, and a Q output terminal. Inverter 104 has an input terminal connected to the Q output terminal of flip-flop 102, and an output terminal. Inverter 105 has an input terminal connected to the Q output terminal of flip-flop 103, and an output terminal.
[0019]
The NOR latch 110 includes NOR gates 111 and 112. NOR gate 111 has a first input terminal connected to the output terminal of inverter 104, a second input terminal, and an output terminal. The NOR gate 112 has a first input terminal connected to the output terminal of the NOR gate 111, a second input terminal connected to the output terminal of the inverter 105, and an output terminal connected to the second input terminal of the NOR gate 111. And have.
[0020]
NAND latch 120 includes NAND gates 121 and 122. NAND gate 121 has a first input terminal connected to the output terminal of NOR gate 111, a second input terminal, and an output terminal. NAND gate 122 has a first input terminal connected to the output terminal of NAND gate 121, a second input terminal connected to the output terminal of NOR gate 112, and an output connected to the second input terminal of NAND gate 121. Terminal. Inverter 130 has an input terminal connected to the output terminal of NAND gate 121, and an output terminal. Inverter 131 has an input terminal connected to the output terminal of NAND gate 122, and an output terminal. One shot 132 has an input terminal connected to the output terminal of inverter 130, and an output terminal for providing signal CLKX. One-shot 133 has an input terminal connected to the output terminal of inverter 131, and an output terminal for providing signal CLKY. Inverter 134 has an input terminal connected to the output terminal of one-shot 132, and an output terminal connected to the R input terminal of flip-flop 102 for providing signal QCLKX. Inverter 135 has an input terminal connected to the output terminal of one-shot 133, and an output terminal connected to the R input terminal of flip-flop 103 for providing signal QCLKY. Flip-flop 136 has an S input terminal connected to the output terminal of one-shot 132, an R input terminal connected to the output terminal of one-shot 133, and a Q output terminal for providing signal XYSEL.
[0021]
Arbitration circuit 24 includes two one-shots 100, 101 that provide short-term pulses to resolve noisy transitions in signals CLOCK (X) and CLOCK (Y). The pulse width of the one-shot 100, 101 is such that when the CLOCK (X) or CLOCK (Y) has a relatively low frequency, the reset input of the flip-flops 102, 103 does not occur before the set input becomes invalid. Short enough. The Q outputs of the flip-flops 102 and 103 are inverted and given to the input of the NOR latch 110.
[0022]
Note that in some situations, the NOR latch 110 may be metastable. In these states, the outputs of the NOR gates 111 and 112 tend to be fixed at an intermediate level. However, the arbitration circuit 24 solves this metastable problem with the NAND latch 120. The threshold value of the NAND latch 120 is set so that the NAND latch 120 can solve even if the NOR latch 110 becomes metastable. The output of the NAND latch 120 is further inverted and input to the one shots 132 and 133. The one shots 132 and 133 convert a slow or unstable clock signal and generate a steep pulse with a limited response period. The outputs of the one shots 132 and 133 are inverted to provide signals QCLKX and QCLKY, which are fed back to the R inputs of the flip-flops 102 and 103. This feedback operation resolves metastability in the NOR latch 110.
[0023]
Although the present invention has been described with reference to particular embodiments, further modifications and improvements will occur to those skilled in the art. Accordingly, the present invention is intended to embrace all such modifications that do not depart from the scope of the invention as defined in the appended claims.
[0024]
A selection signal for selecting which of the first or second address signals is applied to the plurality of memory cells in response to determining which of the first or second clock signals transitions first. Is provided by the arbitration circuit.
[0025]
Further, it is another aspect of the present invention that the arbitration circuit is constituted by the first, second and third flip-flops and the first pair of mutually coupled logic gates. The first flip-flop has a first input terminal for receiving a first clock signal and an output terminal for providing a first latched clock signal. The second flip-flop has a first input terminal for receiving a second clock signal and an output terminal for providing a second latched clock signal. The first pair of interconnected logic gates has first and second input terminals coupled to the output terminals of the first and second flip-flops, respectively, and has first and second output terminals. The third flip-flop has a first input terminal coupled to the first pair of first output terminals of the cross-coupled logic gate and a second input terminal coupled to the first pair of second output terminals of the cross-coupled logic gate. And an output terminal for supplying a selection signal.
[0026]
The arbitration circuit also includes first and second input terminals coupled to a first pair of first and second output terminals of the first pair of mutually coupled logic gates, and a first coupled to the first input terminal of the third flip-flop. It is yet another aspect of the present invention to be configured by a second pair of interconnected logic gates having an output terminal and a second output terminal coupled to the second input terminal of the third flip-flop.
[0027]
In addition, it is still another aspect of the present invention that the arbitration circuit further includes first and second pulse generators. The first pulse generator has an input terminal coupled to the second output terminal of the second pair of interconnected logic gates and an output terminal coupled to the first input terminal of the third flip-flop. The second pulse generator has a first input terminal coupled to the second output terminal of the second pair of interconnected logic gates, and an output terminal coupled to the second input terminal of the third flip-flop.
[0028]
The first flip-flop has a second input terminal coupled to the output terminal of the first pulse generator, and the second flip-flop has a second input coupled to the output terminal of the second pulse generator. Having a terminal is yet another aspect of the present invention.
[Brief description of the drawings]
FIG. 1 is a partial block diagram and partial logic diagram illustrating a pipelined dual-port integrated circuit memory according to the present invention.
2 is a partial schematic and partial block diagram illustrating a portion of the array of FIG. 1, including a single port static RAM cell. FIG.
3 is a partial block diagram and partial logic diagram illustrating the arbitration circuit of FIG. 1; FIG.
[Explanation of symbols]
20 memory
21 Single-port SRAM array
22 Decoder block
23 Light control circuit
24 Arbitration circuit
26, 28 Bonding pads
30 Input section
31-36 Bonding pads
40-45 D-type flip-flop
46-48 multiplexer (MUX)
50 output section
51-54 D-type flip-flop
55,56 3-state buffer
60-64 bonding pads
72 word lines
74,76 bit line
80 single-port memory cells
82,84 N-channel MOS transistors
86,88 inverter
100, 101, 132, 133 One shot
102,103,136 SR type flip-flop
104, 105, 130, 131, 134, 135 Inverter
110 NOR latch
111, 112 NOR gate
120 NAND latch
121, 122 NAND gate
130,131 inverter

Claims (5)

An integrated circuit memory (20) comprising:
A plurality of memory cells (21), each of the plurality of memory cells (21) being coupled to one word line and one bit line pair ( 21);
An address decoder (22) coupled to the plurality of memory cells (21) for selecting a memory cell of the plurality of memory cells (21) in response to receiving an address;
A first address port (31) coupled to the address decoder for providing a first address to the address decoder (22) for accessing the plurality of memory cells (21);
A second address port (32) coupled to the address decoder (22) for providing a second address to the address decoder for accessing the plurality of memory cells (21);
Read data ports (61, 62) coupled to the plurality of memory cells for reading data from the plurality of memory cells (21) in response to either the first or second address. ;
A write data port (35, 36) coupled to the plurality of memory cells (21) for writing data to the plurality of memory cells in response to either the first or second address. ;
Arbitration circuit (24) coupled to the first and second clock ports for receiving the first clock signal and the second clock signal, wherein the first and second clock signals are asynchronous to each other, The arbitration circuit (24) determines which of the first or second address is supplied to the plurality of memory cells based on the first and second clock signals during the access to the integrated circuit memory (20). Determining an arbitration circuit (24);
A timing circuit (51, 53) connected between the plurality of memory cells and the read data port, receiving a timing signal from the arbitration circuit, and timings read data; and a first synchronization circuit and a second synchronization circuit coupled to receive respectively the first clock signal and the second clock signal are asynchronous to each other, said first clock signal and the asynchronous read data with each other A first synchronization circuit (52) and a second synchronization circuit (54) for synchronizing with two clock signals, respectively;
An integrated circuit memory (20) characterized by comprising:  The arbitration circuit (24) ensures that substantially simultaneous requests are processed sequentially within a single clock cycle of one of the first or second clock signals. The integrated circuit memory (20) of claim 1.  The first and second clock signals are applied to the address decoder (22), the read data port, and the write data port, and the arbitration circuit (24) first receives the first clock signal. In response to determining that the transition has occurred, the plurality of memory cells (21) are accessed using a first clock signal for access timing, and the arbitration circuit (24) is configured to receive a second clock. The plurality of memory cells (21) are accessed using a second clock signal for access timing in response to determining that a signal first transitioned. The integrated circuit memory (20) of claim 1. Pipelined dual-port static random access memory (20) comprising:
A plurality of static random access memory cells (21), each of the plurality of static random access memory cells (21) comprising one word line and one bit line pair A plurality of static random access memory cells (21) coupled to
Arbitration circuit (24) receiving a first clock signal and a second clock signal, wherein the first and second clock signals are asynchronous with each other, and the arbitration circuit (24) is asynchronous with each other. An arbitration circuit (24) that determines which of the second clock signals transitions first and provides a selection signal in response thereto;
In response to receiving an address, the plurality of static random access memory cells (21) for selecting a memory cell among the plurality of static random access memory cells (21). An address decoder (22) coupled to
Responsive to the selection signal being in a first logic state to provide a first address to the address decoder (22) for accessing the plurality of static random access memory cells (21). A first address port (31) coupled to the address decoder (22);
In response to the selection signal being in a second logic state, a second address is provided to the address decoder (22) for accessing the plurality of static random access memory cells (21). A second address port (32) coupled to the address decoder (22);
The plurality of static random access memory cells (21) for reading data from the plurality of static random access memory cells (21) in response to either the first or second address. ) Coupled to the read data port (61, 62);
The plurality of static random access memory cells (21) for writing data to the plurality of static random access memory cells (21) in response to either the first or second address. ) Coupled to the write data port (35, 36);
A timing circuit (51) connected between the plurality of static random access memory cells (21) and the read data port, receives a timing signal from the arbitration circuit, and takes a timing of read data. , 53); and a first synchronizing circuit and the second synchronization circuit coupled to the timing circuit to receive respectively the first clock signal and the second clock signal are asynchronous to one another, the asynchronous read data with each other A first synchronization circuit (52) and a second synchronization circuit (54) for synchronizing with the first clock signal and the second clock signal, respectively;
A pipelined dual-port static random access memory (20) characterized by comprising:  The arbitration circuit (24) ensures that substantially simultaneous access requests are processed sequentially within a single clock cycle of one of the first or second clock signals. A pipelined dual-port static random access memory (20) according to claim 4.

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