CN103219037B - The on-chip memory of multi-port read-write - Google Patents
The on-chip memory of multi-port read-write Download PDFInfo
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Abstract
A kind of on-chip memory of multi-port read-write, comprise: the three grades of circuit structures connected successively, first order circuit structure is for the gating of the latch and storage unit that input data, second level circuit structure is used for store in data write storage unit, tertiary circuit structure is for storing the reading of data, wherein, this first order circuit structure comprises write address code translator, clock gated logic circuit, and data input latch, its input end is connected with the output terminal of clock gated logic circuit; This second level circuit structure comprises multiple static ram cell, and its input end is connected with the output terminal of write address code translator and data input latch respectively; This tertiary circuit structure comprises MUX, and its input end is connected with each output terminal of multiple static ram cell; Read address decoder, its output terminal is connected with the input end of MUX respectively; Data output latch, its input end is connected with the output terminal of MUX.
Description
Technical field
The invention belongs to integrated circuit fields, the on-chip memory of a kind of multi-port read-write particularly in digital circuit.
Background technology
In order to meet the demand such as quick access and data buffer storage of data, nearly all chip internal is all integrated with on-chip memory.These on-chip memories (cache in such as processor) participate in its main operational directly usually in data path, have multi-port read-write, and access speed requires high, and single memory capacity is less, but the features such as One's name is legion.Day by day huge along with circuit design scale, and the developing rapidly of single-chip multi-core parallel concurrent processor, digit chip is increasing to the demand of data path buffer memory in sheet, and its area summation has occupied appreciable ratio in whole chip area.
At present, in on-chip memory design, mainly with static RAM (SRAM), register file, these 3 kinds of structures of latch arrays are the most common.For SRAM structure, for standard 6 pipe unit type SRAM, although the area that storage unit takies is little, access speed is also very fast, due to the use of sense amplifier, making SRAM when storing for low capacity, consuming much extra area.Register file and latch display are relatively applicable to the data storing low capacity by contrast, and both respectively has relative merits.Register file has good temporal characteristics, be suitable for use in very much in synchronizing sequential circuit, and be supported in the same cycle read-write operation is carried out to same unit, latch arrays sequential expense is large, can not support to read while write, but under same memory cell number, the area that be close to half fewer than register file can be taken.
In sum, existing interior storage organization all well when guaranteed performance, can not save area, reduces manufacturing cost, so take into account area and performance in the urgent need to a kind of new memory circuitry.And the present invention devises (low-power consumption) clock synchronous storer of a kind of novel support multi-port read-write particularly write once read many, the SRAM memory cell utilizing area less achieves the temporal characteristics of register.
Summary of the invention
The object of the invention is to, provide a kind of on-chip memory of multi-port read-write, described on-chip memory can support multi-port read-write particularly write once read many, has the feature of low-power consumption.
The invention provides a kind of on-chip memory of multi-port read-write, comprising:
The three grades of circuit structures connected successively, first order circuit structure is for the gating of the latch and storage unit that input data, and second level circuit structure to be used for store in data write storage unit, tertiary circuit structure for storing the reading of data, wherein,
This first order circuit structure comprises write address code translator, clock gated logic circuit, and data input latch, and its input end is connected with the output terminal of clock gated logic circuit;
This second level circuit structure comprises multiple static ram cell, and its input end is connected with the output terminal of write address code translator and data input latch respectively;
This tertiary circuit structure comprises MUX, and its input end is connected with each output terminal of multiple static ram cell; Read address decoder, its output terminal is connected with the input end of MUX respectively; Data output latch, its input end is connected with the output terminal of MUX.
The present invention possesses following advantage: 1. because generally, Data output latch number n is far smaller than memory depth k, so in this storer, except address decoding circuitry and static storage cell, the area of other peripheral circuits almost can be ignored, so this storer has greater advantage on area.2. circuit structure is fairly simple, is only suitable for the clock control that a clock gated logic just completes whole storer, not only power dissipation ratio do not adopt the latch arrays of low power dissipation design and register file low, and clock load is very little.Clock easily can drive a huge memory circuit.3. this storer can be expanded very easily, such as when storer is expanded in bit wide, read/write address code translator and clock gated logic can carry out multiplexing, therefore area has been saved to a greater extent, secondly the small-capacity memory of this write once read many can form the multiport memory write more and read more very easily, be used in some specific occasions, in addition this storer well can also adapt to the address decoding mode (embodiment 2 that specifically can see below) of half decode, to reduce the logical block that decoding scheme expends.4. this storer is similar with register file in sequential, allows same storage unit to be read while write, and this is also that simple latch arrays and SRAM memory can not be accomplished.
Accompanying drawing explanation
For illustrating content of the present invention and advantage further, below in conjunction with accompanying drawing and example in detail as rear, wherein:
Fig. 1 is structural representation of the present invention.
Fig. 2 is the structural representation of first embodiment of the invention.
Fig. 3 is the circuit diagram of static ram cell 21 in Fig. 1.
Fig. 4 is the read-write sequence figure of Fig. 2 embodiment.
Fig. 5 is the structural representation of second embodiment of the invention.
Fig. 6 is the structured flowchart that the present invention acts on multi-processor system-on-chip.
Embodiment
Refer to shown in Fig. 1, a kind of on-chip memory of multi-port read-write, comprising:
The three grades of circuit structures connected successively, first order circuit structure 1 is for the gating of the latch and storage unit that input data, and second level circuit structure 2 is for storing in data write storage unit, and tertiary circuit structure 3 is for storing the reading of data, wherein
This first order circuit structure 1 comprises write address code translator 11, clock gated logic circuit 12; And data input latch 13, its input end is connected with the output terminal of clock gated logic circuit 12; Described data input latch 13 has data input pin, and it is input as 1 than feature data, and outputs to each input end of multiple static ram cell 21.Described clock gated logic circuit 12 has input clock end and writes Enable Pin, and described write address code translator 11 is decoded according to write address and write enable signal.
In described storer, the function of first order circuit structure 1 has been the input latch of data and the gating of storage unit, and its detailed process is as follows:
1. clock gated logic circuit 12, controlled by write enable signal and clock signal, when write enable signal is logic low " 0 ", clock gated logic circuit 12 exports as logic low " 0 ", gated clock is closed, when write enable signal is logic high " 1 ", gated clock is switched on again, and the door controling clock signal exported is contrary with input clock signal phase place.
2. when described storer input clock is logic low, when gated clock is logic high, data input latch 13 is sampled to wanting the data of data input pin, when described storer input clock rising edge, data in data input latch 13 are latched, now the data of external data input end are isolated (positive latch thought by latch here, if the negative latch principle of use is similar in this).
3. write address code translator 11 is decoded according to the write address of input and write enable signal, if write enable signal is logic high " 1 ", write address code translator 11 is by OPADD decoded signal, this signal only has the output terminal corresponding with write address effectively (for logic high " 1 "), effective output terminal writes new data by controlling static ram cell 21 corresponding in second level circuit structure 2, if write enable signal is logic low " 0 ", all output is all logic low " 0 ".
Sequential power consumption characteristics in described storer in first order circuit structure 1 is as follows:
1. write enable signal should change when input clock is low level, once write enable signal is logic low " 0 ", all no longer occurrence logic upset of the first order circuit structure 1 of described storer and second level circuit structure 2, enters low power consumpting state.
2. write address and data input all should have been set up during input clock is logic high, and at least a clock period of maintenance changes again, that is write address and data input can not change when input clock low level, generally write address and data input change should with the rising edge synch of input clock.
This second level circuit structure 2 comprises multiple static ram cell 21, its input end is connected with the output terminal of write address code translator 11 and data input latch 13 respectively, the quantity of described static ram cell 21 is more than or equal to 2, each static ram cell 21 in this second level circuit structure 2 described adds a transmission gate switch 213 between two phase inverters 211 and 212 mutually latched, when write control signal is effective, switch disconnects, data input is transparent relative to output, when write control signal is invalid, switch conduction, storer stores signal, what export can only be the data of current storage, have nothing to do with input signal, the grid of this transmission gate switch 213 is connected with the grid of transistor 214, source electrode or the drain electrode of this transistor 214 are connected with the input end of phase inverter 211 (consulting Fig. 3),
The concrete storing process of static ram cell 21 is as follows:
1. when input clock is logic low, when gated clock is logic high, write address and write data and can not change, the write control signal of therefore selected static ram cell 21 is continuously logic high, is now written in this static ram cell 21 by the data that data input latch 13 samples.
2. when storer input clock is logic high, when gated clock is logic low, write address and data input may change during this period, but because data input latch 13 latches data before, so the data in static ram cell 21 corresponding to old write address can not be modified, and the invalid data of static ram cell 21 corresponding to the new write address changed during this period can not be stored, so when write address changes, static ram cell 21 corresponding in old write address, just successfully store the data of one-period write.
This tertiary circuit structure 3 comprises MUX 31, and its input end is connected with each output terminal of multiple static ram cell 21; Read address decoder 32, its output terminal is connected with the input end of MUX 31 respectively; Data output latch 33, its input end is connected with the output terminal of MUX 31, and be subject to the control of clock gating logic circuit 12, several Data output latch 33 described are all connected with described clock gated logic circuit 12, the input clock of each Data output latch is the input clock of described on-chip memory, and the output of each Data output latch is the final sense data of described on-chip memory.
Described MUX 31 is identical with the quantity of Data output latch 33, and its quantity is less than the quantity of static ram cell 21.
Tertiary circuit structure 3 function in described storer has been the reading storing data, and its detailed process is as follows:
Read address and be input to when n (n >=1) is individual and read address decoder 32, produce the gate control signal of n, the static ram cell 21 reading place, address exports data to the input end of Data output latch 33 by the MUX 31 that gate control signal controls, after input clock rising edge, effective data read from Data output latch 33.
The temporal characteristics of tertiary circuit structure 3 is as follows: reading the gate control signal that address decoding obtains can set up during the logic low of a upper clock period, also can after current period rising edge clock, set up and keep stable, as long as meet the maintenance Time Created of Data output latch, but valid reading may be caused bigger than normal according to the delay exported if gate control signal is set up between input clock low period.
Described on-chip memory comprises following input/output port: an input clock, one or more write address, the data input of 1 bit, 1 write enable signal, read address for n, and n 1 bit read data, wherein n is the quantity of Data output latch 33.
Referring to shown in Fig. 2, is first embodiment of the present invention:
Be a FPDP be 1 bit, memory capacity is that one of 4 bits are read one and write dual-ported memory, its composition structure is identical with structural representation shown in Fig. 1, wherein clock gated logic circuit 12 is logical AND gates, data input latch 13 and Data output latch 33 are all positive latch, MUX 31 is by four NMOS transmission gate transistors 311, 312, 313, 314 and a level recover logical circuit 315 and form, 4 NMOS transmission gate transistors 311, 312, 313, the grid of 314 is respectively by gate control signal RD0, RD1, RD2, RD3 controlled.
The port information of storer is as following table one:
| Port title | Port direction | Port bit wide | Port explanation |
| clk | Input | 1 | Storer input clock signal |
| wren | Input | 1 | Storer write enable signal |
| wraddr | Input | 2 | Storer write address |
| rdaddr | Input | 2 | Address read by storer |
| Din | Input | 1 | Data write by storer |
| Dout | Export | 1 | Storer read data |
WL0, WL1, WL2, WL3, RD0, RD1, RD2, RD3 in Fig. 2,-GCLK, DQ are M signal, wherein WL0, WL1, WL2, WL3 are the signal after write address decoding, DQ is that the latch of data input latch 13 exports with sampling,-GCLK is gated clock,-GCLK signal makes data input latch 13 can sample when clk low level, physical relationship is in table two, and the relation between WL0, WL1, WL2, WL3 and wren, wraddr is in table three, RD0, RD1, relation between RD2, RD3 and rdaddr are in table four.
Correspond to logic low " 0 " with the data 0 in following table and in word, data 1 correspond to logic high " 1 ".
Table two is as follows:
| clk | wren | -GCLK |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
Table three is as follows:
| wren | wraddr | WL0 | WL1 | WL2 | WL3 |
| 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 |
| 0 | 2 | 0 | 0 | 0 | 0 |
| 0 | 3 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 1 | 0 | 0 |
| 1 | 2 | 0 | 0 | 1 | 0 |
| 1 | 3 | 0 | 0 | 0 | 1 |
Table four is as follows:
| rdaddr | RD0 | RD1 | RD2 | RD3 |
| 0 | 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 2 | 0 | 0 | 1 | 0 |
| 3 | 0 | 0 | 0 | 1 |
The concrete read-write sequence of storer described in first example following (consulting Fig. 4): clock period 0:wren=0, wraddr=1, raddr=2, WL0=0, WL1=0, the first order of WL2=0, WL3=0 reservoir and the second level all no longer occurrence logic change, and what the 3rd bit memory cell was deposited is 1.Clock period 1:wren=1, wraddr=0, rdaddr=0, after now WL0 becomes 1. rising edges, Dout exports is 1 (storing value of the 3rd bit memory cell), between later half cycle low period, Dout keeps initial value, and input end DQ=Din=0, and Din is write in first storage unit corresponding to WL0.
Clock period 2:wren=1, wraddr=2, now WL0 becomes 0, WL2 becomes 1, rdaddr=2, and after rising edge clock, Dout exports is 0 (storing value of the 1st bit memory cell), between later half cycle low period, Dout keeps initial value, and input end DQ=Din=1, and Din is write in the 3rd bit memory cell corresponding to WL2.Clock period 3:wren=0, wraddr is constant, and rdaddr is constant, and the first order of reservoir and the second level all no longer occurrence logic change, and output data are Dout=1 (storing value of the 3rd bit memory cell).
Referring to shown in Fig. 5, is second embodiment of the present invention:
This embodiment is bit wide 1 bit, and memory capacity is that 2 of 16 bits are read 1 and write multiport memory (see Fig. 5), compares with first embodiment, this embodiment unlike:
1. the decoded mode of write address is half decode mode, high two bit address wraddrH [1:0] and low two bit address wraddrL [1:0] decoding produces 4 respectively address decode signal wrh [0], wrh [1], wrh [2], wrh [3], wrl [0], wrl [1], wrl [2], wrl [3] each signal control 4 storage unit, these 8 signals each other combination of two carry out the storage unit needed for independent strobe, (half decode mode compares fully decoded mode can save a large amount of transistors).
2. in second example owing to there being two read ports, so need two groups of MUX 31, these two groups of MUX 31, the data-out port of common connection 16 static ram cells 21, but receive the gate control signal reading address rdaddr1 [3:0] and rdaddr2 [3:0] respectively, finally distinguish OPADD rdaddr1 [3:0] and rdaddr2 [3:0] stored data.For write port in second example, or any one read port, its temporal aspect and first embodiment are identical.
Referring to shown in Fig. 6, is the structured flowchart that the present invention acts on multi-processor system-on-chip:
It comprises 4 processor cores, 61,62,63,64 and communicating between multi-kernel controller 65, each processor core 61,62,63,64 is interconnected with communicating between multi-kernel controller 65, and it is mutual to there are input and output, comprises an arithmetic logic unit (1bitALU) 611,621,631,641 and storer of the present invention 612,622,632,642 in processor core 61,62,63,64.
This system is owing to adding multiport memory of the present invention, and the arithmetic logic unit 611,621,631,641 in each processor core 61,62,63,64 and communicating between multi-kernel controller 65 can carry out read-write operation to corresponding storer 612,622,632,642 simultaneously.In Fig. 6, the English of part functional part represents the generic representation belonging to those skilled in the art.
The above; be only the embodiment in the present invention, but protection scope of the present invention is not limited thereto, any people being familiar with this technology is in the technical scope disclosed by the present invention; the conversion that can expect easily or replacement, all should be encompassed in of the present invention comprising within scope.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claims.
Claims (6)
1. an on-chip memory for multi-port read-write, comprising:
The three grades of circuit structures connected successively, first order circuit structure is for the gating of the latch and storage unit that input data, and second level circuit structure to be used for store in data write storage unit, tertiary circuit structure for storing the reading of data, wherein,
This first order circuit structure comprises write address code translator, clock gated logic circuit, and data input latch, and its input end is connected with the output terminal of clock gated logic circuit;
This second level circuit structure comprises multiple static ram cell, and its input end is connected with the output terminal of write address code translator and data input latch respectively;
This tertiary circuit structure comprises MUX, and its input end is connected with each output terminal of multiple static ram cell; Read address decoder, its output terminal is connected with the input end of MUX respectively; Data output latch, its input end is connected with the output terminal of MUX;
Described multiple Data output latch is all connected with described clock gated logic circuit, the input clock of each Data output latch is the input clock of the on-chip memory of described multi-port read-write, and the output of each Data output latch is the final sense data of the on-chip memory of described multi-port read-write.
2. the on-chip memory of multi-port read-write as claimed in claim 1, the quantity of wherein said static ram cell is more than or equal to 2.
3. the on-chip memory of multi-port read-write as claimed in claim 1, wherein said MUX is identical with the quantity of Data output latch, and its quantity is more than or equal to 1 and is less than the quantity of static ram cell.
4. the on-chip memory of multi-port read-write as claimed in claim 1, each static ram cell in this second level circuit structure wherein said adds a transmission gate switch between two phase inverters mutually latched, when write control signal is effective, switch disconnects, data input is transparent relative to output, when write control signal is invalid, switch conduction, storer stores signal, what export can only be the data of current storage, have nothing to do with input signal, the grid of this transmission gate switch is connected with the grid of transistor, source electrode or the drain electrode of this transistor are connected with the input end of phase inverter.
5. the on-chip memory of multi-port read-write as claimed in claim 1, wherein said data input latch has data input pin, and it is input as 1 than feature data, and outputs to each input end of multiple static ram cell.
6. by the on-chip memory of multi-port read-write according to claim 1, wherein said on-chip memory comprises following input/output port: an input clock, one or more write address, the data input of 1 bit, 1 write enable signal, read address for n, and n 1 bit read data, wherein n is the quantity of Data output latch.
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| CN107293318B (en) * | 2017-06-24 | 2020-04-10 | 中国电子科技集团公司第五十八研究所 | Bit width configurable embedded memory |
| CN108335707A (en) * | 2018-02-09 | 2018-07-27 | 盛科网络（苏州）有限公司 | A kind of high speed memory designs method and device with mask |
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| CN110688154B (en) * | 2019-09-05 | 2023-02-28 | 上海高性能集成电路设计中心 | Multiport register file based on narrow pulse width domino structure |
| CN110989942A (en) * | 2019-12-30 | 2020-04-10 | 南京信息工程大学滨江学院 | Data storage expansion interface system and control method thereof |
| CN111370040B (en) * | 2020-03-18 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | Memory read data test circuit structure and design method thereof |
| CN112687305A (en) * | 2021-01-05 | 2021-04-20 | 深圳芯邦科技股份有限公司 | Data storage circuit |
| CN112863571B (en) * | 2021-03-03 | 2023-07-07 | 东南大学 | Latch type memory unit with near threshold value and ultra-low leakage and read-write control circuit thereof |
| CN112671395B (en) * | 2021-03-17 | 2021-07-13 | 北京紫光青藤微系统有限公司 | Clock phase selection circuit |
| CN117667777A (en) * | 2022-08-30 | 2024-03-08 | 深圳市中兴微电子技术有限公司 | Memory access control circuit and memory access control method |
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