CN112671395B - Clock phase selection circuit - Google Patents
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- CN112671395B CN112671395B CN202110283402.7A CN202110283402A CN112671395B CN 112671395 B CN112671395 B CN 112671395B CN 202110283402 A CN202110283402 A CN 202110283402A CN 112671395 B CN112671395 B CN 112671395B
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Abstract
The invention provides a clock phase selection circuit which comprises M data acquisition modules, a decoder and a clock selection module. M data acquisition modules respectively acquire instantaneous values of M paths of candidate clocks with sequentially delayed phases at the rising edge moment of the communication field clock and transmit the instantaneous values to a decoder. When the data of the ith input end is 0 and the data of the (i-1) th input end is 1, the decoder sets the data of the (i-1) th output end to be 1 and sets the data of other output ends to be 0. And the clock selection module outputs 1 path of candidate clock corresponding to the output end with the data set as 1 in the M output ends of the decoder as an output clock. The clock phase selection circuit provided by the invention has the advantages that the time for selecting the candidate clocks with similar phases only needs a few cycles of the communication field clock, and compared with the method only using the digital phase-locked loop circuit, the response time for locking the candidate clocks with similar phases according to the phase change of the communication field clock to output is improved.
Description
Technical Field
The present invention relates to the Field of NFC (Near Field Communication) technology, and more particularly, to a clock phase selection circuit.
Background
In the NFC scheme, the reader generates a communication field with a frequency of 13.56 MHz. The NFC card realizes communication with the card reader by reading the strength of a communication field sent by the card reader, and the speed of data sending is synchronous with the frequency of the communication field. This requires that the clock in the NFC card be identical in frequency and phase to the clock of the communication field sent by the reader.
The current common method is to use a digital phase-locked loop to achieve the required clock frequency to be consistent with the clock frequency of the communication field. However, the phase adjustment of the digital phase-locked loop is a very slow process, and if the phase of the communication field clock changes, the digital phase-locked loop cannot be locked to the same phase as the communication field clock in a short time. When the phase of the communication field changes suddenly, the phase of the digital phase-locked loop will deviate for a long time.
Disclosure of Invention
In view of the above, the present invention provides a clock phase selection circuit for quickly responding to a change of a clock phase of a communication field.
In order to achieve the above object, the following solutions are proposed:
a clock phase selection circuit, comprising:
the system comprises M data acquisition modules, a clock acquisition module, a clock synchronization module and a clock synchronization module, wherein the M data acquisition modules are used for respectively acquiring instantaneous values of M paths of candidate clocks at the rising edge moment of a communication field clock, the frequency of each path of candidate clock is N times of the frequency of the communication field clock, N is a positive integer, the phase of the ith path of candidate clock lags behind the phase of the (i-1) path of candidate clock by T/M, i =0, 1, … … and M-1, and T is the period of the candidate clock;
the decoder comprises M input ends and M output ends, wherein the ith input end of the decoder is connected with the output end of the ith data acquisition module; the decoder is used for setting the data of the (i-1) th output end as 1 and setting the data of other output ends as 0 when the data of the (i) th input end is 0 and the data of the (i-1) th input end is 1;
and the clock selection module is used for outputting the 1-path candidate clock corresponding to the output end with the data set as 1 in the M output ends of the decoder as an output clock.
Preferably, the clock selection module includes:
m clock selection submodules, an OR gate and a NOT gate;
each clock selection submodule comprises a first-stage register, a second-stage register, a latch and an AND gate;
the OR gate includes M input ports;
the bit input port of the first-level register of the ith clock selection submodule is connected with the ith output port of the decoder, the input clock port of each first-level register is connected with the communication field clock, and the bit output port of the first-level register of the ith clock selection submodule is connected with the bit input port of the second-level register of the ith clock selection submodule;
the bit input port of the latch of the ith clock selection submodule is connected with the bit output port of the second-stage register of the ith clock selection submodule, and the input clock port of the latch of the ith clock selection submodule is connected with the ith candidate clock;
one input end of an AND gate of the ith clock selection submodule is connected with a bit output port of a latch of the ith clock selection submodule, the other input end of the AND gate of the ith clock selection submodule is connected with an ith candidate clock, and the output end of the AND gate of the ith clock selection submodule is connected with an ith input port of the OR gate;
and the output port of the OR gate is connected with the input clock port of the second-stage register of each clock selection submodule through the NOT gate.
Preferably, the data acquisition module includes:
cascaded two-level registers or three-level registers.
Preferably, the decoder includes:
each decoding unit comprises four bit input ports, a bit enable input port, a bit decoding result port and a bit enable output port, and data output by the bit enable output port is data obtained by performing non-operation on data output by the bit decoding result port;
a first bit input port of an ith decoding unit is connected with an i-1 th input end of the decoder, a second bit input port of the ith decoding unit is connected with an i-th input end of the decoder, a third bit input port of the ith decoding unit is connected with an i +1 th input end of the decoder, a fourth bit input port of the ith decoding unit is connected with an i +2 th input end of the decoder, a bit enable input port of the ith decoding unit is connected with a bit enable output port of the i-1 th decoding unit, and a bit decoding result port of the ith decoding unit is connected with an i-th output end of the decoder;
and when the data of the first bit input port and the second bit input port of the ith decoding unit are both 1, the data of the third bit input port and the fourth bit input port are both 0, and the data of the bit enable input port is 1, setting the data of the bit decoding result port of the ith decoding unit to be 1.
Preferably, the decoding unit includes:
the system comprises three NOT gates and an AND gate, wherein the AND gate comprises five input ports;
a first input port of the AND gate is a bit enable input port of the decoding unit, a second input port is a first bit input port of the decoding unit, a third input port is a second bit input port of the decoding unit, a fourth input port is connected with an output port of the first NOT gate, a fifth input port is connected with an output port of the second NOT gate, and the output port is a bit decoding result port of the decoding unit;
the input end of the first NOT gate is a third bit input port of the decoding unit;
the input end of the second NOT gate is a fourth bit input port of the decoding unit;
the input end of the third not gate is connected with the output port of the and gate, and the output end of the third not gate is the bit enable output port of the decoding unit.
Preferably, the decoder includes:
each decoding unit comprises two bit input ports, a bit enable input port, a bit decoding result port and a bit enable output port, and data output by the bit enable output port is data obtained by performing non-operation on data output by the bit decoding result port;
a first bit input port of the ith decoding unit is connected with an ith input end of the decoder, a second bit input port of the ith decoding unit is connected with an (i + 1) th input end of the decoder, a bit enable input port of the ith decoding unit is connected with a bit enable output port of the (i-1) th decoding unit, and a bit decoding result port of the ith decoding unit is connected with an ith output end of the decoder;
when the data of the first bit input port of the ith decoding unit is 1, the data of the second bit input port is 0, and the data of the bit enable input port is 1, the data of the bit decoding result port of the ith decoding unit is 1.
Preferably, the decoding unit includes:
the system comprises two NOT gates and an AND gate, wherein the AND gate comprises three input ports;
the first input port of the AND gate is a bit enable input port of the decoding unit, the second input port is a first bit input port of the decoding unit, the third input port is connected with the output port of the first NOT gate, and the output port is a bit decoding result port of the decoding unit;
the input end of the first NOT gate is a second bit input port of the decoding unit;
the input end of the second NOT gate is connected with the output port of the AND gate, and the output end of the second NOT gate is the bit enable output port of the decoding unit.
Preferably, N is 2.
Preferably, the clock phase selection circuit is applied to an NFC card.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the clock phase selection circuit provided by the technical scheme comprises M data acquisition modules, a decoder and a clock selection module. M data acquisition modules respectively acquire instantaneous values of M paths of candidate clocks with sequentially delayed phases at the rising edge moment of the communication field clock and transmit the instantaneous values to a decoder. When the data of the ith input end is 0 and the data of the (i-1) th input end is 1, the decoder sets the data of the (i-1) th output end to be 1 and sets the data of other output ends to be 0. And the clock selection module outputs 1 path of candidate clock corresponding to the output end with the data set as 1 in the M output ends of the decoder as an output clock. The clock phase selection circuit provided by the invention has the advantages that the time for selecting the candidate clocks with similar phases only needs a few cycles of the communication field clock, and compared with the method only using the digital phase-locked loop circuit, the response time for locking the candidate clocks with similar phases according to the phase change of the communication field clock to output is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of a clock phase selection circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a clock phase selection circuit for 36 candidate clocks according to an embodiment of the present invention;
FIG. 3 is a timing diagram of an internal signal according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a decoder according to an embodiment of the present invention;
FIG. 5 is a diagram of a four-input decoding unit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another decoder according to an embodiment of the present invention;
FIG. 7 is a diagram of a two-input decoding unit according to an embodiment of the present invention;
fig. 8 is a schematic diagram of various clock signals provided by the embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a clock phase selection circuit provided in this embodiment includes: m data acquisition modules 11, a decoder 12 and a clock selection module 13. ClkiRepresenting the i-th candidate clock, CR representing the communication field clock, qiIndicating the presence of the ith candidate clockThe instantaneous value of the rising edge time of the communication field clock, CO, represents the output clock. q. q.siIf the current value is 0, the current value indicates that the rising edge time of the communication field clock of the ith path of candidate clock is low level; q. q.siA 1 indicates that the i-th candidate clock is at a high level at the time of the rising edge of the communication field clock.
Each data acquisition module 11 is configured to acquire an instantaneous value of one candidate clock at a rising edge time of the communication field clock. Different data acquisition modules 11 acquire instantaneous values of different candidate clocks. The frequency of each path of candidate clock is N times of the communication field clock, and N is a positive integer. The phase of the ith candidate clock lags behind the phase of the (i-1) th candidate clock by T/M. In the invention, i =0, 1, … … and M-1, and T is the period of the candidate clock. When i =0, the phase lag of the i-th candidate clock from the i-1-th candidate clock indicates that the phase lag of the 0-th candidate clock from the M-1-th candidate clock is T/M. The M candidate clocks are generated by a digital phase-locked loop circuit according to the communication field clock CR. The generated M candidate clocks are M candidate clocks with a phase interval T/M. The value of M is not limited in the present invention and can be selected by those skilled in the art according to the actual accuracy requirement.
The decoder 12 includes M inputs and M outputs. The ith input end of the decoder 12 is connected with the output end of the ith data acquisition module. The decoder is used for setting the data of the (i-1) th output end to be 1 and setting the data of other output ends to be 0 when the data of the (i) th input end is 0 and the data of the (i-1) th input end is 1. When i =0, it indicates that the decoder sets the data of the M-1 output terminal to 1 and sets the data of each of the other output terminals to 0 when the data of the 0 th input terminal is 0 and the data of the M-1 th input terminal is 1. And when the data of the ith input end is 0 and the data of the (i-1) th input end is 1, the phase of the communication field clock is between the phase of the (i-1) th candidate clock and the phase of the k-th candidate clock.
And the clock selection module 13 is configured to output, as an output clock, the 1-channel candidate clock corresponding to the output end whose data is set to 1 in the M output ends of the decoder. Specifically, if the data in the ith output end of the decoder is set to 1, the clock selection module 13 outputs the ith candidate clock as the output clock.
The data acquisition module 11 is specifically formed by a register. The register is a standard circuit device and comprises a bit input port (indicated by D), an input clock port and a bit output port (indicated by Q). The registers adopted in the invention are all rising edge trigger registers; the function of the rising edge triggered register is: on the rising edge of the input clock, the data of the bit input port is stored to the bit output port, which is equivalent to collecting and holding the data of D to Q. For the rising edge trigger register, the input signal and the input clock should meet a requirement, that is, the input signal should be kept stable within a tiny time range (about hundreds of picoseconds) before and after the rising edge of the input clock; otherwise, if the input signal changes during this period, the output data may be unstable, and even an intermediate level that is not high or low may be output. In order to ensure the stability of the output data of the register, in some specific embodiments, the data acquisition module 11 is configured by acquiring cascaded two-stage registers or three-stage registers, that is, after the data is acquired by using the first-stage register, the result of the previous-stage register is acquired at least once by using the same clock, and if the unstable state occurs in the first-stage acquisition, the probability of instability during the reacquisition is very low, which can meet the design requirement.
Referring to fig. 2, a clock phase selection circuit for 36 candidate clocks is shown, along with a preferred implementation of the data acquisition module 11, and a preferred implementation of the clock selection module 13. The data acquisition module 11 in fig. 2 adopts a cascaded two-stage register mode. The clock selection module 13 includes 36 clock selection submodules 131, an or gate 132, and a not gate 133. 36-way candidate clock Clki(i =0, 1, … …, 35), the period of each candidate clock is T, and the phase of each candidate clock lags the phase of the previous candidate clock by T/36.
Each clock selection submodule 131 includes a first stage register, a second stage register, a latch, and an and gate. Or gate 132 includes M input ports.
The bit input port of the first-stage register of the ith clock selection submodule 131 is connected to the ith output port of the decoder 12; the input clock port of each first-stage register is connected with a communication field clock; the bit output port of the first-level register of the ith clock selection submodule 131 is connected to the bit input port of the second-level register of the ith clock selection submodule 131. deciRepresenting the data value, en, of the ith output port of the decoder 12iRepresenting the data value of the bit output port of the first level register of the ith clock select submodule 131.
The bit input port of the latch of the ith clock selection submodule 131 is connected with the bit output port of the second-stage register of the ith clock selection submodule 131; the input clock port of the latch of the ith clock selection submodule 131 is connected to the ith candidate clock. The latch is a standard circuit device and comprises a bit input port, an input clock port and a bit output port; the function of the latch is: when the input clock is at low level, the data of the bit input port is directly output to the bit output port, and when the input clock is at high level, the previous value is kept unchanged by the bit output port. den (r)iRepresenting the data value of the bit output port of the second level register of the ith clock select submodule 131.
One input end of the and gate of the ith clock selection submodule 131 is connected to the bit output port of the latch of the ith clock selection submodule 131; the other input end of the and gate of the ith clock selection submodule 131 is connected with the ith candidate clock; the output of the and gate of the ith clock selection submodule 131 is connected to the ith input port of the or gate 132. The output port of the or gate 132 is connected to the input clock port of the second stage register of each clock selection submodule 131 through the not gate 133. Gate (gate)iA data value, gclk, representing the bit output port of the latch of the ith clock selection submodule 131iRepresenting the data value at the output of the and gate of the ith clock selection submodule 131,
representing the inverted clock obtained after the logical negation of CO.
The ith clock selection submodule 131 uses CR as the input clock of the first stage register to collect the ith output dec of the decoderiEn obtainedi(ii) a Backward clock using output clock CO
As input clock for the second stage register, pair eniCollecting to obtain a collected result deniApproximately synchronized with the candidate clock to be selected. ClkiAs the input clock of the latch, the latch is performed to obtain the gatei. Due to the fact that in the deni(i =0, 1, … … 35), only one value is "1", and the rest are all "0"; and deciApproximately synchronous with the candidate clock to be selected, so that the latch result is also only "1" all the way. Latching the result gate with each wayiClk respectively corresponding to local pathiPerforming an AND operation; then the result gclk obtained from each pathiThen the result of the OR operation is output as CO; since only one way has a "1" latch result, only the candidate clock for that way is selected for output as CO.
Since the decoder 12 is made up of a series of circuits, each circuit and connection has a time delay, and after passing through a complex decoder circuit, the output dec of the decoder 120~dec35There may be delays of different degrees, making it difficult to obtain stable results simultaneously; possibly dec0Has been changed from "0" to "1", and dec1A case where "1" has not changed to "0". Therefore if the latch is used directly to latch dec0~dec35Since each latch uses a different candidate clock as the input clock, and dec0~dec35Cannot guarantee simultaneous change, so there is a possibility that the acquisition value gate is generated0~gate35There are multiple disallowed cases where "1" is simultaneously or all are "0". Aiming at the technical problem, the ith clock selection submodule 13 in the invention1 Collection dec with first stage register0~dec35Because the register in the ith data acquisition module 11 and the first-stage register of the ith clock selection submodule 131 both use CR as the input clock, it is further ensured that dec is set at the rising edge of CR0~dec35Has stabilized, the obtained collection value en0~en35Are varied simultaneously.
Next, en0~en35The phase is synchronous with the rising edge of the CR, and if the rising edge acquisition of the candidate clock is directly used, the unstable state problem can be caused because the phase cannot be ensured. The invention aims at the technical problem, a second-stage register is used, and an input clock of the second register uses a reverse clock. Because the frequency of the candidate clock is an integral multiple of CR, the candidate clock selected at each rising edge of CR basically does not change greatly with the previous time, and is probably not changed, or is adjacent to the previous time; i.e. the phase difference between the selected candidate clock and the output clock CO is small, so that the falling edge of CO is used to acquire en0~en35On the one hand, the unstable change can be avoided, and en is collected0~en35On the other hand, the obtained en0~en35The location of the output change is not near the rising edge of the candidate clock to be selected.
As shown in fig. 3, the timing diagram of the internal signals is shown. In the initial state, the circuit uses the Clk35As an output clock CO; on the rising edge of CR, the phase of CR changes, en35From "1" to "0", en0From "0" to "1", and the other eniAlways remains "0". en is a radical of35And en0The value of (d) is collected at the falling edge of CO35And den0At this time Clk35Is low, so den35Is transmitted to gate35，gate35Changes from "1" to "0" and holds. While in Clk0When it goes low, den0Is transmitted to gate0，gate0Changes from "0" to "1" and holds. At this point the circuit has changed to use Clk0As an output clock CO. ByAs can be seen in FIG. 3, in this process, en is avoided due to the addition of the second stage register of clock select submodule 13135And en0Is quickly changed by Clk0A possible unstable state of rising edge acquisition.
Fig. 4 is a schematic structural diagram of a decoder according to this embodiment. The decoder is used for selecting from 36 paths of candidate clocks, and therefore comprises 36 decoding units, and each decoding unit is a four-input decoding unit, namely each decoding unit comprises four bit input ports (respectively represented by Ai, Bi, Ci and Di) and one bit enabling input port (represented by Ai, Bi, Ci and Di)
Representation), one bit decode result port (in
Represented) and a bit enable output port (in use)
Representation). The data output by the bit enable output port is the data output by the bit decoding result port after non-operation. The instantaneous values of the continuous four candidate clocks are judged through the four-input decoding unit, and the stability of clock selection is enhanced.
The first bit input port Ai of the ith decoding unit is connected with the (i-1) th input end of the decoder. The second bit input port Bi of the ith decoding unit is connected with the ith input end of the decoder. And the third bit input port Ci of the ith decoding unit is connected with the (i + 1) th input end of the decoder. The fourth bit input port Di of the ith decoding unit is connected to the (i + 2) th input terminal of the decoder. Bit enable input port of ith decoding unit
Bit enable output port connected to the i-1 th decoding unit
. Bit decoding result port of ith decoding unit
Connected to the ith output terminal of the decoder. When i =0, i-1 represents M-1; for example, in the case shown in fig. 4, i =0, i-1 indicates 35, and the first bit input port Ai of the 0 th decoding unit is connected to the 35 th input terminal of the decoder. Bit enable input port of 0 th decoding unit
Connecting the 35 th decoding unit bit enable output port
. When i = M-1, i +1 represents 0, i +2 represents 1; exemplarily, in the case of fig. 4, when i =35, i +1 denotes 0, and i +2 denotes 1; the third bit input port Ci of the 35 th decoding unit is connected with the 0 th input end of the decoder; the fourth bit input port Di of the 35 th decoding unit is connected to the 1 st input port of the decoder.
The data of the first bit input port Ai and the second bit input port Bi of the ith decoding unit are both 1, the data of the third bit input port Ci and the fourth bit input port Di are both 0, and the bit enable input port
When the data of (1) is 1, the bit decoding result port of the ith decoding unit
The data of (1) is set to 1.
Bit decoding result port of ith decoding unit
When the data of (1) is set, the bit of the ith decoding unit enables the output port
Is 0, so that the bit decoding result port of the (i + 1) th decoding unit
The data of (1) is set to 0.
Referring to fig. 5, a schematic diagram of a four-input decoding unit according to the present embodiment is shown. The four-input decoding unit comprises: three not gates and one and gate. The and gate includes five input ports. The first input port of the AND gate is a bit enable input port of the decoding unit
The second input port is a first bit input port Ai of the decoding unit, the third input port is a second bit input port Bi of the decoding unit, the fourth input port is connected with the output port of the first NOT gate, the fifth input port is connected with the output port of the second NOT gate, and the output port is a bit decoding result port of the decoding unit
. The input end of the first NOT gate is a third bit input port Ci of the decoding unit; the input end of the second not gate is a fourth bit input port Di of the decoding unit; the input end of the third NOT gate is connected with the output port of the AND gate, and the output end of the third NOT gate is the bit enable output port of the decoding unit
。
Referring to fig. 6, a schematic structural diagram of another decoder provided in this embodiment is shown. The decoder is used for selecting from 36 candidate clocks, and therefore comprises 36 decoding units, and each decoding unit is a two-input decoding unit, namely each decoding unit comprises two bit input ports (respectively Ai and Bi) and one bit enable input port (respectively
Representation), one bit decode result port (in
Represented) and a bit enable output port (in use)
Representation). The data output by the bit enable output port is the data output by the bit decoding result port after non-operation.
The first bit input port Ai of the ith decoding unit is connected with the ith input end of the decoder. The second bit input port Bi of the ith decoding unit is connected with the (i + 1) th input end of the decoder. Bit enable input port of ith decoding unit
Bit enable output port connected to the i-1 th decoding unit
. Bit decoding result port of ith decoding unit
And is connected to the ith output end of the decoder. When i =0, i-1 represents M-1; illustratively, in the case shown in fig. 6, when i =0, i-1 indicates 35, and the bit enable input port of the 0 th decoding unit
Connecting the 35 th decoding unit bit enable output port
. When i = M-1, i +1 represents 0; for example, in the case shown in fig. 6, when i =35, i +1 represents 0, and the second bit input port Bi of the 35 th decoding unit is connected to the 0 th input port of the decoder.
When the data of the first bit input port of the ith decoding unit is 1, the data of the second bit input port is 0, and the data of the bit enable input port is 1, the data of the bit decoding result port of the ith decoding unit is 1.
Referring to fig. 7, a schematic diagram of a two-input decoding unit according to the present embodiment is shown. The two-input decoding unit comprises two NOT gates and an AND gate. The and gate includes three input ports. The first input port of the AND gate is a bit enable input port of the decoding unit
The second input port is a first bit input port Ai of the decoding unit, the third input port is connected with the output port of the first NOT gate, and the output port is a bit decoding result port of the decoding unit
. The input end of the first NOT gate is a second bit input port Bi of the decoding unit; the input end of the second NOT gate is connected with the output port of the AND gate, and the output end of the second NOT gate is the bit enable output port of the decoding unit
。
The clock phase selection circuit provided by the invention can be applied to an NFC card. In some embodiments, N is 2, i.e., each candidate clock is generated at twice the frequency of the communication field clock.
Referring to fig. 8, a schematic diagram of the respective clock signals is shown when the candidate clock is 36-way. The 36-way time selection clocks are respectively Clk0~Clk35The period of each candidate clock is T. Clk1Phase ratio Clk of0Time delayed by T/36, Clk2Phase ratio Clk of1Lag by T/36, and so on, Clk0Phase ratio of (Clk)35Time lag T/36; the period of the communication field clock is 2T. The clock phase selection circuit selects a candidate clock which is before the rising edge of CR and is closest to the phase of CR as an output clock CO. Examples of the inventionAlternatively, if the rising edge of CR is at Clk35Rising edge of and Clk0Between rising edges, Clk is then set35As an output clock CO.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The embodiments in the present description are mainly described as different from other embodiments, the same and similar parts in the embodiments may be referred to each other, and the features described in the embodiments in the present description may be replaced with each other or combined with each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A clock phase selection circuit, comprising:
the system comprises M data acquisition modules, a clock acquisition module, a clock synchronization module and a clock synchronization module, wherein the M data acquisition modules are used for respectively acquiring instantaneous values of M paths of candidate clocks at the rising edge moment of a communication field clock, the frequency of each path of candidate clock is N times of the frequency of the communication field clock, N is a positive integer, the phase of the ith path of candidate clock lags behind the phase of the (i-1) path of candidate clock by T/M, i =0, 1, … … and M-1, and T is the period of the candidate clock;
the decoder comprises M input ends and M output ends, wherein the ith input end of the decoder is connected with the output end of the ith data acquisition module; the decoder is used for setting the data of the (i-1) th output end as 1 and setting the data of other output ends as 0 when the data of the (i) th input end is 0 and the data of the (i-1) th input end is 1;
the clock selection module is used for outputting 1 path of candidate clocks corresponding to the output end with the data set as 1 in the M output ends of the decoder as output clocks;
the clock selection module comprises:
m clock selection submodules, an OR gate and a NOT gate;
each clock selection submodule comprises a first-stage register, a second-stage register, a latch and an AND gate;
the OR gate includes M input ports;
the bit input port of the first-level register of the ith clock selection submodule is connected with the ith output port of the decoder, the input clock port of each first-level register is connected with the communication field clock, and the bit output port of the first-level register of the ith clock selection submodule is connected with the bit input port of the second-level register of the ith clock selection submodule;
the bit input port of the latch of the ith clock selection submodule is connected with the bit output port of the second-stage register of the ith clock selection submodule, and the input clock port of the latch of the ith clock selection submodule is connected with the ith candidate clock;
one input end of an AND gate of the ith clock selection submodule is connected with a bit output port of a latch of the ith clock selection submodule, the other input end of the AND gate of the ith clock selection submodule is connected with an ith candidate clock, and the output end of the AND gate of the ith clock selection submodule is connected with an ith input port of the OR gate;
and the output port of the OR gate is connected with the input clock port of the second-stage register of each clock selection submodule through the NOT gate.
2. The clock phase selection circuit of claim 1, wherein the data acquisition module comprises:
cascaded two-level registers or three-level registers.
3. The clock phase selection circuit of claim 1, wherein the decoder comprises:
each decoding unit comprises four bit input ports, a bit enable input port, a bit decoding result port and a bit enable output port, and data output by the bit enable output port is data obtained by performing non-operation on data output by the bit decoding result port;
a first bit input port of an ith decoding unit is connected with an i-1 th input end of the decoder, a second bit input port of the ith decoding unit is connected with an i-th input end of the decoder, a third bit input port of the ith decoding unit is connected with an i +1 th input end of the decoder, a fourth bit input port of the ith decoding unit is connected with an i +2 th input end of the decoder, a bit enable input port of the ith decoding unit is connected with a bit enable output port of the i-1 th decoding unit, and a bit decoding result port of the ith decoding unit is connected with an i-th output end of the decoder;
and when the data of the first bit input port and the second bit input port of the ith decoding unit are both 1, the data of the third bit input port and the fourth bit input port are both 0, and the data of the bit enable input port is 1, setting the data of the bit decoding result port of the ith decoding unit to be 1.
4. The clock phase selection circuit of claim 3, wherein the decode unit comprises:
the system comprises three NOT gates and an AND gate, wherein the AND gate comprises five input ports;
a first input port of the AND gate is a bit enable input port of the decoding unit, a second input port is a first bit input port of the decoding unit, a third input port is a second bit input port of the decoding unit, a fourth input port is connected with an output port of the first NOT gate, a fifth input port is connected with an output port of the second NOT gate, and the output port is a bit decoding result port of the decoding unit;
the input end of the first NOT gate is a third bit input port of the decoding unit;
the input end of the second NOT gate is a fourth bit input port of the decoding unit;
the input end of the third not gate is connected with the output port of the and gate, and the output end of the third not gate is the bit enable output port of the decoding unit.
5. The clock phase selection circuit of claim 1, wherein the decoder comprises:
each decoding unit comprises two bit input ports, a bit enable input port, a bit decoding result port and a bit enable output port, and data output by the bit enable output port is data obtained by performing non-operation on data output by the bit decoding result port;
a first bit input port of the ith decoding unit is connected with an ith input end of the decoder, a second bit input port of the ith decoding unit is connected with an (i + 1) th input end of the decoder, a bit enable input port of the ith decoding unit is connected with a bit enable output port of the (i-1) th decoding unit, and a bit decoding result port of the ith decoding unit is connected with an ith output end of the decoder;
when the data of the first bit input port of the ith decoding unit is 1, the data of the second bit input port is 0, and the data of the bit enable input port is 1, the data of the bit decoding result port of the ith decoding unit is 1.
6. The clock phase selection circuit of claim 5, wherein the decode unit comprises:
the system comprises two NOT gates and an AND gate, wherein the AND gate comprises three input ports;
the first input port of the AND gate is a bit enable input port of the decoding unit, the second input port is a first bit input port of the decoding unit, the third input port is connected with the output port of the first NOT gate, and the output port is a bit decoding result port of the decoding unit;
the input end of the first NOT gate is a second bit input port of the decoding unit;
the input end of the second NOT gate is connected with the output port of the AND gate, and the output end of the second NOT gate is the bit enable output port of the decoding unit.
7. The clock phase selection circuit of claim 1, wherein N is 2.
8. The clock phase selection circuit of claim 1, wherein the clock phase selection circuit is applied to an NFC card.
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