CN113778335B

CN113778335B - Control method of multi-port low-delay access SRAM group in SSD master control

Info

Publication number: CN113778335B
Application number: CN202111049650.1A
Authority: CN
Inventors: 付溢华
Original assignee: Shandong Sinochip Semiconductors Co Ltd
Current assignee: Shandong Sinochip Semiconductors Co Ltd
Priority date: 2021-09-08
Filing date: 2021-09-08
Publication date: 2024-03-08
Anticipated expiration: 2041-09-08
Also published as: CN113778335A

Abstract

The invention discloses a control method of a multi-port low-delay access SRAM group in an SSD main control, which divides the SRAM into a plurality of groups in the SSD main control with multiple ports, each group is provided with an arbiter and a group controller, the arbiter realizes the mapping of the access address of each port, and simultaneously allocates which port can access the SRAM in the group or controls the sequence of which port accesses the group of SRAM. The method sets mapping of discontinuous address space, namely that SRAM physical addresses corresponding to continuous logical addresses are discontinuous, and when ports carry out continuous address reading and writing of large data quantity, access paths are mapped in different groups of SRAMs in sequence. The method effectively solves the problem that a single port occupies a storage space for a long time and the problem that multiple ports access SRAM groups in parallel under the condition of less resource consumption, and realizes the trade-off between the problem of port occupation and high-efficiency parallel access.

Description

Control method of multi-port low-delay access SRAM group in SSD master control

Technical Field

The invention relates to the field of storage, in particular to a control method of an SRAM group with multi-port low-delay access in an SSD master control.

Background

A Static Random-Access Memory (SRAM) is a volatile Memory, and has characteristics of Static state, high speed, and the like, and the SRAM is currently mostly suitable for the fields of cache, and the like, due to the low integration level, high cost, and the like.

In order to meet the storage and access requirements of a certain data volume, a Solid State Disk (SSD) is often in a form of a combination of multiple SRAMs to realize a storage capacity with a larger depth. At this time, the SRAM controller is designed for allocation of memory addresses so as to correspond the access of data to SRAM physical addresses. When a single master accesses the SRAM group, the SRAM controller can realize data transmission by only acquiring the address accessed by the master and read/write data. However, in SSD, the memory area formed by SRAM groups often requires multiple interfaces to be accessed in parallel to improve performance. At this time, it is required that the address spaces accessed by each interface at the same time cannot overlap to prevent access data from being covered or a scramble from occurring. Simply implementing the translation of access addresses in an SRAM controller has not been satisfactory.

When the SRAM controller has a plurality of master ports, it is necessary to allocate access paths and access orders of the interfaces by configuring the arbiter to the SRAM, thereby ensuring that the same address can be accessed by only one interface. For SRAM groups, it is a worth discussing how many arbiters are configured: if all the SRAMs share the same arbiter, when a plurality of ports access to non-overlapping address ranges, the arbiter is only allocated to one port for use, so that the access speed is rapidly reduced; if an arbiter is configured for each SRAM in the group, once the number of SRAMs is too large, a large number of arbiters will cause space occupation and resource waste.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a control method for multi-port low-delay access SRAM group in SSD master control, which carries out grouping management on SRAM according to a certain rule, effectively solves the problem that a single port occupies a storage space for a long time and the problem that the multi-port access SRAM group is accessed in parallel under the condition of less resource consumption, and realizes the trade-off between the problem of port occupation and high-efficiency parallel access.

In order to solve the technical problems, the invention adopts the following technical scheme: a control method of a multi-port low-delay access SRAM group in an SSD master is characterized by comprising the following steps: dividing SRAM into a plurality of groups in an SSD main control with multiple ports, wherein each group is provided with an arbiter and a group controller, the arbiter realizes mapping of access addresses of each port and simultaneously allocates which port can access the SRAM in the group or controls the sequence of which port accesses the group of SRAM; all SRAMs in the same group are only accessed by a unique port at the same time under the management of the arbiter, and meanwhile, each group of SRAMs are mutually independent and can be accessed by different ports at the same time because each group of SRAMs has the own arbiter;

the method sets the mapping of the discontinuous address space, namely that the physical address of the SRAM corresponding to the continuous logical address is discontinuous, when the port carries out continuous address reading and writing of large data quantity, the access paths are mapped in different groups of SRAMs in sequence, and even if one port carries out long-time data access, the reading and writing of other ports are not blocked for a long time, so that the reading and writing speed is improved.

Further, the arbiters of each group of SRAMs are connected to all or part of the ports of the group controller.

Further, the arbiter manages access to different ports, including priority and access order of each port.

Further, the group controller is connected between the arbiter and the plurality of SRAMs in the group, and the group controller manages the SRAMs in the group, including allocation of SRAM physical addresses, timing control of each access, and processing of access data.

Further, the allocation of the group controller to the SRAM physical address includes sequential mapping of the access logical address to the SRAM physical address and non-sequential mapping of the access logical address to the SRAM physical address.

Further, the timing control of each access by the group controller includes real-time access and delayed access.

Further, the processing of the access data by the group controller includes that the data is directly read from or directly written into the SRAM, the access data is written into the SRAM after a certain logic calculation, or the access data and the original data in the SRAM are subjected to a certain logic calculation and are written into the SRAM when the access data are read out of the group controller and are subjected to a write access.

Further, the discontinuous mapping relation between the external logic address and the SRAM physical address is expressed as: for a set of consecutive external logical addresses A0-AN, A0-AN1 are mapped to physical addresses corresponding to the group controller USRAMx, A (n1+1) -AN2 are mapped to physical addresses corresponding to the group controller USRAMx', wherein，/>，，/>，/>M is a natural integer set,where m is the total number of group controllers, when a segment of continuous external logical address is mapped to the same group controller, the segment of address is defined as the same group of continuous space, and the same group of continuous space corresponds to the SRAM physical addresses which are arranged continuously or intermittently.

Further, the same group of consecutive spaces is mapped to the same SRAM or different SRAMs within the same group.

Further, when the external logical address spans multiple same-group continuous spaces, the corresponding SRAM physical address is located in multiple group controllers.

The invention has the beneficial effects that: in the traditional technical scheme, the SRAM controller sequentially arranges the SRAMs, and adopts continuous external logic addresses to sequentially access the physical addresses of the SRAMs, so that only single-port access can be realized, and the access transmission speed of data is greatly limited.

By the method, the physical address space is accessed by adopting multiple ports, so that parallel data transmission is realized, and the access speed is greatly improved. Based on the multiport structure, the patent divides the SRAM into a plurality of groups for different ports to access different physical addresses at the same time. Meanwhile, in order to avoid long-time occupation of a certain port to the same group, the mode of discontinuous mapping of an external logic address and an SRAM physical address is adopted, so that balance of access performance of each port is realized, and the SRAM access efficiency is further improved.

Drawings

FIG. 1 is a schematic diagram of SRAM packet management and discontinuous address mapping.

Detailed Description

The invention will be further described with reference to the drawings and the specific examples.

Example 1

The embodiment discloses a control method for a multi-port low-delay access SRAM group in SSD, which sets a form of grouping SRAM for realizing parallel access of the multi-port to the SRAM group and reducing the number of arbiters. Meanwhile, in order to reduce the long-time occupation of a port to a certain storage space to a greater extent, a management mode of discontinuous address mapping is adopted.

In an SRAM controller having multiple ports, the SRAM is divided into multiple groups, each group being configured with an arbiter. At this time, all SRAMs in the same group are only accessible by a unique port at the same time, as managed by the arbiter. The arbiter can implement mapping of access addresses for each port while assigning which port can access to the SRAM in the group or controlling in which order the ports access the group of SRAMs. Each group of SRAM is provided with an arbiter, so that each group of SRAM is independent and can be accessed by different ports at the same time in parallel.

An important role of SRAM controllers is the mapping of the logical addresses accessed to the SRAM physical addresses, i.e., the port logical addresses are often not equivalent to the SRAM physical addresses, but rather the SRAM controller is required to map both to determine the locations in the SRAM that need to be accessed. Each port is often oriented to a series of contiguous spaces of addresses when accessing large amounts of data, while SRAM physical addresses are also typically arranged sequentially. Therefore, when the port makes access to a large amount of data on consecutive addresses, there is still a case where a certain group of SRAMs is occupied for a long time.

Therefore, the invention sets the mapping of the discontinuous address space, namely the discontinuous SRAM physical address corresponding to the continuous logical address. When the port performs continuous address reading and writing of a large data volume, the access paths are mapped in different groups of SRAMs in sequence. Therefore, even if one port performs long-time data access, the read-write of other ports is not blocked for a long time, so that the read-write speed is improved.

FIG. 1 is a schematic block diagram of the present embodiment, wherein first, an SRAM controller can implement packet management and discontinuous address mapping of an SRAM; the SRAM controller includes a port M for communicating with an external device, an arbiter Arb, and a group controller USRAM, and a series of SRAMs (k) are controlled by M USRAMs, each of which controls n SRAMs. Wherein,，/>，。

second, each USRAM is configured with a separate arbiter Arb, each of which can be connected to the controller port M. The arbiter may connect all ports of the controller or some ports.

Thirdly, the arbiter receives the access information of each connected port and maps the access path to the corresponding USRAM, thereby realizing the allocation of the access of each port and the storage space of the module.

Fourth, the arbiter is capable of managing access to different ports, including but not limited to priority and access order of the ports.

Fifth, the group controller USRAM can implement control of the corresponding n SRAMs, including, but not limited to, allocation of SRAM physical addresses, timing control of each access, and processing of access data.

Sixth, when the group controller USRAM performs SRAM physical address allocation, the access logical address input by the group controller may be mapped with the SRAM physical address sequentially, or may be mapped in a non-sequential manner.

Seventh, when the group controller USRAM performs timing control on the input access, the group controller USRAM may simultaneously perform access to the SRAM or may perform delay access.

Eighth, regarding the processing manner of the group controller USRAM for the access data, the processing manner includes, but is not limited to, directly reading or directly writing the data from or into the SRAM, writing the access data into or out of the group controller after performing certain logic calculation, performing certain logic calculation on the access data and the original data in the SRAM during the write access to obtain new data, and writing the new data into the SRAM.

Ninth, the SRAM controller may perform discontinuous mapping on the external logical address received by the port and the SRAM physical address, that is, the difference between the external logical address and the SRAM physical address is a non-fixed value.

Tenth, the discontinuous mapping relationship between the external logical address and the SRAM physical address is expressed as for a group of continuous external logical addressesA0-AN, A0-AN1 is mapped to the physical address corresponding to the group controller USRAMx, A (n1+1) -AN2 is mapped to the physical address corresponding to the group controller USRAMx', wherein，/>，，/>，/>M, M is a natural integer set.

Eleventh, when a segment of consecutive external logical addresses are all mapped to the same group controller, the segment addresses are defined as the same set of consecutive spaces.

Twelfth, the physical addresses of the SRAMs corresponding to the same group of continuous spaces can be arranged continuously or discontinuously.

Thirteenth, the plurality of same group continuous spaces mapped to the same group controller may be arranged continuously or discontinuously in the corresponding SRAM physical addresses; may be mapped to the same SRAM within the group controller or may be mapped to a different SRAM within the group controller.

Fourteenth, when the external logical address spans multiple identical groups of contiguous space, the corresponding SRAM physical address is located in multiple group controllers.

The foregoing description is only of the basic principles and preferred embodiments of the present invention, and modifications and alternatives thereto will occur to those skilled in the art to which the present invention pertains, as defined by the appended claims.

Claims

1. A control method of a multi-port low-delay access SRAM group in an SSD master is characterized by comprising the following steps: dividing SRAM into a plurality of groups in an SSD main control with multiple ports, wherein each group is provided with an arbiter and a group controller, the arbiter realizes mapping of access addresses of each port and simultaneously allocates which port can access the SRAM in the group or controls the sequence of which port accesses the group of SRAM; all SRAMs in the same group are only accessed by a unique port at the same time under the management of the arbiter, and meanwhile, each group of SRAMs are mutually independent and can be accessed by different ports at the same time because each group of SRAMs has the own arbiter;

the method sets the mapping of the discontinuous address space, namely that the physical address of the SRAM corresponding to the continuous logical address is discontinuous, when the port carries out continuous address reading and writing of large data quantity, the access paths are mapped in different groups of SRAMs in sequence, and even if one port carries out long-time data access, the reading and writing of other ports are not blocked for a long time, so that the reading and writing speed is improved;

the group controller is connected between the arbiter and a plurality of SRAMs in the group, and the group controller realizes the management of the SRAMs in the group and comprises the allocation of SRAM physical addresses, the time sequence control of each access and the processing of access data;

the non-continuous mapping relation between the external logical address and the SRAM physical address is expressed as follows: for a set of consecutive external logical addresses A0-AN, A0-AN1 are mapped to the group controller USRAM&In the physical address corresponding to-x, A (n1+1) -An2 is mapped to the group controller USRAM&-x' corresponds to a physical address, wherein，/>，/>,，/>M is a natural integer set, wherein M is the total number of group controllers, and when a section of continuous external logical addresses are mapped to the same group controller, the section of addresses are defined as SRAM physical addresses which are arranged continuously or discontinuously in the same group of continuous spaces.

2. The method for controlling the multi-port low-delay access SRAM group in the SSD master of claim 1, wherein: the arbiters of each group of SRAMs are connected to all or part of the ports of the group controller.

3. The method for controlling the multi-port low-delay access SRAM group in the SSD master of claim 2, wherein: the arbiter manages access to the different ports, including priority and access order of the ports.

4. The method for controlling the multi-port low-delay access SRAM group in the SSD master of claim 1, wherein: the allocation of the group controller to the SRAM physical addresses includes sequential mapping of the access logical addresses to the SRAM physical addresses and non-sequential mapping of the access logical addresses to the SRAM physical addresses.

5. The method for controlling the multi-port low-delay access SRAM group in the SSD master of claim 1, wherein: the timing control of each access by the group controller includes real-time access and delayed access.

6. The method for controlling the multi-port low-delay access SRAM group in the SSD master of claim 1, wherein: the group controller processes the access data including the data directly read from or directly written into the SRAM, the access data is logically calculated and then written into the SRAM or read out of the group controller, and the access data and the original data in the SRAM are logically calculated to obtain new data and written into the SRAM during the write access.

7. The method for controlling the multi-port low-delay access SRAM group in the SSD master of claim 1, wherein: the same set of contiguous spaces maps to the same SRAM or different SRAMs within the same group.

8. The method for controlling the multi-port low-delay access SRAM group in the SSD master of claim 1, wherein: when the external logical address spans multiple same groups of continuous spaces, the corresponding SRAM physical address is located in multiple group controllers.