CN109656626B - SD card data self-carrying method and device based on AHB bus - Google Patents
SD card data self-carrying method and device based on AHB bus Download PDFInfo
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- CN109656626B CN109656626B CN201811511244.0A CN201811511244A CN109656626B CN 109656626 B CN109656626 B CN 109656626B CN 201811511244 A CN201811511244 A CN 201811511244A CN 109656626 B CN109656626 B CN 109656626B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Abstract
The invention belongs to the technical field of integrated circuit design, and provides an SD card data self-carrying method and device based on an AHB bus. The invention realizes the functions of loading codes from the outside of the processor chip and starting the processor chip by designing the self-starting circuit. The technology increases a self-starting function and simplifies the ROM hardware overhead of the self-starting in the chip.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design and provides an SD card data self-carrying method and device based on an AHB bus.
Background
The traditional chip self-starting function is to load the code and data of the starting software solidified in the low-speed ROM in the chip into the high-speed RAM, and then the code and data are loaded by the processor to realize self-starting. The code and data of the starting software cannot be changed, and the flexibility is lacked; and when the code and data of the starting software are more, the ROM area is large, and the internal area of the chip is occupied.
Disclosure of Invention
The invention provides an AHB bus-based SD card data self-carrying method and device, which load self-starting codes from an off-chip SD card through a self-starting circuit to achieve the effect of reducing the hardware overhead of a ROM.
The first invention, the embodiment of the invention provides a secure digital SD card data self-handling method based on advanced high-performance bus AHB, the method is applied to SD card data self-handling circuit, the circuit comprises a clock enabling module 1, an SD card initialization module 2, a direct memory access DMA enabling module 3 and an arbitration module 4, the method comprises:
the clock enabling module 1 receives a starting signal;
the arbitration module 4 enables the clock enabling module 1 to work according to the state of the controller of the SD card;
the clock enabling module 1 completes the initialization of the SD card controller;
the arbitration module 4 enables the SD card initialization module 2 to work according to the state of the SD card controller;
the SD card initialization module 2 completes the initialization operation of the SD card;
the arbitration module 4 enables the DMA enabling module 3 to start working according to the state of the SD card controller;
the DMA enable module 3 completes DMA enable, thereby completing data transfer.
Optionally, the clock enabling module 1 is implemented by a first state machine, where the first state machine includes an idle state, a write operation control signal sending state, a write operation data signal sending state, a write operation completion state, a read control signal sending state, a read idle state, a read operation detection state, and a clock enabling completion state, where:
in an idle state, when a clock enable signal is high, entering a write operation control signal sending state; when the clock enable signal is low, keeping an idle state;
in a write operation control signal sending state, the SD card data self-handling circuit sends a write control signal to a controller of the SD card through an AHB bus, and sends different control commands according to different write count values;
in a write operation data signal sending state, the SD card data self-handling circuit sends a data signal to the controller through the AHB data bus;
under the state of completing the write operation, completing the detection of the read signal of the slave equipment, and if the read signal of the slave equipment is high, respectively entering different states according to different write count values; if the slave device reading signal is low, continuously keeping the write operation completion state until the slave device reading signal is high;
in the read control signal sending state, the SD card data self-carrying circuit sends a read control signal to the controller through an AHB bus;
in a read idle state, no operation is performed;
under the state of reading operation detection, finishing the detection of a slave device reading signal, when the slave device reading signal is high, detecting the read data, if the read matching information of the SD card controller is established, then jumping to the state of writing operation control signal transmission by the state machine, and if the read matching information of the SD card controller is not established, entering the state of reading control signal transmission and continuing to read the register; when the slave read signal is low, the read operation detection state continues to be maintained until the slave read signal is high.
In the clock enable complete state, the controller completes internal and external clock enables.
Optionally, the SD card initialization module 2 is implemented by a second state machine, where the second state machine includes an idle state, a write operation control signal sending state, a write operation data signal sending state, a write operation completion state, a read control signal sending state, a read idle state, a read operation detection state, and a card initialization completion state, where:
in the idle state, when the initialization signal of the SD card is high, the SD card enters the idle state; when the initialization signal of the SD card is low, keeping an idle state;
in a write operation control signal sending state, the SD card data self-handling circuit sends a write control signal to the controller through an AHB bus, and sends different control commands according to different write count values;
in a write operation data signal sending state, the SD card data self-carrying circuit sends a data signal to the controller through the AHB data bus;
under the state of completing the write operation, completing the detection of the read signal of the slave equipment, and if the read signal of the slave equipment is high, respectively entering different states according to different write count values; if the slave device read signal is low, continuing to maintain the write complete state until the slave device read signal is high;
and in the read control signal sending state, the SD card data self-handling circuit sends a read control signal to the controller through the AHB. And sending different reading control commands according to different reading count values;
in a read idle state, no operation is performed;
under the state of reading operation detection, finishing the detection of a slave device reading signal, when the slave device reading signal is high, detecting the read data, if the read matching information of the SD card controller is established, jumping to a corresponding state according to the read count value, and if the read matching information of the SD card controller is not established, entering a state of reading control signal transmission and continuously reading the register; when the slave read signal is low, continuing to maintain the read operation detection state until the slave read signal is high;
in the initialization completion state of the card, the controller completes the initialization and selection operations of the card.
Optionally, the DMA enable module 3 is implemented by a third state machine, where the third state machine includes an idle state, a write operation control signal sending state, a write operation data signal sending state, a write operation completion state, a read control signal sending state, a read idle state, a read operation detection state, and a DMA initialization completion state, where:
in the idle state, when the DMA initialization signal is high, entering a write operation control signal sending state, and when the DMA initialization signal is low, keeping the idle state;
in the write operation control signal sending state, the SD card data self-handling circuit sends a write control signal to the controller through an AHB bus, and sends a corresponding control command according to different write count values;
in a write operation data signal sending state, the SD card data self-carrying circuit sends a data signal to the controller through the AHB data bus;
under the state of completing the write operation, completing the detection of the read signal of the slave equipment, and if the read signal of the slave equipment is high, respectively entering the corresponding states according to different write count values; if the slave device read signal is low, continuing to maintain the write complete state until the slave device read signal is high;
in the read control signal sending state, the SD card data self-handling circuit sends a read control signal to the controller through an AHB bus, and sends a corresponding read control command according to different read count values;
in a read idle state, no operation is performed;
under the state of reading operation detection, finishing the detection of a slave device reading signal, when the slave device reading signal is high, detecting the read data, if the read matching information of the SD card controller is established, jumping to a corresponding state according to the read count value at the moment, if the read matching information of the SD card controller is not established, entering a state of reading control signal transmission to continuously read the register, and when the slave device reading signal is low, continuously keeping the state of reading operation detection until the slave device reading signal is high;
and in the DMA initialization completion state, the controller completes the DMA initialization and carry operation.
The second invention provides an SD card data self-handling device based on AHB bus, which includes a clock enabling module 1, an SD card initializing module 2, a DMA enabling module 3, and an arbitration module 4, wherein the arbitration module 4 is respectively connected to the clock enabling module 1, the SD card initializing module 2, and the DMA enabling module 3, the clock enabling module 1 is connected to the SD card initializing module 2, and the SD card initializing module 2 is connected to the DMA enabling module 3.
The invention mainly aims to provide a method and a device for self-carrying data of an AHB bus SD card, and reduces the hardware expense of a ROM (read only memory) by designing a circuit and a method for realizing self-starting of an on-chip processor chip by loading a starting code from the outside of a chip.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for self-carrying data based on an AHB bus SD card according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an SD card data self-handling device based on an AHB bus according to an embodiment of the present invention.
Detailed Description
The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and the specific embodiments. It is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than the whole embodiments, and that all other embodiments, which can be derived by a person skilled in the art without inventive step based on the embodiments of the present invention, belong to the scope of protection of the present invention.
Example one
The embodiment of the invention provides a secure digital SD card data self-carrying method based on an advanced high-performance bus AHB, which is applied to an SD card data self-carrying circuit, wherein the circuit comprises a clock enabling module (1), an SD card initialization module (2), a Direct Memory Access (DMA) enabling module (3) and an arbitration module (4). As shown in fig. 1, the method includes:
step 101: the clock enabling module (1) receives a starting signal;
step 102: the arbitration module (4) enables the clock enabling module (1) to work according to the state of the controller of the SD card;
step 103: the clock enabling module (1) completes the initialization of the SD card controller;
step 104: the arbitration module (4) enables the SD card initialization module (2) to work according to the state of the SD card controller;
step 105: the SD card initialization module (2) completes the initialization operation of the SD card;
step 106: the arbitration module (4) enables the DMA enabling module (3) to start working according to the state of the SD card controller;
step 107: the DMA enabling module (3) completes DMA enabling, thereby completing data handling.
Optionally, the circuit of the clock enable module (1) is implemented by a first state machine, where the first state machine includes an idle state, a write operation control signal sending state, a write operation data signal sending state, a write operation completion state, a read control signal sending state, a read idle state, a read operation detection state, and a clock enable completion state, where:
in an idle state, when a clock enable signal is high, entering a write operation control signal sending state; when the clock enable signal is low, keeping an idle state;
in a write operation control signal sending state, the SD card data self-handling circuit sends a write control signal to a controller of the SD card through an AHB bus, and sends different control commands according to different write count values;
in a write operation data signal sending state, the SD card data self-carrying circuit sends a data signal to the controller through the AHB data bus;
under the state of completing the write operation, completing the detection of the read signal of the slave equipment, and if the read signal of the slave equipment is high, respectively entering different states according to different write count values; if the slave device reading signal is low, continuously keeping the write operation completion state until the slave device reading signal is high;
in the read control signal sending state, the SD card data self-carrying circuit sends a read control signal to the controller through an AHB bus;
in a read idle state, no operation is performed;
under the state of reading operation detection, finishing the detection of a slave device reading signal, when the slave device reading signal is high, detecting the read data, if the read matching information of the SD card controller is established, then jumping to the state of writing operation control signal transmission by the state machine, and if the read matching information of the SD card controller is not established, entering the state of reading control signal transmission and continuing to read the register; when the slave read signal is low, the read operation detection state continues to be maintained until the slave read signal is high.
In the clock enable complete state, the controller completes internal and external clock enables.
Optionally, the SD card initialization module (2) is implemented by a second state machine, where the second state machine includes an idle state, a write operation control signal sending state, a write operation data signal sending state, a write operation completion state, a read control signal sending state, a read idle state, a read operation detection state, and a card initialization completion state, where:
in the idle state, when the initialization signal of the SD card is high, the SD card enters the idle state; when the initialization signal of the SD card is low, keeping an idle state;
in the write operation control signal sending state, the SD card data self-handling circuit sends a write control signal to the controller through an AHB bus, and sends different control commands according to different write count values;
in a write operation data signal sending state, the SD card data self-carrying circuit sends a data signal to the controller through the AHB data bus;
under the state of completing the write operation, completing the detection of the read signal of the slave equipment, and if the read signal of the slave equipment is high, respectively entering different states according to different write count values; if the slave device read signal is low, continuing to maintain the write complete state until the slave device read signal is high;
and in the read control signal sending state, the SD card data self-handling circuit sends a read control signal to the controller through the AHB. And sending different reading control commands according to different reading count values;
in a read idle state, no operation is performed;
under the state of reading operation detection, finishing the detection of a slave device reading signal, when the slave device reading signal is high, detecting the read data, if the read matching information of the SD card controller is established, jumping to a corresponding state according to the read count value, and if the read matching information of the SD card controller is not established, entering a state of reading control signal transmission and continuously reading the register; when the slave read signal is low, continuing to maintain the read operation detection state until the slave read signal is high;
in the initialization completion state of the card, the controller completes the initialization and selection operations of the card.
Optionally, the DMA enable module (3) circuit is implemented by a third state machine, where the third state machine includes an idle state, a write operation control signal transmission state, a write operation data signal transmission state, a write operation completion state, a read control signal transmission state, a read idle state, a read operation detection state, and a DMA initialization completion state, where:
in the idle state, when the DMA initialization signal is high, entering a write operation control signal sending state, and when the DMA initialization signal is low, keeping the idle state;
in the write operation control signal sending state, the SD card data self-handling circuit sends a write control signal to the controller through an AHB bus, and sends a corresponding control command according to different write count values;
in a write operation data signal sending state, the SD card data self-carrying circuit sends a data signal to the controller through the AHB data bus;
under the state of completing the write operation, completing the detection of the read signal of the slave equipment, and if the read signal of the slave equipment is high, respectively entering the corresponding states according to different write count values; if the slave device read signal is low, continuing to maintain the write complete state until the slave device read signal is high;
in the read control signal sending state, the SD card data self-handling circuit sends a read control signal to the controller through an AHB bus, and sends a corresponding read control command according to different read count values;
in a read idle state, no operation is performed;
under the state of reading operation detection, finishing the detection of a slave device reading signal, when the slave device reading signal is high, detecting the read data, if the read matching information of the SD card controller is established, jumping to a corresponding state according to the read count value at the moment, if the read matching information of the SD card controller is not established, entering a state of reading control signal transmission to continuously read the register, and when the slave device reading signal is low, continuously keeping the state of reading operation detection until the slave device reading signal is high;
and in the DMA initialization completion state, the controller completes the DMA initialization and carry operation.
Example two
The embodiment of the invention provides an AHB bus-based SD card data self-carrying device, which comprises a clock enabling module (1), an SD card initializing module (2), a DMA enabling module (3) and an arbitration module (4), wherein the arbitration module (4) is respectively connected with the clock enabling module (1), the SD card initializing module (2) and the DMA enabling module (3), the clock enabling module (1) is connected with the SD card initializing module (2), and the SD card initializing module (2) is connected with the DMA enabling module (3).
Specifically, when the enable signal is valid, firstly, the clock enable module (1) starts to work, and secondly, the arbitration module (4) enables the clock enable module (1) to obtain the circuit control right according to the state of the SD card controller. After the clock enabling module (1) obtains the circuit control right, the SD card controller master device clock is enabled through the arbitration module (4) until the controller internal clock is stable. Then, the master device clock is divided to generate an SD card clock, and a matching voltage is selected. Power is then supplied to the card, enabling the SD clock. And then the arbitration module (4) continues to enable the SD card initialization module (2) to obtain the circuit control right according to the state of the SD card controller. After the SD card initialization module (2) obtains the circuit control right, a command is firstly sent to the controller through the arbitration module (4) to enable the card to be in an empty state. The card type is then determined and the operating voltage is configured. And finally, acquiring CID (card identification number), acquiring RCA (relative address) and selecting the card. And then the arbitration module (4) continues to enable the DMA enabling module (3) to obtain the circuit control right according to the state of the SD card controller. After the DMA enabling module (3) obtains the circuit control right, an enabling register, a data volume register and a status register of the controller are firstly configured through an arbitration module (4). Then, the block size is set and a read command is sent. And finally, reading the data in the SD card to the inside of the chip through an AHB bus by the self-starting circuit.
In addition, when the enable signal is invalid, the internal data of the SD card is normally read by the CPU through the AHB bus.
Claims (2)
1. A secure digital SD card data self-carrying method based on an advanced high-performance bus AHB is characterized in that: the method is applied to an SD card data self-handling circuit, the circuit comprises a clock enabling module, an SD card initialization module, a DMA enabling module and an arbitration module, and the method comprises the following steps:
the clock enabling module receives a starting signal;
the arbitration module enables the clock enabling module to work according to the state of the controller of the SD card;
the clock enabling module completes the initialization of the SD card controller;
the arbitration module enables the SD card initialization module to work according to the state of the SD card controller;
the SD card initialization module completes the initialization operation of the SD card;
the arbitration module enables the DMA enabling module to start working according to the state of the SD card controller;
the DMA enabling module completes DMA enabling so as to complete data transportation;
the clock enabling module circuit is realized by a first state machine, the first state machine comprises an idle state, a write operation control signal sending state, a write operation data signal sending state, a write operation completion state, a read control signal sending state, a read idle state, a read operation detection state and a clock enabling completion state, wherein:
in an idle state, when a clock enable signal is high, entering a write operation control signal sending state; when the clock enable signal is low, keeping an idle state;
in a write operation control signal sending state, the SD card data self-handling circuit sends a write control signal to a controller of the SD card through an AHB bus, and sends different control commands according to different write count values;
in a write operation data signal sending state, the SD card data self-carrying circuit sends a data signal to the controller through the AHB data bus;
under the state of completing the write operation, completing the detection of the read signal of the slave equipment, and if the read signal of the slave equipment is high, respectively entering different states according to different write count values; if the slave device reading signal is low, continuously keeping the write operation completion state until the slave device reading signal is high;
in the read control signal sending state, the SD card data self-carrying circuit sends a read control signal to the controller through an AHB bus;
in a read idle state, no operation is performed;
under the state of reading operation detection, finishing the detection of a slave device reading signal, when the slave device reading signal is high, detecting the read data, if the read matching information of the SD card controller is established, then jumping to the state of sending a writing operation control signal by a state machine, and if the read matching information of the SD card controller is not established, entering the state of sending a reading control signal to continuously read the register; when the slave read signal is low, continuing to maintain the read operation detection state until the slave read signal is high;
in the clock enable complete state, the controller completes internal and external clock enables;
the SD card initialization module circuit is realized by a second state machine, the second state machine comprises an idle state, a write operation control signal sending state, a write operation data signal sending state, a write operation completion state, a read control signal sending state, a read idle state, a read operation detection state and a card initialization completion state, wherein:
in the idle state, when the initialization signal of the SD card is high, the SD card enters the idle state; when the initialization signal of the SD card is low, keeping an idle state;
in the write operation control signal sending state, the SD card data self-handling circuit sends a write control signal to the controller through an AHB bus, and sends different control commands according to different write count values;
in a write operation data signal sending state, the SD card data self-carrying circuit sends a data signal to the controller through the AHB data bus;
under the state of completing the write operation, completing the detection of the read signal of the slave equipment, and if the read signal of the slave equipment is high, respectively entering different states according to different write count values; if the slave device read signal is low, continuing to maintain the write complete state until the slave device read signal is high;
in the read control signal sending state, the SD card data self-carrying circuit sends a read control signal to the controller through an AHB bus; and sending different reading control commands according to different reading count values;
in a read idle state, no operation is performed;
under the state of reading operation detection, finishing the detection of a slave device reading signal, when the slave device reading signal is high, detecting the read data, if the read matching information of the SD card controller is established, jumping to a corresponding state according to the read count value at the moment, and if the read matching information of the SD card controller is not established, entering a state of reading a control signal and continuing to read the register; when the slave read signal is low, continuing to maintain the read operation detection state until the slave read signal is high;
in the initialization completion state of the card, the controller completes the initialization and selection operation of the card;
the DMA enable module circuit is implemented by a third state machine, which includes an idle state, a write operation control signal transmission state, a write operation data signal transmission state, a write operation completion state, a read control signal transmission state, a read idle state, a read operation detection state, and a DMA initialization completion state, wherein:
in the idle state, when the DMA initialization signal is high, entering a write operation control signal sending state, and when the DMA initialization signal is low, keeping the idle state;
in the write operation control signal sending state, the SD card data self-handling circuit sends a write control signal to the controller through an AHB bus, and sends a corresponding control command according to different write count values;
in a write operation data signal sending state, the SD card data self-carrying circuit sends a data signal to the controller through the AHB data bus;
under the state of completing the write operation, completing the detection of the read signal of the slave equipment, and if the read signal of the slave equipment is high, respectively entering the corresponding states according to different write count values; if the slave device read signal is low, continuing to maintain the write complete state until the slave device read signal is high;
in the read control signal sending state, the SD card data self-handling circuit sends a read control signal to the controller through an AHB bus, and sends a corresponding read control command according to different read count values;
in a read idle state, no operation is performed;
under the state of reading operation detection, finishing the detection of a slave device reading signal, when the slave device reading signal is high, detecting the read data, if the read matching information of the SD card controller is established, jumping to a corresponding state according to the read count value at the moment, if the read matching information of the SD card controller is not established, entering a reading control signal sending state to continue reading a register, and when the slave device reading signal is low, continuously keeping the reading operation detection state until the slave device reading signal is high;
and in the DMA initialization completion state, the controller completes the DMA initialization and carry operation.
2. An AHB bus-based SD card data self-handling device, which is applied to the advanced high-performance bus-based AHB bus secure digital SD card data self-handling method as claimed in claim 1:
the device comprises a clock enabling module, an SD card initializing module, a DMA enabling module and an arbitration module, wherein the arbitration module is respectively connected with the clock enabling module, the SD card initializing module and the DMA enabling module, the clock enabling module is connected with the SD card initializing module, and the SD card initializing module is connected with the DMA enabling module.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1434137A1 (en) * | 2002-12-23 | 2004-06-30 | STMicroelectronics S.r.l. | Bus architecture with primary bus and secondary bus for microprocessor systems |
| CN101071405A (en) * | 2006-05-08 | 2007-11-14 | 中兴通讯股份有限公司 | Asynchrous AHB interconnection matrix interface device |
| CN103309828A (en) * | 2013-05-31 | 2013-09-18 | 杭州晟元芯片技术有限公司 | SD (secure digital) card subordinate controller and control method thereof |
| CN104679681A (en) * | 2015-03-18 | 2015-06-03 | 山东华芯半导体有限公司 | High-speed bridge device for AHB (advanced high-performance bus) accessing on-chip SRAM (static random access memory) and operating method of high-speed bridge device |
| EP2546757B1 (en) * | 2011-07-14 | 2015-06-24 | LSI Corporation | Flexible flash commands |
| CN105573947A (en) * | 2014-10-13 | 2016-05-11 | 北京自动化控制设备研究所 | APB (Advanced Peripheral Bus) based SD/MMC (Secure Digital/ MultiMedia Card) control method |
| CN106874224A (en) * | 2017-02-17 | 2017-06-20 | 杭州朔天科技有限公司 | The multi-thread SPI Flash controllers of automatic transporting and adaptation device |
| CN107729271A (en) * | 2017-10-26 | 2018-02-23 | 中国电子科技集团公司第五十八研究所 | Possess the dual bus type E FLASH control circuits of self-test function |
| CN208126378U (en) * | 2018-05-21 | 2018-11-20 | 安徽集弘物联科技有限公司 | A kind of 40GBPS-SSD control equipment |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8719485B2 (en) * | 2008-06-27 | 2014-05-06 | Marvell World Trade Ltd. | Solid-state disk with wireless functionality |
| US10289577B2 (en) * | 2016-05-11 | 2019-05-14 | New York University | System, method and computer-accessible medium for low-overhead security wrapper for memory access control of embedded systems |
-
2018
- 2018-12-11 CN CN201811511244.0A patent/CN109656626B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1434137A1 (en) * | 2002-12-23 | 2004-06-30 | STMicroelectronics S.r.l. | Bus architecture with primary bus and secondary bus for microprocessor systems |
| CN101071405A (en) * | 2006-05-08 | 2007-11-14 | 中兴通讯股份有限公司 | Asynchrous AHB interconnection matrix interface device |
| EP2546757B1 (en) * | 2011-07-14 | 2015-06-24 | LSI Corporation | Flexible flash commands |
| CN103309828A (en) * | 2013-05-31 | 2013-09-18 | 杭州晟元芯片技术有限公司 | SD (secure digital) card subordinate controller and control method thereof |
| CN105573947A (en) * | 2014-10-13 | 2016-05-11 | 北京自动化控制设备研究所 | APB (Advanced Peripheral Bus) based SD/MMC (Secure Digital/ MultiMedia Card) control method |
| CN104679681A (en) * | 2015-03-18 | 2015-06-03 | 山东华芯半导体有限公司 | High-speed bridge device for AHB (advanced high-performance bus) accessing on-chip SRAM (static random access memory) and operating method of high-speed bridge device |
| CN106874224A (en) * | 2017-02-17 | 2017-06-20 | 杭州朔天科技有限公司 | The multi-thread SPI Flash controllers of automatic transporting and adaptation device |
| CN107729271A (en) * | 2017-10-26 | 2018-02-23 | 中国电子科技集团公司第五十八研究所 | Possess the dual bus type E FLASH control circuits of self-test function |
| CN208126378U (en) * | 2018-05-21 | 2018-11-20 | 安徽集弘物联科技有限公司 | A kind of 40GBPS-SSD control equipment |
Non-Patent Citations (1)
| Title |
|---|
| 基于AHB总线的SD/SDHC/MMC控制器设计;王宁等;《微电子学与计算机》;20100131;第99-101、105页 * |
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