CN108897696A - A kind of high-capacity FIFO controller based on DDRx memory - Google Patents
A kind of high-capacity FIFO controller based on DDRx memory Download PDFInfo
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Abstract
The invention discloses a kind of high-capacity FIFO controllers based on DDRx memory, and by memory package one or more asynchronous FIFO control module, and asynchronous FIFO control module is connect by memory interface time-sequence control module with memory；The asynchronous FIFO control module includes：Write port synchronization module, read port synchronization module, write port access request module, read port access request module, read-write pointer management module and Port Scheduling poller module.It is asynchronous FIFO control unit interface by memory package, when using memory as FIFO data buffering, while guaranteeing has memory large capacity space, high bandwidth characteristic, application interface is simplified.
Description
Technical field
The invention belongs to fifo controller architecture technology fields；More particularly to a kind of large capacity based on DDRx memory
Fifo controller.
Background technique
Currently, FPGA adds the data of DDR2/DDR3 memory in most of electronic product Project design implementation process
Cache structure is more and more applied.Although FPGA manufacturer both provides greatly the IP kernel of DDRx controller, for
For FPGA design personnel, it is desired nonetheless to do a large amount of FPGA digital logic circuit design work to complete data processing and DDRx
The function of controller internal interface timing, this not only increases the design difficulty of project it is also possible to influencing project process.
The scheme that existing disclosed technology proposes is FPGA connection two panels DDRx chip, is realized using the mode of ping-pong operation
Data continuous data transmission, this method have the waste of cache resources and the increase of logical design difficulty in many situations.
FPGA supplier provides the controller IP of the DDRx interface based on fifo interface for its part FPGA, but it is controlled
Timing is complex, and be only capable of using with the specific fpga chip of several moneys, do not have versatility
Summary of the invention
The present invention provides a kind of high-capacity FIFO controllers based on DDRx memory；It is asynchronous by memory package
Fifo controller interface is guaranteeing DDRx memory large capacity, high band when using memory as FIFO data buffering
While wide characteristic, application interface is simplified.
The technical scheme is that：A kind of high-capacity FIFO controller based on DDRx memory, by memory package
One or more asynchronous FIFO control modules, and asynchronous FIFO control module passes through Port Scheduling poller module and memory interface
Time-sequence control module is connect with memory；The asynchronous FIFO control module includes：The synchronous mould of write port synchronization module, read port
Block, write port access request module, read port access request module and read-write pointer management module；Write port synchronization module, will
The data that the fifo controller is written are synchronized on memory interface time-sequence control module by Port Scheduling poller module；Read end
The data of the fifo controller are passed through Port Scheduling poller module by mouth synchronization module from memory interface time-sequence control module
It reads and is cached；Write port access request module obtains write port synchronization module and needs to be written to the data in memory
Number, and to Port Scheduling poller module initiate write access request；It is synchronous to obtain read port for read port access request module
Module can read the number of the data in memory, and initiate read access request to Port Scheduling poller module；Port tune
Poller module is spent, each asynchronous FIFO control module of poll reads or writes access request to memory；Memory interface timing control
Molding block, the read or write request of response asynchronous FIFO control module, and the memory block DDRx is accessed accordingly.
Further, the features of the present invention also characterized in that：
Wherein asynchronous FIFO control module further includes read-write pointer management module, and read-write pointer management module completes the FIFO
The pointer operation of controller read or write, and calculate the number of the data in the fifo controller；Carrying out reading or writing for data
After operation, read-write pointer management module carries out the update and to the read-write of memory of the data amount check in the fifo controller
The update of location.
The data wherein read in read port synchronization module are that will read and write the data of pointer management module read pointer direction.
Write port synchronization module is wherein obtained in write port access request module needs to be written to the data in memory
The process of number is：The number n for needing the data transmitted is obtained, when the remaining space of memory can store n data, then
The data amount check of the write request of write port request module output is n；When the remaining space of memory can store m data, and m
<N, then the data amount check of the write request of write port request module output is m.
Wherein read port access request module obtains the data that can be written in read port synchronization module in memory
The detailed process of number is：The number x for needing the data transmitted is obtained, when the remaining space in read port synchronization module can be deposited
When putting x data, then the data amount check of the read request of read port access request module output is x；When in read port synchronization module
Remaining space when can store y data, and y<X, the then data amount check for the read request that read port access request module exports
For y.
Wherein memory interface time-sequence control module reads the data in memory in corresponding read operation, and is written
In read port synchronization module.
Wherein memory interface time-sequence control module reads the data in write port synchronization module in corresponding write operation
Out, it and is written in memory.
Compared with prior art, the beneficial effects of the invention are as follows：The asynchronous FIFO interface phase of the fifo controller and standard
Together, Universal joint, simple, it is easy to use；The present invention uses burst transfer and the pipeline design technology, i.e., is connect using memory
Mouth time-sequence control module and the realization of Port Scheduling poller module are polled read-write operation to multiple asynchronous FIFO control modules, mention
The high efficiency of transmission of data, ensure that the read and write access high bandwidth of memory；Fifo controller of the invention be configured to 1 or
Multiple asynchronous FIFO control modules, configuration is flexible, the usage scenario suitable for different bandwidth.
Detailed description of the invention
Fig. 1 is the structural diagram of the present invention.
In figure：1 is write port synchronization module；2 be read-write pointer management module；3 be write port access request module；4 are
Read port access request module；5 be read port synchronization module；6 be Port Scheduling poller module；7 be the control of memory interface timing
Molding block.
Specific embodiment
Technical solution of the present invention is further illustrated in the following with reference to the drawings and specific embodiments.
The present invention provides a kind of high-capacity FIFO controller based on DDRx memory, including one or more are asynchronous
FIFO control module, asynchronous FIFO control module by Port Scheduling poller module 6 and memory interface time-sequence control module 7 with
Memory connection.As shown in Figure 1, there are two asynchronous FIFO control modules for the fifo controller in the embodiment.
As shown in Figure 1, asynchronous FIFO control module includes port synchronization module 1, read port synchronization module 5, write port visit
Ask request module 3, read port access request module 4 and read-write pointer management module 2.
Wherein, write port synchronization module 1 is used to the data that the fifo controller is written being synchronized to memory interface timing
Under control module 7, and it is written in memory；The module is realized by an asynchronous FIFO control module, when write port is synchronous
When the data that module 1 needs to be written meet the condition of write-in DDRx, Port Scheduling poller module 6 will be in write port synchronization module 1
Data, read and be simultaneously written in memory by memory interface time-sequence control module 7.
The data (i.e. read pointer be directed toward data) that read port synchronization module 5 is used to need to read by the fifo controller from
It reads and is cached in memory；The module is realized by an asynchronous FIFO control module, when user needs to control from the FIFO
When reading data in device processed, user is read data by operating read port synchronization module 5.
Write port access request module 3 passes through the number judged in data amount check and memory in write port synchronization module 1
According to the data timeout case in number and write port synchronization module, calculates the needs of write port synchronization module 1 and be written to storage
Data amount check in device, and DDRx write access request is initiated to Port Scheduling poller module 6.
Write port synchronization module 1 is wherein obtained in write port access request module 3 needs to be written to the data in memory
The process of number be：The number n for needing the data transmitted is obtained, when the remaining space of memory can store n data,
The data amount check for the write request that then write port request module 3 exports is n；When the remaining space of memory can store m data,
And m<N, the then data amount check for the write request that write port request module 3 exports are m.
Read port access request module 4 passes through the number judged in data amount check and memory in read port synchronization module 5
According to the data timeout case in number and memory, calculating be can be written into memory 5 in read port synchronization module
Data amount check, and DDRx read access request is initiated to Port Scheduling poller module 6.
Read port access request module 4 obtains for the data that can be written in read port synchronization module 5 in memory
Several detailed processes are：The number x for needing the data transmitted is obtained, when the remaining space in read port synchronization module 5 can be deposited
When putting x data, then the data amount check for the read request that read port access request module 4 exports is x；When read port synchronization module 5
In remaining space when can store y data, and y<X, the then data for the read request that read port access request module 4 exports
Number is y.
Port Scheduling poller module 6 is kernel control module, by state machine come each asynchronous FIFO control module of poll
Access request is read or write to memory, when some asynchronous FIFO control module has read and write access request, is then jumped to corresponding
Processing status request is responded, and it is same from write port by the data of request to control memory interface time-sequence control module 7
The write-in of module 1 address that the fifo controller write pointer is directed toward into memory is walked, or the fifo controller read pointer is directed toward
Address date read and cache into read port synchronization module 5.
Read-write pointer management module 2 is responsible for realizing that the read-write pointer of the fifo controller calculates and to calculate this in real time asynchronous
Data amount check in FIFO control module is carried out when having data from when reading in memory or having data to be written in memory
The read/write address of DDRx updates and data amount check updates.
Memory interface time-sequence control module 7 responds read-write operation request, completes the read and write access of memory.Number is write in response
When according to operation requests, the data in write port synchronization module 1 are read and are written in memory；When response readings are according to operation,
Data in memory are read and are written in read port synchronization module 5.
Preferably, memory of the present invention is DDR2 memory or DDR3 memory etc., corresponding memory interface
Time-sequence control module 7 is DDR2 or DDR3 interface sequence control module, realizes and realizes corresponding behaviour to DDR2 or DDR3 memory
Make.
As shown in Figure 1, fifo controller of the invention has the two symmetrical asynchronous FIFO control modules in left and right,
Working method is：The write port of the same asynchronous FIFO control module (the asynchronous FIFO control module on left side or right side) is synchronous
The data that module 1 is written into are synchronized under memory interface time-sequence control module 7, and the data of write port synchronization module 1
When reaching the condition of write-in memory, the data in write port synchronization module 1 are read and are written to by Port Scheduling poller module 6
In memory.The read-write pointer management module 2 of the same asynchronous FIFO control module is for realizing the asynchronous FIFO control module
Read-write pointer calculate and calculate the number of data in the asynchronous FIFO control module, when thering are data to read from memory or write
When entering into memory, the update of read/write address and the update of its data amount check having in memory are carried out.
The write port access request module 3 of the same asynchronous FIFO control module calculates in its write port synchronization module 1
Need to be written to the number of the data in memory, specifically, work as the write port synchronization module 1 of the asynchronous FIFO control module
When write port continuously has data write-in, write port access request module 3 can wait until always the data in the write port synchronization module 1
When number reaches setting value (such as being set as 64) a data, the request of write-in memory is initiated, this processing mode can be use up
It is possible that the data that channel is written is made to realize burst transfer, write access bus utilization and transmission bandwidth are improved, when the write port
When the data deficiencies setting value (64) for needing to be written is a, write port access request module 3 sets a timeout value (such as 512ns),
When the time that data store in write port synchronization module 1 is more than 512ns, write port access request module 3 can also be initiated count
According to the write request of write-in memory, to ensure that the write port of the same asynchronous FIFO control module to the data of read port
Delay is in a determining range.Wherein the calculation of the data amount check of write request is：It is needed in the manner described above
The data amount check n to be transmitted, when the remaining space of memory can store n data, then write port access request module 3
The data amount check of write request is n；When the remaining space of memory can store m data, and m<When n, then write port access is asked
The data amount check of the write request of modulus block 3 is m.
The read port access request module 4 of the same asynchronous FIFO control module, which is calculated from memory, is transferred to read port
Data amount check in synchronization module 5, when the valid data in memory continue to increase, the meeting of read port access request module 4 one
Directly until the data in the DDRx buffer area of the asynchronous FIFO control module reach setting value (such as 64) a data, then
The request of data in read in memory is initiated, this processing mode can make the data of read channel realize that burst passes as far as possible
It is defeated, improve read channel bus utilization and transmission bandwidth；When the data in the DDRx buffer area of the asynchronous FIFO control module not
At 64, foot, read port access request module 4 has the timeout value that can be set (such as 512ns), and data are in DDRx buffer area
When the time of middle storage is more than 512ns, read port access request module 4 can be initiated to read the operation application of data in memory, from
And guarantees the data from the write port of the asynchronous FIFO control module to read port and postpone in a determining range.Read request
The calculation method of data amount check is：The available one data amount check x for needing to transmit in such a way that above-mentioned read request generates,
When 5 remaining space of read port synchronization module can store x data, then read port access request module 4 export read request
Data amount check be x；When 5 remaining space of read port synchronization module can store y data, and y<When x, read port access request
The data amount check for the read request that module 4 exports is y.
The asynchronous FIFO control module read pointer is directed toward by the read port synchronization module 5 of the same asynchronous FIFO control module
Data read and cached from memory, when user needs from the asynchronous FIFO control module to read data, then use
Family is read data by operation read port.
Port Scheduling poller module 6 is the kernel control module of the fifo controller, different come poll two by state machine
The read and write access to memory for walking four ports (2 read ports and 2 write ports) of FIFO control module is requested, when some
When reading or writing port has corresponding access request and the data amount check of transmission is requested to be greater than 0, then corresponding processing shape is jumped to
State responds request.The method that the module is used when being polled scheduling is average port basis poll, each port
Priority be it is identical, bandwidth allow in the range of, can guarantee that the data of each port can obtain at effective transmission
Reason.During carrying out data transmission, mode while being written and read to FIFO using assembly line generates memory and answers
With interface sequence, so that the maximization of data transmission efficiency.
Memory interface time-sequence control module 7, the module Port Scheduling poller module 6 respond read-write operation request when,
Realize the timing sequence conversion of the transmission of data.When responding data writing operation request, the data in write port synchronization module 1 are read simultaneously
It is written in memory；When response readings are according to operation, the data in memory are read and are written to read port synchronization module 5
In.
The high-capacity FIFO controller proposed according to the present invention, the logical design with Verilog HDL language to controller
It is described, and is applied in certain two-way video capture card product design, and the function and performance of controller are tested.It surveys
Test result shows that the present invention has good exploitativeness, and performance meets expection.
Claims (7)
1. a kind of high-capacity FIFO controller based on DDRx memory, which is characterized in that by memory package one or more
Asynchronous FIFO control module, and asynchronous FIFO control module passes through Port Scheduling poller module (6) and memory interface timing control
Molding block (7) is connect with memory；
The asynchronous FIFO control module includes：Write port synchronization module (1), read port synchronization module (5), write port access are asked
Modulus block (3), read port access request module (4) and read-write pointer management module (2)；
The data that the fifo controller is written are synchronized to by Port Scheduling poller module (6) and are deposited by write port synchronization module (1)
On memory interface time-sequence control module (7)；
The data of the fifo controller are passed through end from memory interface time-sequence control module (7) by read port synchronization module (5)
Mouth scheduling poller module (6) reads and is cached；
Write port access request module (3) obtains that write port synchronization module (1) needs to be written to the data in memory
Number, and write access request is initiated to Port Scheduling poller module (6)；
Read port access request module (4), the number of the data in memory can be read by obtaining read port synchronization module (5),
And read access request is initiated to Port Scheduling poller module (6)；
Port Scheduling poller module (6), each asynchronous FIFO control module of poll read or write access request to memory；
Memory interface time-sequence control module (7), the read or write request of response asynchronous FIFO control module, and to DDRx
Memory block is accessed accordingly.
2. the high-capacity FIFO controller according to claim 1 based on DDRx memory, which is characterized in that described asynchronous
FIFO control module further includes read-write pointer management module (2), and the reading of the fifo controller is completed in read-write pointer management module (2)
Or the pointer operation write, and calculate the number of the data in the fifo controller；After the read or write for carrying out data, read-write
Pointer management module (2) carry out the update of the data amount check in the fifo controller and to the read/write address of memory more
Newly.
3. the high-capacity FIFO controller according to claim 2 based on DDRx memory, which is characterized in that the reading end
The data read in mouth synchronization module (5) are that will read and write the data of pointer management module (2) read pointer direction.
4. the high-capacity FIFO controller according to claim 1 based on DDRx memory, which is characterized in that described to write end
The process that write port synchronization module (1) needs to be written to the number of the data in memory is obtained in mouth access request module (3)
It is：The number n for needing the data transmitted is obtained, when the remaining space of memory can store n data, then write port is requested
The data amount check of the write request of module (3) output is n；When the remaining space of memory can store m data, and m<N then writes
The data amount check of the write request of port request module (3) output is m.
5. the high-capacity FIFO controller according to claim 1 based on DDRx memory, which is characterized in that the reading end
Mouth access request module (4) obtains the specific of the number for the data that can be written in read port synchronization module (5) in memory
Process is：The number x for needing the data transmitted is obtained, when the remaining space in read port synchronization module (5) can store x number
According to when, then read port access request module (4) output read request data amount check be x；When in read port synchronization module (5)
When remaining space can store y data, and y<X, the then data amount check for the read request that read port access request module (4) exports
For y.
6. the high-capacity FIFO controller according to claim 1 based on DDRx memory, which is characterized in that the storage
Device interface sequence control module (7) reads the data in memory in corresponding read operation, and read port synchronization module is written
(5) in.
7. the high-capacity FIFO controller according to claim 1 based on DDRx memory, which is characterized in that the storage
Device interface sequence control module (7) reads the data in write port synchronization module (1) in corresponding write operation, and is written to
In memory.
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| CN111581132A (en) * | 2020-04-27 | 2020-08-25 | 武汉中科牛津波谱技术有限公司 | Extensible multiport DDR3 controller based on FPGA |
| CN112416823A (en) * | 2020-11-15 | 2021-02-26 | 珠海市一微半导体有限公司 | Sensor data read-write control method, system and chip in burst mode |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111581132A (en) * | 2020-04-27 | 2020-08-25 | 武汉中科牛津波谱技术有限公司 | Extensible multiport DDR3 controller based on FPGA |
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| CN112416823A (en) * | 2020-11-15 | 2021-02-26 | 珠海市一微半导体有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN112416823B (en) * | 2020-11-15 | 2024-05-03 | 珠海一微半导体股份有限公司 | Sensor data read-write control method, system and chip in burst mode |
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