CN117665534A - IEEE 1149.10-JTAG signal converter - Google Patents

Abstract

The invention provides an IEEE1149.10 to JTAG signal converter, the method comprising: data packets based on the IEEE1149.10 standard format are received and parsed into JTAG signals to allow communication and control by JTAG interface-compliant devices. The JTAG drive signals include: TCK test clock signal, TMS test mode select signal, TDI test data input signal, TDO test data output signal, TRST test reset signal. According to the invention, the IR instruction information and the DR data information are packaged according to the data packaging standard in the IEEE1149.10 standard, and JTAG driving signals with correct time sequence can be obtained by the method, so that the requirements that the data of the high-speed test port needs to be rapidly and accurately analyzed and then tested are met.

Description

IEEE 1149.10-JTAG signal converter

Technical Field

The invention relates to the field of chip testing, in particular to an IEEE 1149.10-JTAG signal converter.

Background

JTAG (Joint Test Action Group, joint test working group) interface is an interface standard of IEEE, and plays an important role in testing, simulating, debugging and the like of integrated circuits. Most existing advanced devices support JTAG protocols, such as DSP, FPGA (FPGA Field Programmable Gate Array, field programmable gate array) and the like. By embedding JTAG interface circuits in the chip, boundary scan testing of the chip can be realized. The JTAG interface circuit includes a TAP controller, an instruction register, and a data register.

The TAP (Test Access Port) controller is the core of the boundary scan Test. According to the IEEE1149.1 standard, the TAP controller has 5 driving signals, namely a test clock input signal TCK, a test mode select signal TMS, a test data input signal TDI, a test data output port TDO, and a test reset input signal TRST. Among them, the first four signals are mandatory in the IEEE1149.1 standard, and TRST is optional in the IEEE1149.1 standard.

Of the 5 JTAG drive signals, the TCK provides an independent, basic clock signal for the operation of the TAP controller, through which all operations of the TAP controller are driven. The TMS signal is used for controlling the conversion of the TAP state machine, and through the TMS signal, the TAP controller can be controlled to be converted mutually between different states, and the TMS signal is effective at the rising edge of TCK. TDI is an interface for data input, and all data to be input to a particular register, i.e., an instruction register or a data register, is input bit-by-bit serially (driven by TCK) through the TDI interface. TD0 is an interface for data output, and all data to be output from a specific register is serially output bit by bit (driven by TCK) through the TDO interface. TRST may be used to reset (initialize) the TAP controller, and TAP may be reset (initialize) via TMS.

The internal logic of the JTAG interface circuit is implemented by a TAP state machine, see FIG. 1 for a state transition diagram of the TAP state machine specified by the IEEE1149.1 standard. In the transition diagram of the state machine of the TAP controller shown in fig. 1, only 6 states of the state machine of the TAP controller are steady states, including Test-Logic Reset (Test-Logic Reset), test/wait (Run-Test/Idle), data register Shift (Shift-DR), data register Shift Pause (Pause-DR), instruction register Shift (Shift-IR), instruction register Shift Pause (Pause-IR), and none of the other states are steady states but only transient states. As shown in fig. 1, the TAP state machine comprises two branches, a command register (IR) access branch and a Data Register (DR) access branch, respectively. And the state transitions of the TAP state machine are controlled by a test mode select signal (TMS) in the JTAG interface circuit.

Test time has been an important indicator of system on chip (SoC). The original IEEE1149.1 test access port is good for simple inter-board interconnect testing, but with the increase in on-chip operation through the IEEE1149.1 Test Access Port (TAP), using the IEEE1149.1 TAP becomes inefficient for on-board testing and on-board Field Programmable Gate Array (FPGA) configurations. The industry needs a high speed access port (HSTAP) and block encoder/decoder and distribution architecture (PEDDA) to standardize the test data transmission mechanisms of IC Automated Test Equipment (ATE).

IEEE1149.10 provides an alternative, requiring only differential receivers and transmitters: four pins, a system clock and power supply, can deliver the same test data bandwidth. By making the scan channels "virtual," the scan rate, the number of concurrently active scan channels, and the required test bandwidth can be weighed during test design.

In the above-mentioned test data transmission mechanism, when testing a chip with a JTAG interface, test data is packed based on IEEE1149.10 protocol, firstly, it is required to verify whether a JTAG functional module in the chip is normal, and then TCK, TMS, TDI signals are required to be generated and sent to the JTAG interface, so that a process of converting information into JTAG driving signals after decoding a data packet is involved.

Disclosure of Invention

The invention provides an IEEE 1149.10-JTAG signal converter, which is used for solving the problem that when test data accords with IEEE1149.10 standard and is applied to JTAG test, JTAG driving signals need to be generated quickly and accurately.

To solve the above technical problem, the present invention provides an IEEE1149.10 to JTAG signal converter, the method comprising:

and receiving test data coded by the IEEE1149.10 standard, analyzing to obtain corresponding instruction register IR instruction information and data register DR data information, and receiving clock information.

And generating corresponding JTAG driving signals according to the clock information, the IR instruction information and the DR data information.

Preferably, before analyzing the received packaged test data to obtain clock information, IR instruction information and DR data information, determining the required clock information, IR instruction information and DR data information according to the test content of the target chip, and encoding the IR instruction information and DR data information according to IEEE1149.10 standard to obtain a SCAN packet, and generating corresponding clock information.

Preferably, the JTAG drive signals include a test clock input signal TCK signal.

And generating a TCK signal according to the clock information, wherein the basic clock is divided according to the clock information, so that the TCK signal is obtained, and the TCK signal is provided for a JTAG interface of the target chip.

Preferably, decoding the SCAN packet results in IR instruction information.

Analyzing the IR instruction information to obtain an IR instruction length and an IR instruction content, determining the duration of the test port TAP state machine in the Shift-IR state according to the IR instruction length, and providing the IR instruction content as the TDI signal to a JTAG interface of a target chip when the TAP state machine is in the Shift-IR state.

Preferably, decoding the SCAN packet to obtain DR data information;

and analyzing the DR data information to obtain DR data length and DR data content, determining the duration of the test port TAP state machine in the Shift-DR state according to the DR data length, and providing the DR data content as the TDI signal to a JTAG interface of a target chip when the TAP state machine is in the Shift-DR state.

Preferably, the JTAG drive signals further include a test mode select signal TMS signal.

Generating a corresponding JTAG driving signal according to the clock information, the IR instruction information and the DR data information comprises:

outputting TMS signals for transferring the TAP controller into a Shift-IR state according to the IR instruction information required to be output, and outputting TMS signals for enabling the TAP controller to be kept in the Shift-IR state in a clock period indicated by the IR instruction length according to the IR instruction length; and outputting a TMS signal for enabling the TAP controller to enter an Update-IR state; finally, a TMS signal is output that causes the TAP controller to transition into the "Run-Test/Idle" state.

Outputting TMS signals for transferring the TAP controller into a Shift-DR state according to DR data information to be output, and outputting TMS signals for enabling the TAP controller to be kept in the Shift-DR state in a clock period indicated by the DR data length according to the DR data length; and outputting a TMS signal for enabling the TAP controller to enter an Update-DR state; finally, a TMS signal is output that causes the TAP controller to transition into the "Run-Test/Idle" state.

The beneficial effects of the invention include:

by the JTAG signal converter provided by the invention, the test data is only required to be encoded according to the JTAG test content of the target chip and the requirements of the IEEE1149.10 standard, and the encoded data packet is sent to the JTAG signal converter, and the JTAG signal converter decodes the data packet according to the IEEE1149.10 standard and analyzes the decoded data packet to obtain the IR instruction information and the DR data information. The clock information is provided by the test controller according to the test content requirement. And generating corresponding JTAG signals according to the clock information, the IR instruction information and the DR data information.

Drawings

FIG. 1 is a state transition diagram of a TAP controller as specified in the IEEE1149.1 standard;

FIG. 2 is a flowchart illustrating an implementation method of an IEEE 1149.10-JTAG signal converter according to an embodiment of the present invention;

FIG. 3 is an exemplary TCK, TDI, TMS, timing diagram provided by an embodiment of the present invention;

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention.

Referring to fig. 2, a flowchart of a JTAG signal converter according to an embodiment of the present invention is provided, and as shown in fig. 2, the JTAG signal converter according to the embodiment of the present invention includes:

step 1, receiving a SCAN packet and decoding to obtain IR instruction information and DR data information;

step 2, analyzing the IR instruction information and the DR data information to obtain an IR instruction length, an IR instruction content, a DR data length and a DR data content;

and step 3, generating JTAG signals according to the IR instruction length, the IR instruction content, the DR data length, the DR data content and clock information provided by the system.

In the embodiment of the present invention, the SCAN packet format is a format provided in the IEEE1149.10 standard, and the format is: start character (SOP) +command Character (CMD) +identification (ID) +instruction shift capture update (ICSU) +data Payload frame (#payload-Frames) +scan clock number (Cycle-Count) +data (payoad) +check character (CRC 32) +end character (EOP).

Table 1 is an exemplary SCAN packet configuration provided in this embodiment, and the following explains each part of the data.

The start character SOP indicates the start of a data packet; wherein, according to the content of the command character CMD being 0x06, the data packet is a SCAN scanning data packet, which contains IR instruction information and DR data information; the content in the ID indicates the sequence of the data packet, 0x01 indicates that the SCAN packet is received for the first time, and the response packet also has the same ID value; the instruction capture shift update ICSU, i.e. Instruction, capture, shift, update initial, is composed of a 4-bit binary system, a corresponding bit of 1 indicates that the corresponding operation is valid, an ICSU high bit of 1 indicates that the packet is an instruction packet, the content in payoad is instruction information, otherwise, the packet is a data packet, and the content in payoad is test data, such as: 0b0110 is denoted as a data packet, and performs a capture shift operation; the data Payload frame #payload-Frames indicates how many Frames the following payoad data is, with 32 bits as one frame, # Payload-Frames as 0x01000000 indicates that there is one frame of payoad data; the scanning clock Cycle-Count represents the clock number required by data; payoad is used for carrying interleaved data to be transmitted; the check character CRC32 represents 16-ary data calculated by the CRC32 check principle for non-control characters other than the start character before; the end character EOP indicates the termination of a packet.

TABLE 1

SCAN packet format	Content
		SOP	8’hfb
CMD	8’h06
		ID	4’h01
ICSU	4’b0110
		#Payload-Frames	32’h01000000
Cycle-Count	32’hB0000000
		PAYLOAD	32’h12600000
CRC32	32’hD04D7009
		EOP	32’hfdfdfdfd

According to the configuration description, the ICSU information is analyzed to judge whether the SCAN packet is an instruction packet or a data packet, the size of the PAYLOAD is confirmed by analyzing # Payload-Frames, the clock number required by the information in the PAYLOAD for executing shifting operation is confirmed by analyzing Cycle-Count, one clock is shifted by one bit, and the PAYLOAD is analyzed to obtain IR instruction information or DR data information.

The JTAG driving signals mentioned in the embodiment of the invention comprise: the TCK signal, the TMS signal and the TDI signal are respectively and correspondingly provided for a TCK interface, a TMS interface and a TDI interface of a target chip JTAG module.

The generation of the three JTAG driving signals is described below.

In the embodiment of the invention, the TCK signal is divided by a clock circuit module on a basic clock according to the IR instruction information and the DR data information and is provided for a TCK interface in the JTAG module.

In the embodiment of the invention, the TMS signal is determined and provided by analyzing ICSU information and Cycle-Count information. Specifically, analyzing the ICSU information to determine whether the data packet carries PAYLOAD information as IR instruction information or DR data information, so as to configure TMS to enter a corresponding state; analyzing the Cycle-Count information determines the duration of the data in the shifted state.

In the embodiment of the invention, the TDI signal is determined and provided by analyzing PAYLOAD information, specifically, PAYLOAD is analyzed to obtain IR instruction information and DR data information, and the IR instruction information and the DR data information are provided to the TDI interface through a TAP state machine in a serial shift input mode.

The following is an exemplary illustration in connection with the examples provided in table 1.

Assuming a master system clock of 300MHz and a test circuit requires a 50MHz clock, the clock circuit module divides the system clock by 6 and provides the divided clock to the TCK interface of the JTAG module. The TMS signal outputs first a number of clock 1's under the TCK clock drive, ensuring that the TAP state machine enters a "Test-Logic-Reset" Test Logic Reset state to await receipt of data. After receiving the ICSU, confirming the SCAN packet as a data packet, analyzing information in the PAYLOAD, and providing the analyzed data as a TDI signal to a TDI interface of a JTAG module; the output TMS signal is equal to 0100, so that the TAP state machine enters the Shift-DR state, and the analysis Cycle-Count confirms that the data length is 11 (the data is converted into decimal through hexadecimal B), the Shift is needed for 11 times, and the Shift operation is needed to be performed once before, so that the Shift-DR state is needed to be kept for 10 times, and the output TMS signal is equal to 10 0. After the DR data is sent, TMS signal output 11 enters an "Update-DR" state to Update the data in the tested structure, and TMS signal output 0 to enable the TAP state machine to enter a "Run-Test/Idle" state to wait for the next data processing.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention, and are intended to be included within the scope of the appended claims and description.

Claims (8)

1. An IEEE1149.10 to JTAG signal converter, the method comprising the steps of:

receiving a data packet coded based on an IEEE1149.10 standard, and analyzing IR instruction information, capturing, shifting, updating, DR data information and clock information;

and generating corresponding JTAG driving signals according to the IR instruction information, the DR data information and the clock information.

2. The method of claim 1, further comprising, prior to said receiving the data packet encoded based on the IEEE1149.10 standard, parsing the IR instruction information, DR data information, clock information: and determining the SCAN package according to the content of the tested target chip.

3. The method of claim 1, wherein the JTAG drive signal comprises a test clock input signal TCK;

the generating the corresponding JTAG driving signal according to the clock information, the IR instruction information and the DR data information includes: generating a TCK signal according to the clock information; and dividing the frequency of the basic clock according to the clock frequency division value carried in the clock information, thereby obtaining the TCK signal and providing the TCK signal to a JTAG interface of the target chip.

4. The method of claim 2, wherein said SCAN contains IR instruction information or DR data information, and capture, shift, update information.

5. The method of claim 4, wherein the IR instruction information is parsed to obtain an IR instruction length and an IR instruction content, and the DR data information is parsed to obtain a DR data length and a DR data content;

and temporarily storing the analyzed IR instruction length, IR instruction content, DR data length and DR data content.

6. The method of claim 5, wherein the JTAG drive signals further comprise a test data input signal TDI signal; generating corresponding JTAG drive signals according to the clock information, the IR instruction information and the DR data information includes:

according to the length of the IR instruction, determining the duration of the test port TAP in the Shift-IR state, and providing the IR instruction content as a TDI signal to a JTAG interface of a target chip when a TAP state machine is in the Shift-IR state;

and determining the duration of the TAP state machine in the Shift-DR state according to the DR data length, and providing the DR data content as a TDI signal to a JTAG interface of a target chip when the TAP state machine is in the Shift-DR state.

7. The method of claim 5, wherein the JTAG signals further comprise a test mode select signal TMS signal;

and determining a TAP state machine transfer time sequence according to the clock information, the IR instruction information and the DR data information, determining a control signal required for realizing the transfer time sequence, and providing the control signal as a TMS signal to a JTAG interface of a target chip.

8. The method of claim 7, wherein determining TAP state machine transition timing based on the clock information, IR instruction information, and DR data information, and determining control signals required to implement the transition timing, providing the control signals as TMS signals to a JTAG interface of a target chip, comprises:

outputting TMS signals which enable the TAP controller to be transferred into a Shift-IR state according to IR instruction information, outputting TMS signals which enable the TAP controller to be kept in the Shift-IR state in a clock period required by the IR instruction length according to the IR instruction length, outputting TMS signals which enable the TAP controller to be transferred into an Update-IR state, and finally outputting TMS signals which enable the TAP controller to be transferred into a Run-Test/Idle state.

Outputting TMS signals which enable the TAP controller to be transferred into a Shift-DR state according to DR data information, outputting TMS signals which enable the TAP controller to be kept in the Shift-DR state in a clock period required by the DR data length according to the DR data length, outputting TMS signals which enable the TAP controller to be transferred into an Update-DR state, and finally outputting TMS signals which enable the TAP controller to be transferred into a Run-Test/Idle state.