CN110456251A - The array test method of image sensor chip - Google Patents
The array test method of image sensor chip Download PDFInfo
- Publication number
- CN110456251A CN110456251A CN201810426558.4A CN201810426558A CN110456251A CN 110456251 A CN110456251 A CN 110456251A CN 201810426558 A CN201810426558 A CN 201810426558A CN 110456251 A CN110456251 A CN 110456251A
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- Prior art keywords
- chip
- test
- image sensor
- array
- sensor chip
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2829—Testing of circuits in sensor or actuator systems
Abstract
The present invention relates to a kind of array test methods of image sensor chip, comprising: provides several image sensor chips of test circuit board, array arrangement, the test circuit board corresponds to image sensor chip and is respectively arranged with test chip；The image sensor chip of array arrangement is connected to test chip correspondingly, the test chip tests the image sensor chip of connection；Distribute the address of each test chip；The test data of correspondence image sensor chip or image data are successively transmitted to adjacent test chip by each test chip, and finally by total data information transfer to main control chip.In the present invention, multiple chips can be tested simultaneously, improve chip testing efficiency, shorten the period.
Description
Technical field
The present invention relates to image sensor chip the field of test technology more particularly to a kind of arrays of image sensor chip
Formula test method.
Background technique
Chip checking and test are very important link for the volume production of chip, will be into before shipment to every chips
Row functional test, to guarantee the yield of shipment chip, and this test process also directly affects the cost of chip.
Traditional chip checking test method includes: the test to the digital logic portion of intermediate wafer, abbreviation probe
(CP, Chip Probing) test；To the number and simulation test of terminal, abbreviation terminal test (FT, Final Test) or
Console tests (BBT, BenchBoard Test) software test.Usual chip carries out in test process, once to single or several
A chip is tested, thus the period tested is long, low efficiency.
Summary of the invention
The purpose of the present invention is to provide a kind of array test methods of image sensor chip, solve in the prior art
The low problem of chip testing efficiency.
In order to solve the above technical problem, the present invention provides a kind of array test method of image sensor chip, packets
It includes:
Several image sensor chips of test circuit board, array arrangement are provided, the test circuit board corresponds to image sensing
Device chip is respectively arranged with test chip, and the image sensor chip of array arrangement is connected to test chip correspondingly;
Distribute the address of each test chip；
The test chip tests the image sensor chip of connection；
The test data of correspondence image sensor chip or image data are successively transmitted to adjacent test by each test chip
Chip, and finally by total data information transfer to main control chip.
Optionally, the array is N × M arrangement, wherein N and M is natural number, and N × M is more than or equal to 32.
Optionally, each test chip on the test circuit board has L electricity connection end, each electricity connection end
It is respectively configured as logically high or logic low, corresponding configuration 2LThe test chip of a different address.
Optionally, the main control chip sends L initialization directives, the test chip foundation to some test chip
Initialization directive configures its address, and forms a new command and be sent to next test chip, next test chip foundation
New command configures its address, until the address configuration of all test chips is completed.
Optionally, have 2 on the main control chipLA electricity connection end, is configured to 2LA different address, and be correspondingly connected with
Each test chip.
Optionally, the corresponding test chip for being sent to specified address of control instruction is controlled array by the main control chip
The test of the image sensor chip of arrangement.
Optionally, control instruction is directly sent to test chip by being electrically connected line by the main control chip.
Optionally, the control instruction of main control chip is successively transmitted to adjacent test chip by each test chip.
Optionally, further includes: the main control chip tests each test chip, and records fault test chip pair
The address answered.
It optionally, is bidirectional data transfers between each test chip.
Compared with the existing technology, the array test method of image sensor chip of the invention has below beneficial to effect
Fruit:
In the present invention, the image sensor chip of array arrangement is connected to test chip correspondingly, test chip is to even
The image sensor chip connect is tested, and each test chip is by the test data or picture number of correspondence image sensor chip
According to being successively transmitted to adjacent test chip, and finally by total data information transfer to main control chip, the present invention can survey simultaneously
Multiple chips are tried, chip testing efficiency is improved, shorten the period.
Detailed description of the invention
Fig. 1 is the flow diagram of the array test method of image sensor chip in one embodiment of the invention；
Fig. 2 is the schematic diagram that circuit board is tested in the embodiment of the present invention one
Fig. 3 is the schematic diagram that circuit board is tested in the embodiment of the present invention two；
Fig. 4 is the schematic diagram that circuit board is tested in the embodiment of the present invention three.
Specific embodiment
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention.But the present invention can be with
Much it is different from other way described herein to implement, those skilled in the art can be without prejudice to intension of the present invention the case where
Under do similar popularization, therefore the present invention is not limited to the specific embodiments disclosed below.
Secondly, the present invention is described in detail using schematic diagram, when describing the embodiments of the present invention, for purposes of illustration only, institute
Stating schematic diagram is example, should not limit the scope of protection of the invention herein.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with 1 ~ Fig. 4 of attached drawing to this
The array test method of the image sensor chip of invention is described in detail.
Embodiment one
Refering to what is shown in Fig. 1, the array test method of image sensor chip of the invention the following steps are included:
Step S1 is executed, several image sensor chips of test circuit board, array arrangement are provided, to testing image sensor
Chip, refering to what is shown in Fig. 2, the test circuit board 100 has main control chip 101 and several test chips 102, the test
Circuit board 100 corresponds to image sensor chip and is respectively arranged with test chip 102, i.e., several test chips 102 are equally in
The image sensor chip of array arrangement is connected to test chip 102 by array arrangement correspondingly.Wherein, the array
For N × M arrangement, N and M are natural number, and in the present embodiment, it is 8 that N × M, which is more than or equal in 32, such as Fig. 2 with N, 8 × 4 that M is 4
It is illustrated for array.
Step S2 is executed, the address of each test chip 102 is distributed.In the present embodiment, chip 102 and main control chip are tested
It is connected by the way of I2C between 101, tests between chip 102 and connected by MIPI agreement, main control chip 101 and test core
The transmitting of information is realized between piece 102 by serial data line SDA and serial time clock line SCL two lines.Specifically, distribution is each
The address of test chip 102 can carry out in the following way: each test chip 102 tool on the test circuit board 100
There is L electricity connection end, each electricity connection end is respectively configured as logically high " 1 " or logic low " 0 ", corresponding configuration 2LA difference
The test chip of address.Wherein L is 5, be respectively configured as 00000,00001,00010,00011 ..., 11111, so as to
Configure the different test chip in 32 addresses.In the address distribution, after test circuit board is installed, each test chip
102 corresponding addresses are fixed.
In addition, the address of each test chip 102 of distribution can also carry out in the following way: the main control chip 101
The initialization directive that chip sends L, such as 5 initialization directive A, the test core are tested to some by MIPI agreement
Piece configures its address according to initialization directive A, also, the test chip increases n(in original initialization directive), such as n is 1, forms a new command and is sent to next test chip, next test chip foundation
New command configures its address, successively hands on according to this method, and each test chip is sequentially allocated address, until all tests
The address configuration of chip is completed, and the test chip of 32 different addresses is formed.
It further include the power up test process to each test chip, the main control chip after the completion of address above mentioned allocation step
101 pairs of each test chips 102 are tested, and record the corresponding address of fault test chip.What the power up test process referred to
Be: after the completion of testing 102 configuration address of chip, main control chip 102 from receive A instruct test chip (or from first survey
Try chip) start, it successively sends and instructs to each test chip 101, it is desirable that it returns to nominative testing data, tests chip 102
Result is successively returned to by MIPI agreement by main control chip 102 after receiving instruction, main control chip 101 is returned the result receiving
Next test chip 102 is tested again afterwards, otherwise in the case where time-out does not receive returned data, main control chip 101
Starting alarm, and indicate the address of record failure chip.
Step S3 is executed, the image sensor chip of 102 pairs of the chip connections of test is tested.The main control chip
101, by the corresponding test chip 102 for being sent to specified address of control instruction, control the image sensor chip of array arrangement
Test.The main control chip 101 directly will control by two electric connection lines of serial data line SDA and serial time clock line SCL
Instruction is sent to test chip 102, and test chip tests image sensor chip according to control instruction, for example, control
Image sensor chip is taken pictures.
Step S4 is executed, each test chip 102 passes through MIPI agreement for the test data of correspondence image sensor chip
Or image data is successively transmitted to adjacent test chip, and finally by total data information transfer to main control chip, and each
Testing is bidirectional data transfers between chip.For example, test data is sent to the 31st test chip by the 32nd test chip,
The test data of the test data that 32nd is tested chip and the 31st test chip is sent to the 30th by the 31st test chip
The test data that 32nd, 31,30 is tested chip is transferred to the 29th test core by a test chip, the 30th test chip
Piece, and successively hand on, so that the data of all test chips are finally sent to main control chip 101.It can in MIPI agreement
The data type (dataType) of test chip transmission is configured, to support test data, test result, control instruction
Transmission, such as data type can be set to, the control instruction that 0x30 is indicated.The test data or test result that 0x31 is indicated.
Embodiment two
Refering to what is shown in Fig. 3, the mode that chip address distribution is tested unlike embodiment one, in the present embodiment is different, control
The mode of system instruction transmitting is different.It is specific:
During executing step S2, main control chip 101 is connect using SPI mode with test chip 102, allocation for test chip
102 addresses carry out in the following way: having 2 on the main control chip 101LA electricity connection end, is configured to 2LIt is a differently
Location, each electricity connection end are correspondingly connected with each test chip, for example, L is 5, configure 32 different addresses.Therefore, this implementation
The address allocation procedure of example is address fixed in main control chip.
Likewise, further include the power up test process to each test chip after the completion of address above mentioned allocation step, it is described
Main control chip 101 tests each test chip 102, and records the corresponding address of fault test chip.The power up test
Process is i.e. after the completion of testing 102 configuration address of chip, and main control chip 102 is since first test chip, successively to each
It tests chip 101 and sends instruction, it is desirable that it returns to nominative testing data, and test chip 102 is assisted after receiving instruction by MIPI
Result is successively returned to main control chip 102 by view, main control chip 101 receive return the result after again to next test chip
102 are tested, otherwise in the case where time-out does not receive returned data, the starting alarm of main control chip 101, and indicate record event
Hinder the address of chip.
During executing step S3, the image sensor chip of 102 pairs of the chip connections of test is tested.It is described
The corresponding test chip 102 for being sent to specified address of control instruction is controlled the image sensing of array arrangement by main control chip 101
The test of device chip.The main control chip 101 is directly sent out control instruction by tetra- electric connection lines of SCLK, SDO, SDI, CS
It send to test chip 102, test chip tests image sensor chip according to control instruction, for example, control image passes
Sensor chip is taken pictures.
Embodiment three
Refering to what is shown in Fig. 4, control instruction transfer mode is different in the present embodiment unlike embodiment one, it is specific:
In the present embodiment, main control chip is connect with test chip using MIPI agreement.During executing step S3, the test
The image sensor chip of 102 pairs of chip connections is tested.The main control chip 101 is sent to finger for control instruction is corresponding
The test chip 102 for determining address, controls the test of the image sensor chip of array arrangement.Each test chip is by main control chip
Control instruction be successively transmitted to adjacent test chip, specifically, control instruction is sent to first by the main control chip 101
Control instruction is successively sent to next test chip by a test chip, the test chip, until corresponding be sent to specified ground
The test chip of location, the test result of the test chip pass through MIPI agreement in the same way and test result are back to master
Chip 101 is controlled, is completed until all image sensor chips are tested.
In conclusion the array test method of image sensor chip provided by the invention, by the image of array arrangement
Sensor chip is connected to test chip correspondingly, and test chip tests the image sensor chip of connection, often
The test data of correspondence image sensor chip or image data are successively transmitted to adjacent test chip by a test chip, and
Finally by total data information transfer to main control chip, multiple chips can be tested simultaneously, improve chip testing efficiency.
Although the invention has been described by way of example and in terms of the preferred embodiments, but it is not for limiting the present invention, any this field
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this hair
Bright technical solution makes possible variation and modification, therefore, anything that does not depart from the technical scheme of the invention, and according to the present invention
Technical spirit any simple modifications, equivalents, and modifications to the above embodiments, belong to technical solution of the present invention
Protection scope.
Claims (10)
1. a kind of array test method of image sensor chip characterized by comprising
Several image sensor chips of test circuit board, array arrangement are provided, the test circuit board corresponds to image sensing
Device chip is respectively arranged with test chip, and the image sensor chip of array arrangement is connected to test chip correspondingly；
Distribute the address of each test chip；
The test chip tests the image sensor chip of connection；
The test data of correspondence image sensor chip or image data are successively transmitted to adjacent test by each test chip
Chip, and finally by total data information transfer to main control chip.
2. the array test method of image sensor chip according to claim 1, which is characterized in that the array is
N × M arrangement, wherein N and M is natural number, and N × M is more than or equal to 32.
3. the array test method of image sensor chip according to claim 1, which is characterized in that the test electricity
Each test chip on the plate of road has L electricity connection end, and each electricity connection end is respectively configured as logically high or logic low,
Corresponding configuration 2LThe test chip of a different address.
4. the array test method of image sensor chip according to claim 1, which is characterized in that the master control core
Piece sends L initialization directives to some test chip, which configures its address, and shape according to initialization directive
It is sent to next test chip at a new command, which configures its address according to new command, until all
The address configuration for testing chip is completed.
5. the array test method of image sensor chip according to claim 1, which is characterized in that the master control core
On piece has 2LA electricity connection end, is configured to 2LA different address, and it is correspondingly connected with each test chip.
6. the array test method of image sensor chip according to claim 1, which is characterized in that the master control core
The corresponding test chip for being sent to specified address of control instruction is controlled the survey of the image sensor chip of array arrangement by piece
Examination.
7. the array test method of image sensor chip according to claim 6, which is characterized in that the master control core
Control instruction is directly sent to test chip by being electrically connected line by piece.
8. the array test method of image sensor chip according to claim 6, which is characterized in that each test core
The control instruction of main control chip is successively transmitted to adjacent test chip by piece.
9. the array test method of image sensor chip according to claim 1, which is characterized in that further include: institute
It states main control chip to test each test chip, and records the corresponding address of fault test chip.
10. the array test method of image sensor chip according to claim 1, which is characterized in that each test
It is bidirectional data transfers between chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810426558.4A CN110456251A (en) | 2018-05-07 | 2018-05-07 | The array test method of image sensor chip |
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| CN201810426558.4A CN110456251A (en) | 2018-05-07 | 2018-05-07 | The array test method of image sensor chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113884199A (en) * | 2021-09-28 | 2022-01-04 | 深圳市海谱纳米光学科技有限公司 | Calibration device and calibration method for MEMS Fabry-Perot cavity chip |
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