CN104833446B - A kind of CMOS TEMPs chip test system - Google Patents
A kind of CMOS TEMPs chip test system Download PDFInfo
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Abstract
The present invention relates to a kind of CMOS TEMPs chip test system.Including temperature control incubator and the FPGA module being placed in the temperature control incubator, chip carrying module to be measured, LCD display module, DAC-circuit, low-pass filter circuit for carrying TEMP chip to be measured；The temperature control incubator is carried out the adjust automatically of the test temperature of TEMP chip to be measured by FPGA module control；FPGA module is by the chip carrying module to be measured for TEMP chip to be measured provides test sequence, and by DAC-circuit and low-pass filter circuit for TEMP chip to be measured provides standard sine signal, the signal that TEMP chip to be measured is exported is compared with standard sine signal, and then processes the parameter for obtaining TEMP chip to be measured；LCD display module is used to realize the display of the parameter of TEMP chip to be measured when man-machine interaction and test.Used device of the present invention is few, builds simple, and expansibility is strong, and building just can complete and testing for simple hardware carrying platform is only needed for different chips to be measured.
Description
Technical field
The present invention relates to a kind of CMOS TEMPs chip test system.
Background technology
CMOS temperature transmitter chip, it is general mainly by Sigma-Delta ADC in temperature sensing circuit, piece and some
Interface circuit is collectively constituted, and the test of traditional CMOS temperature transmitter chip performance, test circuit is complicated, and needs work
Personnel are tested manually, and automaticity is not high.
The content of the invention
It is an object of the invention to provide a kind of CMOS TEMPs chip test system, the system building is simple, can open up
Malleability is strong, and building just can complete and testing for simple hardware carrying platform is only needed for different chips to be measured.
To achieve the above object, the technical scheme is that：A kind of CMOS TEMPs chip test system, including temperature
Temperature-controlled box and the FPGA module being placed in the temperature control incubator, the chip carrying mould to be measured for carrying TEMP chip to be measured
Block, LCD display module, DAC-circuit, low-pass filter circuit；
The temperature control incubator is carried out the automatic tune of the test temperature of TEMP chip to be measured by FPGA module control
It is whole；
The FPGA module by the chip carrying module to be measured for TEMP chip to be measured provides test sequence, and
By the DAC-circuit and low-pass filter circuit for TEMP chip to be measured provides standard sine signal, in different test temperature
Under degree, the signal that TEMP chip to be measured is exported is compared with standard sine signal, and then process acquisition TEMP to be measured
The parameter of chip is specific to be：Treating testing temperature sensing chip by FPGA module carries out the data acquisition of a cycle, and to this
Data carry out Fourier transformation；Then the value after to Fourier transformation is calculated, you can obtain TEMP core to be measured
Piece includes the ratio between side-play amount, signal to noise ratio, gain, signal and noise distortion, the parameter of total harmonic distortion；
The LCD display module is used to realize the display of the parameter of TEMP chip to be measured when man-machine interaction and test.
In an embodiment of the present invention, the mode of the FPGA module generation test sequence is：By to input FPGA's
Fixed frequency clock source carries out scaling down processing, obtains the least unit time of sequential needed for TEMP chip to be measured, passes through
To the least unit time counting, low and high level signal to the TEMP core to be measured is exported according to count value FPGA module
Piece, until count value reaches the cycle of sequential needed for TEMP chip to be measured, completes the output of a cycle clock signal.
In an embodiment of the present invention, the FPGA module carries out the survey of TEMP chip to be measured to the temperature control incubator
Try temperature adjust automatically mode be：
S21：By setting a standard temperature being connected with the FPGA module at TEMP chip testing to be measured
Degree sensor；
S22：Initial test temperature value T and interval when TEMP chip testing to be measured is set by FPGA module are tested
Temperature value △ T；
S23：Temperature control incubator current temperature value T1 is detected by standard temperature sensor, and is sent to the FPGA module；
S24：FPGA module compares temperature control incubator current temperature value T1 with starting test temperature value T, according to comparative result
Control temperature control incubator is heated up or is lowered the temperature accordingly, until the temperature value after adjustment is consistent with initial test temperature value T, is carried out
TEMP chip testing to be measured at this temperature；After the completion for the treatment of to test at this temperature, FPGA module control temperature control incubator heat up or
Cooling, until the temperature value T2 of standard temperature sensor detection is consistent with T+ △ T, carries out TEMP chip to be measured at this temperature
Test；Similarly, until completing all test temperatures adjustment of chip.
In an embodiment of the present invention, the FPGA module stores sine wave quantization parameter by built-in ROM.
In an embodiment of the present invention, key-press module also is connected with the FPGA module including one, it is described in order to adjust
FPGA module is the sinusoidal signal of TEMP chip output to be measured.
In an embodiment of the present invention, the FPGA module uses Altera DE2-115.
Compared to prior art, the invention has the advantages that：
1st, method of testing has the ability of very strong programmability and real-time processing data；
2nd, used device is few, builds simply, and expansibility is strong；Simple hardware is only needed to carry for different chips to be measured
Building for platform can just complete test；
3rd, the automation in environment temperature test process is realized, the output of manpower is greatly reduced.
Brief description of the drawings
Fig. 1 is invention system theory diagram of the present invention.
Fig. 2 timing diagrams for needed for the TEMP chip to be measured of an example of the invention.
Fig. 3 is that FPGA module sequential of the present invention produces flow chart.
Fig. 4 is that FPGA module sinusoidal signal of the present invention produces flow chart.
Fig. 5 is FPGA module flow chart of data processing figure of the present invention.
Fig. 6 is temperature control incubator control flow chart of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawings, technical scheme is specifically described.
As shown in figures 1 to 6, a kind of CMOS TEMPs chip test system of the invention, including temperature control incubator and it is placed in institute
State the FPGA module in temperature control incubator（FPGA development board models：Altera DE2-115）, for carrying TEMP core to be measured
The chip carrying module to be measured of piece, LCD display module, DAC-circuit, low-pass filter circuit；
The temperature control incubator is carried out the automatic tune of the test temperature of TEMP chip to be measured by FPGA module control
It is whole；
The FPGA module by the chip carrying module to be measured for TEMP chip to be measured provides test sequence, and
By the DAC-circuit and low-pass filter circuit for TEMP chip to be measured provides standard sine signal, in different test temperature
Under degree, the signal that TEMP chip to be measured is exported is compared with standard sine signal, and then process acquisition TEMP to be measured
The parameter of chip is specific to be：Treating testing temperature sensing chip by FPGA module carries out the data acquisition of a cycle, and to this
Data carry out Fourier transformation；Then the value after to Fourier transformation is calculated, you can obtain TEMP core to be measured
Piece includes the ratio between side-play amount, signal to noise ratio, gain, signal and noise distortion, the parameter of total harmonic distortion；
The LCD display module is used to realize the display of the parameter of TEMP chip to be measured when man-machine interaction and test.
In the present embodiment, the mode of the FPGA module generation test sequence is：By the fixed frequency to being input into FPGA
Clock source carries out scaling down processing, the least unit time of sequential needed for TEMP chip to be measured is obtained, by the minimum
Unit interval is counted, and low and high level signal to the TEMP chip to be measured is exported according to count value FPGA module, until meter
Numerical value reaches the cycle of sequential needed for TEMP chip to be measured, completes the output of a cycle clock signal.
To realize automatically controlling for chip testing temperature, the FPGA module carries out treating that testing temperature is passed to the temperature control incubator
The adjust automatically mode of the test temperature of sense chip is：
S21：By setting a standard temperature being connected with the FPGA module at TEMP chip testing to be measured
Degree sensor；
S22：Initial test temperature value T and interval when TEMP chip testing to be measured is set by FPGA module are tested
Temperature value △ T；
S23：Temperature control incubator current temperature value T1 is detected by standard temperature sensor, and is sent to the FPGA module；
S24：FPGA module compares temperature control incubator current temperature value T1 with starting test temperature value T, according to comparative result
Control temperature control incubator is heated up or is lowered the temperature accordingly, until the temperature value after adjustment is consistent with initial test temperature value T, is carried out
TEMP chip testing to be measured at this temperature；After the completion for the treatment of to test at this temperature, FPGA module control temperature control incubator heat up or
Cooling, until the temperature value T2 of standard temperature sensor detection is consistent with T+ △ T, carries out TEMP chip to be measured at this temperature
Test；Similarly, until completing all test temperatures adjustment of chip.
In the present embodiment, the FPGA module stores sine wave quantization parameter by built-in ROM.
In the present embodiment, key-press module also is connected with the FPGA module including one, in order to adjust the FPGA module
It is the sinusoidal signal of TEMP chip to be measured output.
It is to allow persons skilled in the art to know more about technical scheme, below by way of specific works of the invention
Principle and example tell about detailed description.
It is of the invention main by FPGA module, chip carrying module to be measured, LCD display module, DAC-circuit, LPF electricity
Road and automatic temperature-controlled module（Including temperature control incubator, standard temperature sensor）Composition, as shown in figure 1, its operation principle is：It is whole
Individual device produces sine wave signal by FPGA（By outside DAC and low pass filter）, by resulting signal as to be measured
TEMP chip（It is equipped on the board mounting in chip carrying module to be measured）Input stimulus source.TEMP chip to be measured
According to the sequential that FPGA is provided, the sine wave of input is changed into data signal.FPGA is gathered and is processed signal, finally
The parameter of correlation is obtained, and is shown on LCD.The function introduction of specific each module is as follows：
1st, FPGA module
（1）Because the test of CMOS TEMP chips generally requires sequential（Be illustrated in figure 2 example treats testing temperature
Timing diagram needed for sensing chip, the signal port and function declaration of the timing diagram are shown in Table 1）, so pass through FPGA in the application
Produce sequential.The clock signal ratio produced by FPGA is more accurate with 51 single-chip microcomputers or STM32, grade of the error in several ns；Phase
Than producing clock signal with logic analyser in more accurately, then FPGA generations are more convenient and simple, and precision is also fully achieved will
Ask.
As shown in figure 3, the mode of its generation sequential is：A clock source of 100MHZ is firstly introduced into, because treating testing temperature
The minimum time unit of sensing chip timing requirements is 0.5us so clock is carried out into 50 scaling down processings, is clock source frequency dividing
2MHZ（0.5us）.The cycle of sequential is 200us, so the clock in 2MHZ is given a definition a parameter count, when clock rises
Along when counted, write 399 all over（0-399 is exactly 400 countings）Number resets, and the cycle that is achieved that is 200us.As long as then
According to the sequential of chip to be measured requirement, judge the value of count to each value tax 1 in sequential or set to 0 just can be according to sequential
Figure output waveform.Wherein RST is more special, it is only necessary in first cycle reset once, so should after a cycle
Indirect assignment 0.
（2）As shown in figure 4, in order to give TEMP chip to be measured one sine signal source of standard, FPGA module is also needed
Pumping signal is provided to TEMP chip to be measured, the signal and standard sine signal of TEMP chip output relatively more to be measured are
The relevant parameter of chip can be drawn.Sinusoidal signal is that the sine wave read inside the good ROM of predefined by FPGA quantifies ginseng
Number, then by outside high accuracy DAC and the sine wave of a low pass filter generation standard.And in order that design circuit tool
There is autgmentability, add frequency control word to be set to the sine wave of output in code adjustable.
（3）As shown in figure 5, using the sine wave of standard as the input in chip to be measured, corresponding number is had in output end
According to output, data processing module is exactly to complete collection, parameter calculating, the output of result of calculation to chip data to be measured.
FPGA first carries out the collection of a cycle to the parameter of chip to be measured, and the data that will be gathered are put into one group of FPGA
Register in.The parameter testing of this project is calculated in frequency domain, so needing to carry out the parameter in register
Fast Fourier Transform (FFT), and the value storage that will be obtained is in another register.Counted accordingly by the parameter for treating
Calculate and can obtain side-play amount（OFFSET）, signal to noise ratio (SNR), gain（GAIN）, the ratio between signal and noise distortion (SINAD)
, total harmonic distortion (THD) etc. parameter.
For example to obtain side-play amount to only need to carry out Fast Fourier Transform (FFT) to the data for gathering, the multifrequency thresholding for obtaining
First group of data, i.e. the DC component of the sine wave after ADC conversions, this group of data include value of real part, the imaginary part of DC component
Value and the order of magnitude（If the order of magnitude is the first power that 1 that real part or imaginary part are multiplied by e）.This group of data are carried out with multiplication, is opened
Side can be obtained by the amplitude of DC component, and this amplitude is exactly that we will obtain side-play amount.It is similar to side-play amount, if it is desired to
Signal to noise ratio is obtained, then to use the 2nd group after Fourier transformation to the 255th group data, these data are first harmonic（Base
Ripple）To n times harmonic wave（Noise）.Data equally are carried out with the amplitude that computing obtains each harmonic wave, according to the formula for calculating signal to noise ratio：
As long as with first harmonic divided by other harmonic waves summation, computing of then taking the logarithm finally is multiplied by 20 and can be obtained by
Signal to noise ratio（In units of DB）.Other specification is similar with the two not to be repeated.
In order to save FPGA resource, we employ some special algorithms when multiplication division and evolution is carried out
Replacement directly with multiplier or calls IP kernel.
First, Booth algorithm（Multiplication）
Booth algorithm just can calculate the product of complement data only with addition, subtraction and right-shift operation.To multiplier from low level
Start to judge, determine to carry out addition or subtraction according to two situations of data bit, product term moves right one every time.Sentence
Two disconnected data bit are present bit and its one, the right, need to increase a service bit 0 when initial.According to yiWith yi+1（Quilt
Two adjacent positions of multiplier）Value, the mode of operation of Booth algorithm single cycle depends on expression formula (yi+1 - yi) value,
It is represented by following table：
Multiplication is converted into serial plus-minus and shift operation by this algorithm, so as to save a large amount of logical resources.
2nd, classical division
It is that positive number is divided by due to doing during division arithmetic, so using without symbol classics division.This algorithm converts division
It is serial comparing and shift operation, so as to save a large amount of logical resources.
1. compare the size of remainder (dividend) and divisor every time, determine that business is 1 or 0；
2. a subtraction is often done, holding remainder is motionless, and low level is covered by dividend low level, then subtracts the divisor after moving to right.
The Expenditure Levels of each algorithm resource are given below：Wherein IP_core refers to the synopsys that quartus softwares are carried
The IP kernel of company；ALUTs refers to the number of look-up table；ALMs refers to adaptive logic unit number；Reg refers to programmable register
Number.
It can be seen that Booth algorithm and classical division can effectively reduce the consumption of resource, although output time delay can be increased, but
It is that, because the working frequency of FPGA is higher, and to compare can be what is ignored the time realized with whole system, so increased
Output time delay has no effect on overall performance.
2nd, chip carrying module to be measured
Most of function is all directly realized by FPGA in the design, can largely reduce the design of peripheral circuit, but still
The TEMP chip to be measured that different specification or model need to be directed to provides different board mountings.The main effect of board mounting be by
Chip to be measured is connected with FPGA.Carry module to be connected completely by arranging pin and female seat with FPGA module, greatly reduce and pass through
Interference caused by the connection signal such as Du Pont's line.
3rd, LCD display module
LCD module provide human-computer interaction interface, including the frequency and relevant parameter of sinusoidal excitation display.
4th, DAC-circuit, low-pass filter circuit
Main Function is that the pumping signal that FPGA module is exported is converted into the sine wave signal of standard, and is exported to be measured
TEMP chip.
5th, automatic temperature-controlled module
Require that temperature is tested once from -40 DEG C to 80 DEG C at interval of 5 DEG C in test process, in order to improve testing efficiency,
The automaticity of test is improved, we devise a temperature automatically controlled module in systems.The module includes a high accuracy
Standard temperature sensor, its place position it is close from TEMP chip to be measured, so due to the body inside temperature control incubator
Product is general than larger, therefore the temperature value that the sensor measurement is obtained is also more accurate than incubator nominal value.So, we can pass through
FPGA module control incubator carries out heating and cooling, and the full-automatic testing of testing temperature sensing chip is treated in realization.Temperature control can specifically be seen
Depending on the control mode of incubator, such as the external interface that the incubator used by us has individual RS232 agreements can be used to control incubator
, then with this external interface of incubator be connected with special wire for FPGA module output control port by heating and cooling（If incubator is
The interface of other agreements, or wave point also can similarly be realized）.Automatic temperature-adjusting test flow chart is shown in Fig. 6.For example, from -40 DEG C
Tested once at interval of 5 DEG C to 80 DEG C, automatic temperature-controlled module work is as follows：We preset in a control program will start
The actual temp value of survey（-40℃）, the temperature and setting value that standard temperature sensor is sensed contrasted, if it is different,
Then correspondingly control incubator is heated up or is lowered the temperature, and is preset until the temperature value that standard temperature sensor is transmitted reaches
After value, and stabilization certain hour, the test of TEMP chip to be measured is proceeded by, FPGA reads data, data are carried out
Treatment storage.After the completion of the relevant data acquisition of chip to be measured, FPGA is communicated with incubator, make the temperature change of incubator to-
35 DEG C, tested again after checking temperature stabilization, by that analogy, until test is fully completed.Can be saved significantly by the module
About manpower, realizes the test under full-automatic temperature environment.
The present invention is directed to different TEMP chips to be measured, it is desirable to have different sequential is provided.Before platform test,
All sequential needed for RTL code obtains us are write by FPGA.By simple hardware design carry platform, by generate when
Sequence enters to carry the corresponding port of chip on platform, makes chip under test normal work.After obtaining the communication protocol of test incubator, design
Program, realizes automatic temperature-adjusting controls of the FPGA to incubator.
Then write RTL code and produce the sine-wave excitation of standard to input to by outside DAC-circuit by FPGA and treat
Chip is surveyed, the signal that chip to be measured is produced then is returned into FPGA, storage is in a register.FPGA can carry out relevant treatment,
Draw the parameter of our needs and shown on LCD.
Above is presently preferred embodiments of the present invention, all changes made according to technical solution of the present invention, produced function work
During with scope without departing from technical solution of the present invention, protection scope of the present invention is belonged to.
Claims (4)
1. a kind of CMOS TEMPs chip test system, it is characterised in that：Including temperature control incubator and it is placed in the temperature control incubator
Interior FPGA module, the chip carrying module to be measured for carrying TEMP chip to be measured, LCD display module, DAC-circuit,
Low-pass filter circuit；
The temperature control incubator is carried out the adjust automatically of the test temperature of TEMP chip to be measured by FPGA module control；
The FPGA module, for TEMP chip to be measured provides test sequence, and is passed through by the chip carrying module to be measured
The DAC-circuit and low-pass filter circuit provide standard sine signal for TEMP chip to be measured, under different test temperatures,
The signal that TEMP chip to be measured is exported is compared with standard sine signal, and then processes acquisition TEMP chip to be measured
Parameter is specific to be：Treating testing temperature sensing chip by FPGA module carries out the data acquisition of a cycle, and the data are entered
Row Fourier transformation；Then the value after to Fourier transformation is calculated, you can obtaining TEMP chip to be measured includes
The ratio between side-play amount, signal to noise ratio, gain, signal and noise distortion, the parameter of total harmonic distortion；
The LCD display module is used to realize the display of the parameter of TEMP chip to be measured when man-machine interaction and test；
The FPGA module produces the mode of test sequence to be：Carried out at frequency dividing by the fixed frequency clock source for being input into FPGA
Reason, obtains the least unit time of sequential needed for TEMP chip to be measured, by the least unit time counting, according to meter
Numerical value FPGA module exports low and high level signal to the TEMP chip to be measured, until count value reaches TEMP to be measured
In the cycle of sequential needed for chip, complete the output of a cycle clock signal；
The adjust automatically mode that the FPGA module carries out the test temperature of TEMP chip to be measured to the temperature control incubator is：
S21：By setting a normal temperature biography being connected with the FPGA module at TEMP chip testing to be measured
Sensor；
S22：Initial test temperature value T and interval test temperature when TEMP chip testing to be measured is set by FPGA module
Value △ T；
S23：Temperature control incubator current temperature value T1 is detected by standard temperature sensor, and is sent to the FPGA module；
S24：FPGA module compares temperature control incubator current temperature value T1 with starting test temperature value T, according to comparative result control
Temperature control incubator is heated up or is lowered the temperature accordingly, until the temperature value after adjustment is consistent with initial test temperature value T, carries out the temperature
TEMP chip testing to be measured under degree；After the completion for the treatment of to test at this temperature, FPGA module control temperature control incubator heats up or lowers the temperature,
Until the temperature value T2 of standard temperature sensor detection is consistent with T+ △ T, TEMP chip testing to be measured at this temperature is carried out；
Similarly, until completing all test temperatures adjustment of chip.
2. a kind of CMOS TEMPs chip test system according to claim 1, it is characterised in that：The FPGA module
Sine wave quantization parameter is stored by built-in ROM.
3. a kind of CMOS TEMPs chip test system according to claim 1, it is characterised in that：Also include one and institute
FPGA module connection key-press module is stated, in order to adjust the sinusoidal letter that the FPGA module is TEMP chip output to be measured
Number.
4. a kind of CMOS TEMPs chip test system according to claim 1, it is characterised in that：The FPGA module
Using Altera DE2-115.
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| CN106054058B (en) * | 2016-04-28 | 2019-01-25 | 芯海科技（深圳）股份有限公司 | One kind can be to multiple sigma-delta ADC chip testings and temperature controlled system and method |
| CN106679849B (en) * | 2016-12-19 | 2019-02-19 | 北京兆易创新科技股份有限公司 | A kind of test method and device of MCU temperature sensor |
| CN108061611B (en) * | 2017-12-10 | 2019-08-09 | 北京工业大学 | A kind of device and method using FPGA embedded toroidal oscillator measurement Temperature Distribution |
| CN111678613A (en) * | 2020-06-11 | 2020-09-18 | 江苏华创微系统有限公司 | DSP chip shell temperature detection method based on shell interior temperature sensing |
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