CN104035021A - Testing method and system of clock chip - Google Patents

Testing method and system of clock chip Download PDF

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CN104035021A
CN104035021A CN201310074100.4A CN201310074100A CN104035021A CN 104035021 A CN104035021 A CN 104035021A CN 201310074100 A CN201310074100 A CN 201310074100A CN 104035021 A CN104035021 A CN 104035021A
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clock chip
crystal oscillator
oscillator frequency
numerical value
test
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CN104035021B (en
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郭宝胆
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Nanjing Hongtai Semiconductor Technology Co ltd
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SHANGHAI MACROTEST SEMICONDUCTOR Inc
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Abstract

The invention, which relates to the integrated circuit testing field, discloses a testing method and system of a clock chip. According to the invention, on the basis of the clock chip testing principle, a testing load plate and a tested device interface are designed and arranged. When the memory of the clock chip works normally, the precision of the crystal oscillator frequency can be tested; a high-precision frequency meter is used for measuring the crystal oscillator frequency in a working temperature range of the clock chip; a temperature compensation value of the crystal oscillator frequency in the working temperature range of the clock chip is calculated according to the measuring value and is stored into the memory of the clock chip; and the temperature compensation value is read, and when the read value meets a predetermined simulated curve, that the clock chip passes the temperature compensation test successfully is determined. Therefore, temperature compensation testing is realized in a wide temperature range from minus 40 DEG C to 85 DEG C for the crystal oscillator frequency of the clock chip; and the clock precision is improved.

Description

The method of testing of clock chip and system
Technical field
The present invention relates to integrated circuit testing field, particularly clock chip method of testing and system.
Background technology
Clock chip is built-in 32.768kHz crystal oscillator, with I 2c bus interface is communication mode, except having calendar and time clock feature, also has warning, fixed cycle Interruption, and the time is upgraded the function such as 32.768kHz frequency output of interrupting and enabling OE, is described as follows:
1. real-time clock function: this function is used to set and read year, month, day, week, time, point, second temporal information, the time is that rear two bit digital represent, anyly can be treated as the leap year by 4 times of dividing exactly and process;
2. Interruption generating function: fixed cycle Interruption generating function can produce the interrupt event of a fixed cycle, the fixed cycle can the random time between 244.14uS to 4095 minute be set;
3. the time is upgraded interrupt function: this function can be according to the timing setting of internal clocking, and per second or per minute produces an interrupt event;
4. warning interrupt function: this function can produce an interruption according to alarm settings.
The time error of clock chip is mainly derived from the frequency error of crystal oscillator in clock chip, and the frequency error of crystal oscillator is mainly because temperature variation causes, so generally need to take into account trip temperature compensation in the time that clock chip designs.At present, it is at 40 degrees below zero that the frequency error of this clock chip is tested, and normal temperature 25 is spent, 55 degree, and 80 degree four processes tests, and make simulation curve; Its compensation way is: employing be the mode of design, digital compensation is after crystal oscillating circuit output 32.768kHz, the compensation of carrying out in the process of frequency dividing circuit frequency division, 32.768kHz does not carry out temperature compensation; Adopt 20S to compensate working method once, the time gate limit value of test should be set to the integral multiple of 20S or 20S, if can only be arranged to 10S, please test for continuous two times, averages.Owing to not carrying out temperature compensation test, therefore probably cause clock chip unreliable in the precision of some temperature range, thereby make clock chip can not be operated in reliably wider temperature range.
Summary of the invention
The object of the present invention is to provide a kind of clock chip method of testing and system, make the crystal oscillator frequency of clock chip in the wider temperature range of 40 degrees below zero to 85 degree, obtain temperature compensation test, improve clock accuracy.
For solving the problems of the technologies described above, embodiments of the present invention provide a kind of clock chip method of testing, comprise following steps:
A. according to the test philosophy of clock chip, carry out the front preparation of test, comprise: on test platform, edit test procedure; Connect described test platform, test load plate, measured device interface, described clock chip and frequency meter;
B. carry out described test procedure, judge whether the storer of described clock chip can normally work; And in the time judging that described storer is normally worked, adopt described frequency meter to measure the crystal oscillator frequency of described clock chip, check the precision of described crystal oscillator frequency; And the convert numerical value that obtains of the crystal oscillator frequency measuring is write in the first default address of described storer;
If C. the precision of described crystal oscillator frequency meets the frequency requirement of described clock chip, in the operating temperature range of described clock chip, be taken to few four temperature spots, the crystal oscillator frequency of clock chip described in proportion instrumentation amount, and the numerical value that the crystal oscillator frequency measuring is converted in numerical value and the described first default address obtaining writes respectively in the second default address field; Wherein, the described second default number of address field and the number of described temperature spot are corresponding;
D. according to the numerical value in the described second default address field, calculate in the operating temperature range of described clock chip, the temperature compensation value of described crystal oscillator frequency, and deposit in the 3rd default address field of described storer;
E. read the numerical value in the described the 3rd default address field, the numerical value reading described in observation; And in the time that the described numerical value reading meets predefined simulation curve, judge that described clock chip tests by temperature compensation.
Embodiments of the present invention also provide a kind of clock chip test macro, comprise: test platform, test load plate, measured device interface and frequency meter; Described test platform connects described test load plate; Described test load plate connects described measured device interface, and described measured device interface connects described clock chip; Described frequency meter is connected with described clock chip and described test platform respectively;
Wherein, on described test platform, edit test procedure;
Described test platform is carried out described test procedure, judges whether the storer of described clock chip can normally work; And in the time judging that described storer is normally worked, adopt described frequency meter to measure the crystal oscillator frequency of described clock chip, check the precision of described crystal oscillator frequency; And the convert numerical value that obtains of the crystal oscillator frequency measuring is write in the first default address of described storer;
In the time that the precision of judging described crystal oscillator frequency meets the frequency requirement of described clock chip, described test platform is in the operating temperature range of described clock chip, be taken to few four temperature spots, the crystal oscillator frequency of clock chip described in proportion instrumentation amount, and the numerical value that the crystal oscillator frequency measuring is converted in numerical value and the described first default address obtaining writes respectively in the second default address field; Wherein, the described second default number of address field and the number of described temperature spot are corresponding;
Described test platform, according to the numerical value in the described second default address field, calculates in the operating temperature range of described clock chip, the temperature compensation value of described crystal oscillator frequency, and deposit in the 3rd default address field of described storer;
Described test platform is read the numerical value in the described the 3rd default address field, the numerical value reading described in observation; And in the time that the described numerical value reading meets predefined simulation curve, judge that described clock chip tests by temperature compensation.
Embodiment of the present invention in terms of existing technologies, according to clock chip test philosophy, design manufacturing test load board and measured device interface, in the time that the storer of clock chip can normally be worked, the precision of inspection crystal oscillator frequency, and in the operating temperature range of clock chip, adopt high precision frequency meter to measure crystal oscillator frequency, and calculate in the operating temperature range of clock chip according to measured value, the temperature compensation value of crystal oscillator frequency, deposit the storer of clock chip in, read again afterwards, and in the time that the numerical value reading meets predefined simulation curve, judgement clock chip is tested by temperature compensation.Make the crystal oscillator frequency of clock chip in the wider temperature range of 40 degrees below zero to 85 degree, obtain temperature compensation test, improve clock accuracy.
In addition, can judge whether the storer of described clock chip can normally work by following sub-step:
According to clock 400kHz, all addresses after the reserved address of described storer write Arbitrary Digit, and read, and compare, if sense data is consistent with data writing, judge that described storer can normally work;
Wherein, while writing, after write an address more; Write fashionable 8 clock period that take, and wait for 2.5 milliseconds the 6th clock period; While reading, before address of mutiread.
By write Arbitrary Digit in storer, and read, compared, can check storer whether can normally work, simple to operate, be easy to realize.
In addition, can be by the following formula crystal oscillator frequency measuring that converts: (f-32768)/32768*1000000; Wherein, f is the crystal oscillator frequency measuring.Make the storer precision of clock chip reach 0.00001Hz by this conversion, to meet the strict demand of clock chip to frequency accuracy.
In addition, can get four temperature spots, be respectively 40 degrees below zero, 25 degree, 55 degree, 80 degree.By measuring the crystal oscillator frequency of clock chip under representative temperature, can reflect the temperature variant relation of frequency error of crystal oscillator, make temperature compensation test more closing to reality application, thereby make test result more reliable.
In addition, can adopt high precision, with the frequency meter of general purpose interface bus gpib interface; The crystal oscillator frequency that described frequency meter measures is sent on described test platform by general purpose interface bus GPIB communication.The crystal oscillator frequency of measuring clock chip by the frequency meter of high precision, can meet the strict demand of clock chip to frequency accuracy.
Brief description of the drawings
Fig. 1 is according to the process flow diagram of the clock chip method of testing of first embodiment of the invention;
Fig. 2 is according to the structural representation of the clock chip test macro of second embodiment of the invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, the embodiments of the present invention are explained in detail.But, persons of ordinary skill in the art may appreciate that in the each embodiment of the present invention, in order to make reader understand the application better, many ins and outs are proposed.But, even without these ins and outs and the many variations based on following embodiment and amendment, also can realize the each claim of the application technical scheme required for protection.
The first embodiment of the present invention relates to a kind of clock chip method of testing, the method makes the crystal oscillator frequency of clock chip in the wider temperature range of 40 degrees below zero to 85 degree, obtain temperature compensation test, improve clock accuracy, thereby make clock chip can be applicable to the wider temperature range of 40 degrees below zero to 85 degree, idiographic flow as shown in Figure 1, comprises following steps:
Step 101, according to the test philosophy of clock chip, carries out the front preparation of test, comprises: on test platform, edit test procedure; Connecting test platform, test load plate, measured device interface, clock chip and frequency meter.
Specifically, comprise following sub-step:
According to the test philosophy of clock chip, design manufacturing test load board and measured device (DUT) interface.
According to the test specification of clock chip, on test platform, edit test procedure; Such as, according to test specification, on MTS747, edit test procedure.
Connect test load plate and measured device interface, and be ready to being connected of clock chip and measured device interface and frequency meter.
Step 102, carries out test procedure, and whether the storer of clock chip can normally be worked and be tested;
Step 103, judges whether the storer of clock chip can normally work; In this way, perform step 104; As no, finish this test.
Can judge whether the storer of clock chip can normally work by following sub-step:
According to clock 400kHz, all addresses after the reserved address of storer write Arbitrary Digit, and read, and compare, if sense data is consistent with data writing, determine memory can normally be worked; Wherein, while writing, after write an address more; Write fashionable 8 clock period that take, and wait for 2.5 milliseconds the 6th clock period; While reading, before address of mutiread.
Such as, in clock chip, there are 255 memory addresss, 00H-0FH address is as reserved address, all addresses according to clock 400kHz after writing, while writing, after write an address (address date can be write Arbitrary Digit) more, 8 clock period (clk), wait for 2.5mS at the 6th clk; While reading, before address of mutiread.
By write Arbitrary Digit in storer, and read, compared, can check storer whether can normally work, simple to operate, be easy to realize.
Step 104, the crystal oscillator frequency of proportion instrumentation amount clock chip, the precision of inspection crystal oscillator frequency; And the crystal oscillator frequency measuring is converted in the first default address of the numerical value write store that obtains.
Clock chip is stricter for frequency requirement, is accurate to 0.00001Hz, so need external professional frequency meter, the value on frequency meter is passed on MTS747; The crystal oscillator frequency that root is measured converts according to formula (f-32768)/32768*1000000, and the value that conversion is obtained write 12H(, and 12H is the first default address).Make the storer precision of clock chip reach 0.00001Hz by this conversion, to meet the strict demand of clock chip to frequency accuracy.
In addition, what deserves to be explained is, present embodiment adopts high precision, the frequency meter of band general purpose interface bus (GPIB) interface, and the crystal oscillator frequency that frequency meter measures is sent on test platform by GPIB communication.The crystal oscillator frequency of measuring clock chip by the frequency meter of high precision, can meet the strict demand of clock chip to frequency accuracy.
Step 105, judges whether the precision of crystal oscillator frequency meets the frequency requirement of clock chip, in this way, performs step 106; As no, finish this test.
Step 106, in the operating temperature range of clock chip, be taken to few four temperature spots, the crystal oscillator frequency of proportion instrumentation amount clock chip, and the numerical value that the crystal oscillator frequency measuring is converted in numerical value and the first default address obtaining writes respectively in the second default address field.Wherein, the second default number of address field and the number of temperature spot are corresponding.
Such as, in the time that clock chip is tested, can get four temperature spots, be respectively 40 degrees below zero, 25 degree, 55 degree, 80 degree tests, along with the variation of temperature, the value in 12H address and the frequency values of reading are all different, read respectively the value of 12H address and crystal oscillator frequency that each temperature survey the obtains numerical value after converting; By measuring the crystal oscillator frequency of clock chip under representative temperature, can reflect the temperature variant relation of frequency error of crystal oscillator, make temperature compensation test more closing to reality application, thereby make test result more reliable.
Specifically, at 40 degrees below zero, the numerical value after the crystal oscillator frequency measuring is converted and 12H address date writing address 1AH respectively, 1BH, 1CH, at this, 1AH, 1BH, 1CH is the second default address field that 40 degrees below zero is corresponding; At subzero 10 degree, the numerical value after the crystal oscillator frequency measuring is converted and 12H address date writing address 23H respectively, 24H, 25H; At 25 degree, the numerical value after the crystal oscillator frequency measuring is converted and 12H address date writing address 17H respectively, 18H, 19H; At 55 degree, the numerical value after the crystal oscillator frequency measuring is converted and 12H address date writing address 1DH respectively, 1EH, 1FH; At 80 degree, the numerical value after the crystal oscillator frequency measuring is converted and 12H address date writing address 20H respectively, 21H, 22H.
Step 107, according to the numerical value in the second default address field, calculates in the operating temperature range of clock chip, the temperature compensation value of crystal oscillator frequency, and deposit in the 3rd default address field of storer.
In the present embodiment, can adopt to solve quaternary cubic equation and carry out analog temperature compensation curve, specifically, 40 degrees below zero, reads 1AH, and the worthwhile y1 that is of 1BH address, reads the worthwhile x1 of being of 1CH address; 25 degree, read 17H, and the worthwhile y2 that is of 18H address, reads the worthwhile x2 of being of 19H address; 55 degree, read 1DH, and the worthwhile y3 that is of 1EH address, reads the worthwhile x3 of being of 1FH address; 80 degree, read 20H, and the worthwhile y4 that is of 21H address, reads the worthwhile x4 of being of 22H address; Substitution y=A*x*x*x+B*x*x+C*x+D, asks for quaternary cubic equation respectively, draws A, B, C, D.Then, start to be to these 218 addresses of FFH(25H-FFH the 3rd default address field from 25H address), convert sexadecimal (25H-FFH) to decimal number, as x, all in substitution y=A*x*x*x+B*x*x+C*x+D, draw y, then y value is write respectively in these 218 addresses of 25H-FFH.
Step 108, reads the numerical value in the 3rd default address field, observes the numerical value reading.Namely read the data in this sector address of 25H-FFH, obtain simulation curve.Due to the interior employing quaternary of step 107 cubic equation, therefore, what this step obtained should be para-curve.
Step 109, the numerical value that reads of judgement meets predefined simulation curve, in this way, judges that clock chip tests (step 110) by temperature compensation; As no, judge that clock chip do not test (step 111) by temperature compensation, finish this test.
That is to say, whether the para-curve of reading by observation is the same with expection, if consistent, thinks that measured clock chip has passed through temperature compensation test.
Compared with prior art, according to clock chip test philosophy, design manufacturing test load board and measured device interface, in the time that the storer of clock chip can normally be worked, the precision of inspection crystal oscillator frequency, and in the operating temperature range of clock chip, adopt high precision frequency meter to measure crystal oscillator frequency, and calculate in the operating temperature range of clock chip according to measured value, the temperature compensation value of crystal oscillator frequency, deposit the storer of clock chip in, read again afterwards, and in the time that the numerical value reading meets predefined simulation curve, judgement clock chip is tested by temperature compensation.Make the crystal oscillator frequency of clock chip in the wider temperature range of 40 degrees below zero to 85 degree, obtain temperature compensation test, improve clock accuracy.
The step of the whole bag of tricks is divided above, just in order being described clearly, can to merge into a step or some step is split while realization, is decomposed into multiple steps, as long as comprise identical logical relation, all in the protection domain of this patent; To adding inessential amendment in algorithm or in flow process or introducing inessential design, but the core design that does not change its algorithm and flow process is all in the protection domain of this patent.
Second embodiment of the invention relates to a kind of clock chip test macro, as shown in Figure 2, comprises: test platform, test load plate, measured device interface and frequency meter; Test platform connecting test load board; Test load plate connects measured device interface, and measured device interface connects clock chip; Frequency meter is connected with clock chip and test platform respectively;
Wherein, on test platform, edit test procedure;
Test platform is carried out test procedure, judges whether the storer of clock chip can normally work; Its concrete test is as follows:
According to clock 400kHz, all addresses after the reserved address of storer write Arbitrary Digit, and read, and compare, if sense data is consistent with data writing, determine memory can normally be worked; Wherein, while writing, after write an address more; Write fashionable 8 clock period that take, and wait for 2.5 milliseconds the 6th clock period; While reading, before address of mutiread.
When test platform is normally worked at determine memory, the crystal oscillator frequency of proportion instrumentation amount clock chip, the precision of inspection crystal oscillator frequency; And the crystal oscillator frequency measuring is converted in the first default address of the numerical value write store that obtains; By the following formula crystal oscillator frequency measuring that converts: (f-32768)/32768*1000000; Wherein, f is the crystal oscillator frequency measuring.
In the time that the precision of judging crystal oscillator frequency meets the frequency requirement of clock chip, test platform, in the operating temperature range of clock chip, is taken to few four temperature spots, such as, get four temperature spots, be respectively 40 degrees below zero, 25 degree, 55 degree, 80 degree; The crystal oscillator frequency of proportion instrumentation amount clock chip, and the numerical value that the crystal oscillator frequency measuring is converted in numerical value and the first default address obtaining writes respectively in the second default address field; Wherein, the second default number of address field and the number of temperature spot are corresponding;
Test platform, according to the numerical value in the second default address field, calculates in the operating temperature range of clock chip, the temperature compensation value of crystal oscillator frequency, and deposit in the 3rd default address field of storer;
Test platform is read the numerical value in the 3rd default address field, observes the numerical value reading; And in the time that the numerical value reading meets predefined simulation curve, judgement clock chip is tested by temperature compensation.
In addition, what deserves to be explained is, because clock chip is stricter for frequency requirement, be accurate to 0.00001Hz, so present embodiment adopts high precision, the frequency meter of band general purpose interface bus (GPIB) interface, the crystal oscillator frequency that frequency meter measures is sent on test platform by GPIB communication.
Be not difficult to find, present embodiment is the system embodiment corresponding with the first embodiment, present embodiment can with the enforcement of working in coordination of the first embodiment.The correlation technique details of mentioning in the first embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the first embodiment.
It is worth mentioning that, each module involved in present embodiment is logic module, and in actual applications, a logical block can be a physical location, can be also a part for a physical location, can also realize with the combination of multiple physical locations.In addition, for outstanding innovation part of the present invention, in present embodiment, the unit not too close with solving technical matters relation proposed by the invention do not introduced, but this does not show not exist in present embodiment other unit.
Persons of ordinary skill in the art may appreciate that the respective embodiments described above are to realize specific embodiments of the invention, and in actual applications, can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.

Claims (10)

1. a clock chip method of testing, is characterized in that, comprises following steps:
A. according to the test philosophy of clock chip, carry out the front preparation of test, comprise: on test platform, edit test procedure; Connect described test platform, test load plate, measured device interface, described clock chip and frequency meter;
B. carry out described test procedure, judge whether the storer of described clock chip can normally work; And in the time judging that described storer is normally worked, adopt described frequency meter to measure the crystal oscillator frequency of described clock chip, check the precision of described crystal oscillator frequency; And the convert numerical value that obtains of the crystal oscillator frequency measuring is write in the first default address of described storer;
If C. the precision of described crystal oscillator frequency meets the frequency requirement of described clock chip, in the operating temperature range of described clock chip, be taken to few four temperature spots, the crystal oscillator frequency of clock chip described in proportion instrumentation amount, and the numerical value that the crystal oscillator frequency measuring is converted in numerical value and the described first default address obtaining writes respectively in the second default address field; Wherein, the described second default number of address field and the number of described temperature spot are corresponding;
D. according to the numerical value in the described second default address field, calculate in the operating temperature range of described clock chip, the temperature compensation value of described crystal oscillator frequency, and deposit in the 3rd default address field of described storer;
E. read the numerical value in the described the 3rd default address field, the numerical value reading described in observation; And in the time that the described numerical value reading meets predefined simulation curve, judge that described clock chip tests by temperature compensation.
2. clock chip method of testing according to claim 1, is characterized in that, in described step B, judges whether the storer of described clock chip can normally work by following sub-step:
According to clock 400kHz, all addresses after the reserved address of described storer write Arbitrary Digit, and read, and compare, if sense data is consistent with data writing, judge that described storer can normally work;
Wherein, while writing, after write an address more; Write fashionable 8 clock period that take, and wait for 2.5 milliseconds the 6th clock period; While reading, before address of mutiread.
3. clock chip method of testing according to claim 1, is characterized in that, in described step B and described step C, by the following formula crystal oscillator frequency measuring that converts:
(f-32768)/32768*1000000;
Wherein, f is the crystal oscillator frequency measuring.
4. clock chip method of testing according to claim 1, is characterized in that, in described step C, gets four temperature spots, is respectively 40 degrees below zero, 25 degree, 55 degree, 80 degree.
5. clock chip method of testing according to claim 1, is characterized in that, in described step B and step C, adopts high precision, with the frequency meter of general purpose interface bus gpib interface; The crystal oscillator frequency that described frequency meter measures is sent on described test platform by GPIB communication.
6. a clock chip test macro, is characterized in that, comprises: test platform, test load plate, measured device interface and frequency meter; Described test platform connects described test load plate; Described test load plate connects described measured device interface, and described measured device interface connects described clock chip; Described frequency meter is connected with described clock chip and described test platform respectively;
Wherein, on described test platform, edit test procedure;
Described test platform is carried out described test procedure, judges whether the storer of described clock chip can normally work; And in the time judging that described storer is normally worked, adopt described frequency meter to measure the crystal oscillator frequency of described clock chip, check the precision of described crystal oscillator frequency; And the convert numerical value that obtains of the crystal oscillator frequency measuring is write in the first default address of described storer;
In the time that the precision of judging described crystal oscillator frequency meets the frequency requirement of described clock chip, described test platform is in the operating temperature range of described clock chip, be taken to few four temperature spots, the crystal oscillator frequency of clock chip described in proportion instrumentation amount, and the numerical value that the crystal oscillator frequency measuring is converted in numerical value and the described first default address obtaining writes respectively in the second default address field; Wherein, the described second default number of address field and the number of described temperature spot are corresponding;
Described test platform, according to the numerical value in the described second default address field, calculates in the operating temperature range of described clock chip, the temperature compensation value of described crystal oscillator frequency, and deposit in the 3rd default address field of described storer;
Described test platform is read the numerical value in the described the 3rd default address field, the numerical value reading described in observation; And in the time that the described numerical value reading meets predefined simulation curve, judge that described clock chip tests by temperature compensation.
7. clock chip test macro according to claim 6, is characterized in that, described test platform judges whether the storer of described clock chip can normally work in the following way:
According to clock 400kHz, all addresses after the reserved address of described storer write Arbitrary Digit, and read, and compare, if sense data is consistent with data writing, judge that described storer can normally work;
Wherein, while writing, after write an address more; Write fashionable 8 clock period that take, and wait for 2.5 milliseconds the 6th clock period; While reading, before address of mutiread.
8. clock chip test macro according to claim 6, is characterized in that, described test platform is by the following formula crystal oscillator frequency measuring that converts:
(f-32768)/32768*1000000;
Wherein, f is the crystal oscillator frequency measuring.
9. clock chip test macro according to claim 6, is characterized in that, described test platform is got four temperature spots, is respectively 40 degrees below zero, 25 degree, 55 degree, 80 degree.
10. clock chip test macro according to claim 6, is characterized in that, described frequency is counted high precision, with the frequency meter of general purpose interface bus gpib interface; The crystal oscillator frequency that described frequency meter measures is sent on described test platform by GPIB communication.
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104833446A (en) * 2015-05-08 2015-08-12 福州大学 CMOS temperature sensing chip test system
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CN108226756A (en) * 2018-01-29 2018-06-29 深圳市兴威帆电子技术有限公司 The test system and its test method of a kind of clock chip
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CN110261757A (en) * 2019-06-10 2019-09-20 南京宏泰半导体科技有限公司 A kind of number isolating chip test method and system
CN112098770A (en) * 2020-08-20 2020-12-18 深圳市宏旺微电子有限公司 Test method and device for simulating extreme environment aiming at dynamic coupling fault
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100244430B1 (en) * 1997-06-30 2000-02-01 김영환 Test of semiconductor chip
US20010022536A1 (en) * 2000-03-17 2001-09-20 Janne Kallio Adjustment of Oscillator
CN1862273A (en) * 2006-01-09 2006-11-15 北京大学深圳研究生院 System for testing clock signal dither and method thereof
CN101364978A (en) * 2007-08-10 2009-02-11 鸿富锦精密工业(深圳)有限公司 Instant time clock precise verification system and method
CN101908012A (en) * 2009-06-05 2010-12-08 鸿富锦精密工业(深圳)有限公司 Clock signal testing device and testing method thereof
CN102591197A (en) * 2012-02-20 2012-07-18 惠州市德赛西威汽车电子有限公司 Clock-temperature-error compensation method and system thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100244430B1 (en) * 1997-06-30 2000-02-01 김영환 Test of semiconductor chip
US20010022536A1 (en) * 2000-03-17 2001-09-20 Janne Kallio Adjustment of Oscillator
CN1862273A (en) * 2006-01-09 2006-11-15 北京大学深圳研究生院 System for testing clock signal dither and method thereof
CN101364978A (en) * 2007-08-10 2009-02-11 鸿富锦精密工业(深圳)有限公司 Instant time clock precise verification system and method
CN101908012A (en) * 2009-06-05 2010-12-08 鸿富锦精密工业(深圳)有限公司 Clock signal testing device and testing method thereof
CN102591197A (en) * 2012-02-20 2012-07-18 惠州市德赛西威汽车电子有限公司 Clock-temperature-error compensation method and system thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
李帆 等: "电能表和采集设备时钟芯片的检测", 《仪表技术》 *

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* Cited by examiner, † Cited by third party
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CN104833446B (en) * 2015-05-08 2017-07-04 福州大学 A kind of CMOS TEMPs chip test system
CN104833446A (en) * 2015-05-08 2015-08-12 福州大学 CMOS temperature sensing chip test system
CN105182067A (en) * 2015-09-30 2015-12-23 上海大学 SOC frequency testing method
CN105182067B (en) * 2015-09-30 2018-03-06 上海大学 SOC frequency test method
CN106445756A (en) * 2016-09-27 2017-02-22 乐视控股(北京)有限公司 Terminal testing method and device
CN108226756A (en) * 2018-01-29 2018-06-29 深圳市兴威帆电子技术有限公司 The test system and its test method of a kind of clock chip
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CN109613420B (en) * 2019-01-30 2021-04-06 上海华虹宏力半导体制造有限公司 Chip testing method
CN109613420A (en) * 2019-01-30 2019-04-12 上海华虹宏力半导体制造有限公司 The test method of chip
CN110261757A (en) * 2019-06-10 2019-09-20 南京宏泰半导体科技有限公司 A kind of number isolating chip test method and system
CN112098770A (en) * 2020-08-20 2020-12-18 深圳市宏旺微电子有限公司 Test method and device for simulating extreme environment aiming at dynamic coupling fault
CN112147488A (en) * 2020-09-25 2020-12-29 杰华特微电子(杭州)有限公司 Chip parameter testing and calibrating method
CN114706376A (en) * 2022-06-06 2022-07-05 南京宏泰半导体科技有限公司 Hardware control device and method based on software decoupling
CN114706376B (en) * 2022-06-06 2022-08-26 南京宏泰半导体科技有限公司 Hardware control device and method based on software decoupling
CN114924119A (en) * 2022-07-21 2022-08-19 深圳市英特瑞半导体科技有限公司 Clock chip and frequency measuring method

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