JP2014106591A - Power consumption estimation device and power consumption estimated method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power consumption estimation device which can improve accuracy of a power consumption estimate at an initial design stage, for example.SOLUTION: A block power consumption information 100, use case information 101, and block parallel operation information 102 are read, to create data base information 106. System configuration information is read to create block diagram information 107. Based on the data base information 106 and the system information 107, power consumption of each use case is determined, and maximum electric power consumption is determined.

Description

  The present invention relates to a power consumption estimation device and a power consumption estimation method for a semiconductor integrated circuit.

  In recent years, semiconductor integrated circuits have become larger in scale and have also been required to have a short TAT (Turn Around Time) in the design period, and importance is placed on estimating power consumption at the initial design stage of the semiconductor integrated circuit.

  In general, power consumption estimation in the design process of a semiconductor integrated circuit includes an initial estimation performed at the initial stage of setting such as a specification review stage, and a later stage estimation performed at a later stage of design such as RTL (Register Transfer Level) design. Can be divided. FIG. 13 shows an initial estimation method of power consumption in the design of a conventional semiconductor integrated circuit.

  In the initial estimation of power consumption shown in FIG. 13, the reuse module and IP (Intellectual Property) module use the power consumption information stored in the past design information 202. The new design module uses information that estimates the power consumption of the module from the process information 200 to be used, the estimated circuit scale information 201, and the like. Then, considering whether or not each module operates at the same time from the use case, the power consumption estimate 203 of the entire semiconductor integrated circuit is obtained by desktop calculation to obtain power consumption estimate information 204. This is applied to the use case where the power consumption is the largest, and the maximum power consumption value of the semiconductor integrated circuit is obtained.

  In this initial estimation, it is possible to accurately estimate the power consumption value of the newly designed module and the parallel operation between modules in the use case, and the use case that maximizes the power consumption from many use cases. It is important to be able to find. Since the use case where the power consumption is maximized is estimated by the designer as described above, it depends on the skill level of the designer. In addition, since the initial estimation of power consumption is used for cost estimation of the semiconductor integrated circuit, if the estimation accuracy here is low, the subsequent process will be greatly affected.

  Patent Document 1 describes automatic division of software and hardware using parameters such as processing amount and power consumption in order to improve design efficiency without relying on designers' skills when designing a semiconductor integrated circuit device. A design method for performing is described. That is, it describes that the software and hardware are divided by automatically estimating the power consumption regardless of the skill level of the designer.

  Next, FIG. 14 shows a late estimation method of power consumption in the design of the conventional semiconductor integrated circuit in the design of the conventional semiconductor integrated circuit. In the later estimation of power consumption shown in FIG. 14, first, logic simulation 302 is performed using circuit information 300 at RT (Register Transfer) level or gate level, and test pattern 301 close to actual operation, and changes in internal signals of the circuit are performed. Number-of-times information 304 is acquired. Next, using a power consumption library 303 in which internal signal change count information 304, circuit information 300, cell level power consumption information, and the like are stored, a commercially available or in-house power consumption estimation tool 305 is used. The power consumption estimation information 306 is obtained.

  In the late estimation, there is a problem of how to select the test pattern to be used for power consumption estimation, but since the actual circuit diagram and the information on the number of changes in the internal signal of the circuit can be used, a highly accurate estimation is required. Can do.

  The initial estimation of the power consumption of the semiconductor integrated circuit has a problem that it is difficult to make a highly accurate estimation even though the influence on the subsequent process is large. In particular, it is difficult for even a skilled designer to find a use case that maximizes power consumption.

  In Patent Document 1, although a division method is described in hardware and software that achieves optimum power consumption, no consideration is given to a use case indicating a transmission pattern of signals and data between blocks in actual operation. .

  In the later estimation of power consumption, simulation is performed using a test pattern of a use case that maximizes power consumption, and power consumption is estimated based on internal signal change information. Then, it is confirmed whether or not the test pattern is a test pattern of the intended use case, and whether the parallel operation of each module is as expected. However, the increase in the circuit scale and the complexity of the circuit are made, so that it is not easy to confirm them. That is, there is a problem that it becomes difficult to evaluate the validity of the test pattern.

  The present invention aims to solve such problems.

  That is, an object of the present invention is to provide a power consumption estimation apparatus that can improve the accuracy of power consumption estimation at the initial design stage, for example.

  In order to solve the problems described above, the invention described in claim 1 is a power consumption estimation device for estimating power consumption of a semiconductor integrated circuit, and module configuration information indicating a module configuration of the semiconductor integrated circuit is provided. Stored module configuration information storage means, parallel operation information storage means for storing parallel operation information for each use case of the module, and module power consumption information storage means for storing power consumption information of the module The module configuration information stored in the module configuration information storage means, the parallel operation information stored in the parallel operation information storage means, and the power consumption stored in the power consumption information storage means Power consumption estimation means for estimating the power consumption of the semiconductor integrated circuit based on the information. A power estimation device to.

  According to the first aspect of the present invention, a use case in which the power consumption of the circuit scale is maximized by reading information necessary for power consumption estimation and exhaustively estimating power consumption in all use cases. This makes it possible to obtain the power consumption with high accuracy.

It is a block diagram of the power consumption estimation apparatus concerning one Embodiment of this invention. It is a block diagram of the computer used as the power consumption estimation apparatus shown by FIG. 3 is a flowchart illustrating an operation of the power consumption estimation apparatus illustrated in FIG. 1. It is the block diagram which showed the system configuration example used as a semiconductor integrated circuit. It is an example of the power consumption information of the block diagram shown by FIG. It is another example of the power consumption information of the block diagram shown by FIG. It is an example of the use case information shown by FIG. It is explanatory drawing of the data path | route of the use case 1 shown by FIG. It is explanatory drawing of the data path | route of the use case 2 shown by FIG. It is an example of the parallel operation information of the block shown by FIG. It is an example of the logic simulation result information shown by FIG. It is another example of the logic simulation result information shown by FIG. It is explanatory drawing which showed the initial estimation method performed in the setting initial stage concerning a prior art. It is explanatory drawing which showed the latter term estimation method performed in the setting latter term concerning a prior art.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a configuration diagram of a power consumption estimation apparatus according to an embodiment of the present invention. FIG. 2 is a configuration diagram of a computer serving as the power consumption estimation apparatus shown in FIG. FIG. 3 is a flowchart showing the operation of the power consumption estimation apparatus shown in FIG. FIG. 4 is a block diagram showing a system configuration example that is a semiconductor integrated circuit. FIG. 5 is an example of power consumption information of the block diagram shown in FIG. FIG. 6 is another example of the power consumption information of the block diagram shown in FIG. FIG. 7 is an example of the use case information shown in FIG. FIG. 8 is an explanatory diagram of the data path of use case 1 shown in FIG. FIG. 9 is an explanatory diagram of the data path of use case 1 shown in FIG. FIG. 10 is an example of parallel operation information of the block shown in FIG. FIG. 11 is an example of the logic simulation result information shown in FIG. FIG. 12 is another example of the logic simulation result information shown in FIG.

  FIG. 1 shows a configuration diagram of a power consumption estimation apparatus 1 according to an embodiment of the present invention. The power consumption estimation apparatus 1 receives and stores block power consumption information 100, use case information 101, block parallel operation information 102, and system configuration information 103. Further, the power consumption estimation apparatus 1 includes a database creation unit 104, a block diagram creation unit 105, and a power consumption estimation unit 108, and includes database information 106, block diagram information 107, power consumption estimation information 109, Is generated. Further, the power consumption estimation apparatus 1 is inputted and stored with circuit information 110 and input pattern information 111, and includes a logic simulation unit 112 and a power consumption estimation check unit 114, and generates simulation result information 113. Is done.

  The block power consumption information 100 stores power consumption information for each block of a plurality of blocks (modules) constituting the semiconductor integrated circuit.

  The use case information 101 stores information indicating a transmission pattern between signals and data between blocks in the actual operation of the semiconductor integrated circuit.

  The block parallel operation information 102 stores parallel operation information of a plurality of blocks constituting the semiconductor integrated circuit.

  The system configuration information 103 stores module configuration information of a system that is a semiconductor integrated circuit described in a programming language, a hardware description language, or the like.

  The database creation unit 104 creates a database from the block power consumption information 100, the use case information 101, and the block parallel operation information 102, and outputs the database as database information 106. Further, the database creation unit 104 can change or delete information registered in the database information 106.

  The block diagram creating means 105 creates a block diagram of the system (semiconductor integrated circuit) from the system configuration information 103 and outputs it as block diagram information 107.

  The power consumption estimation means 108 calculates the power consumption for each use case based on the database information 106 and the block diagram information 107 and outputs it as the power consumption estimation information 109.

  The circuit information 110 is RT level or gate level logic circuit information described in a hardware description language such as Verilog HDL or SystemC, for example.

  The input pattern information 111 is an input pattern (input signal pattern information) whose validity is evaluated by the power consumption estimation check unit. The input pattern is a pattern indicating the actual operation of the target semiconductor integrated circuit.

  The logic simulation unit 112 reads the circuit information 110 and the input pattern information 111, performs a logic simulation by a known logic simulator, and outputs simulation result information 113. The input pattern of the input pattern information 111 is given to the circuit information 110.

  The power consumption estimation check means 114 is a use case in which the result indicated by the simulation result information 113 from the simulation result information 113, the database information 106, the power consumption estimation information 109, and the block diagram information 107 is the maximum power consumption calculated in advance. To check.

  FIG. 2 is a configuration diagram illustrating a configuration example of a computer that is the power consumption estimation apparatus 1 illustrated in FIG. 1. The computer includes a central processing unit (CPU) 10, an input device 11, a display device 12, a memory 13, and a storage device 14.

  The CPU 10 governs overall control of the computer serving as the power consumption estimation device 1, and reads and executes programs, data, and the like stored in the memory 13 and the storage device 14. The CPU 10 functions as the database creation unit 104, the block diagram creation unit 105, the power consumption estimation unit 108, the logic simulation unit 112, and the power consumption estimation check unit 114 in FIG.

  The input device 11 is composed of, for example, a keyboard and a mouse. The input device 11 is used for operations on a computer that becomes the power consumption estimation device 1.

  The display device 12 is configured by a liquid crystal display, for example. The display device 12 displays a result processed by the CPU 10, displays an input from the input device 11, displays data stored in the storage device 14 and the like.

  The memory 13 is composed of, for example, a RAM (Random Access Memory), and temporarily stores programs executed by the CPU 10, data to be processed, and the like.

  The storage device 14 is composed of, for example, a hard disk device, and stores programs executed by the CPU 10, data to be processed, processing results, and the like. The storage device 14 includes power consumption information 100, use case information 101, parallel operation information 102, system configuration information 103, database information 106, block diagram information 107, power consumption estimation information 109, circuit information of the block in FIG. 110, input pattern information 111, and simulation result information 113 are stored.

  The block power consumption information 100, the use case information 101, the block parallel operation information 102, the system configuration information 103, the circuit information 110, and the input pattern information 111 are directly input from the input device 11 by the user and stored in the storage device 14. May be. Further, it may be stored in a portable storage medium such as a memory card or an optical disk and transferred to the storage device 14. Alternatively, the computer may be provided with a network interface and stored in the storage device 14 via the network.

  Needless to say, the computer that becomes the power consumption estimation apparatus 1 is not limited to FIG. For example, without storing the block power consumption information 100, use case information 101, block parallel operation information 102, system configuration information 103, circuit information 110, and input pattern information 111 in the storage device 14, It may be directly input and temporarily stored in the memory 13 for use. Alternatively, it may be input via a network and temporarily stored in the memory 13. Alternatively, the database information 106, the block diagram information 107, the power consumption estimation information 109, and the simulation result information 113 may be stored in an external storage device so that the CPU 10 can read and write via the network. Furthermore, the power consumption estimation apparatus 1 may be configured by a plurality of computers.

  Next, the operation of the power consumption estimation apparatus 1 having the above-described configuration will be described with reference to the flowchart of FIG. The flowchart shown in FIG. 3 is executed by the CPU 10 in FIG.

  First, when performing power consumption estimation by selecting whether to perform power consumption estimation or input pattern validity checking in step S1, proceed to step S2, and to perform input pattern validity checking, proceed to step S7. move on. In this step, the user selects one using the input device 11, for example, and makes a determination based on the selection information.

  Here, the power consumption estimation indicates power consumption estimation (initial estimation) at the initial stage of design. The validity check of the input pattern means checking the validity of whether the input pattern that is the operation of the maximum power consumption in the late stage of design corresponds to the use case of the maximum power consumption estimated in the early stage of design.

  Next, in step S2, a block diagram is created and the process proceeds to step S3. This block diagram shows the block diagram information 107 of FIG. 1, and is created by the block diagram creation means 105 reading the system configuration information 103 and outputting the block diagram information 107 created. The block diagram information 107 is module configuration information indicating the module configuration of the semiconductor integrated circuit, and the storage device 14 in which the block diagram information 107 is stored functions as module configuration information storage means.

  Here, an example of the block diagram information 107 will be described with reference to FIG. The system (semiconductor integrated circuit) shown in FIG. 4 includes four blocks A1, A2, A3, and A4. The block here may indicate a single circuit module, or a functional unit including a plurality of circuit modules may be referred to as a block. Here, the system is assumed to be hardware, but may be software. That is, the system configuration information 103 is an operation description of software described in a programming language or a circuit described in a hardware description language. Then, the block diagram as shown in FIG. 4 is created by the block diagram creation means 105 configured by a known circuit diagram creation tool or block diagram creation tool. In the case of software, functions and the like are extracted as blocks.

  In the block diagram shown in FIG. 4, each block has an input / output port, and blocks A1, A3, and A4 have I1 as an input port and O1 as an output port. The block may have a plurality of input / output ports, and the block A2 has one input port I1 and two output ports O1 and O2.

  Returning to the description of the flowchart of FIG. 3, in step S3, a database is created, and the process proceeds to step S4. This database shows the database information 106 of FIG. 1, and the database creation means 104 reads the block power consumption information 100, the use case information 101, and the block parallel operation information 102, and creates a database in which each information is registered. To do. That is, the database information 106 stores parallel operation information for each use case of the module, power consumption information of the module, and use case information indicating the use case in the module configuration. Accordingly, the storage device 14 in which the database information 106 is stored functions as parallel operation information storage means, power consumption information storage means, and use case information storage means.

  Here, examples of the block power consumption information 100, the use case information 101, and the block parallel operation information 102 in the block diagram shown in FIG. 4 will be described with reference to FIGS.

  First, an example of the block power consumption information 100 in the block diagram shown in FIG. 4 is shown in FIGS. FIG. 5 is an example in which power consumption is described for each block. In FIG. 5, 10 mW is consumed when the block A1 operates, 20 mW when the block A2 operates, 25 mW when the block A3 operates, and 50 mW when the block A4 operates.

  FIG. 6 is an example in which power consumption is described for each use case. In FIG. 6, in the case of use case 1, the power consumption of block A2 is 20 mW, but in the case of use case 2, the power consumption of block A2 is 25 mW. In FIG. 6, only the power consumption of the changing block is described, but it goes without saying that the power consumption of all the blocks may be described for each use case.

  Next, examples of use case information 101 in the block diagram shown in FIG. 4 are shown in FIGS. FIG. 7 shows an example of use case description. In FIG. 7, two use cases are described. Use case 1 indicates that data (or a signal) flows from block A1 through block A2 to block A3 as indicated by the arrow in FIG. Use case 2 indicates that data flows from block A1 through block A2 to block A4 as indicated by the arrow in FIG.

  The use case shows an actual operation (actual usage) as described above. That is, in the semiconductor integrated circuit having the block configuration (system configuration) shown in FIG. 4, use case 1 and use case 2 are actually used data flows, and all of blocks A1, A2, A3, and A4 are used. This indicates that there is no case where the block operates. This can prevent excessively large power consumption estimation.

  Next, FIG. 10 shows an example of the block parallel operation information 102 in the block diagram shown in FIG. FIG. 10 is a description example of parallel operation of blocks. In FIG. 10, blocks that operate simultaneously for each use case are described by separating them with a semicolon. When the use case 1 is in operation, the blocks A1, A2 and A3 are shown to operate simultaneously. In use case 2, blocks A1 and A2 operate simultaneously, but block A4 does not operate simultaneously with blocks A1 and A2. Note that the block parallel operation information 102 is not limited to being separated by a semicolon, but may be another description method as long as the blocks operating simultaneously for each use case can be distinguished.

  Returning to the description of the flowchart of FIG. 3, in step S4, power consumption is estimated, and the process proceeds to step S5. The power consumption estimation unit 108 performs the power consumption estimation unit 108 based on the block diagram created in step S2 and the database created in step S3. That is, the power consumption estimation unit 108 estimates the power consumption of the semiconductor integrated circuit based on the module configuration information, the parallel operation information, and the power consumption information. Further, this step functions as a power consumption estimation process.

  A specific example in which the power consumption is estimated using each piece of information shown in FIGS. First, in use case 1, blocks A1, A2, and A3 operate simultaneously. The maximum power consumption of use case 1 is (A1 power consumption + A2 power consumption + A3 power consumption) = (10 + 20 + 25) = 55 mW.

  Use case 2 can be divided into a pattern in which blocks A1 and A2 operate simultaneously and a pattern in which block A4 operates independently. The power consumption of the pattern in which A1 and A2 operate simultaneously is (A1 power consumption + A2 power consumption) = (10 + 25) = 35 mW. On the other hand, the power consumption of the pattern in which the block A4 operates independently is (power consumption of A4) = (50) = 50 mW. Therefore, in use case 2, the maximum power consumption is 50 mW.

  These results become the power consumption estimation information 109. In the examples of FIGS. 4 to 10, use case 1 is a use case with the maximum power consumption, and the maximum power consumption can be obtained as 55 mW. Note that the calculation formula for obtaining the power consumption is merely a simple example for explanation, and the calculation formula may be changed in order to estimate the power consumption more accurately. In this step, the maximum power consumption and the power consumption for each use case may be displayed on the display device 12.

  Next, in step S5, it is determined whether or not the database information 106 and the block diagram information 107 are corrected. As a result of the determination, if the block diagram information 107, that is, the system configuration information 103 is corrected, the process returns to step S2, and if the information registered in the database information 106 such as the block power consumption information 100 is corrected, the process returns to step S3. If there is no correction (in the case of N), the process proceeds to step S6.

  In the present embodiment, various types of input information are centrally managed as database information 106, and information in the database information 106 can be changed. For example, it is assumed that a part of the function of the block A3 is reduced due to the change of the design specification. This function reduction also reduces the power consumption of the block A3. In this case, the database information 106 can be changed by rereading the power consumption information 100 of the changed block or by reading the power consumption information of only the block A3.

  For example, if the power consumption of the block A3 is changed to 15 mW in the above-described example, the maximum power consumption of use case 1 is (10 + 20 + 15) = 45 mW. The maximum power consumption of use case 2 is 50 mW because there is no change. As a result, use case 2 has the maximum power consumption, and the maximum power consumption can be determined to be 50 mW.

  In addition, although the example in the case where the block power consumption information 100 has been changed has been described above, the same applies to the case where the block parallel operation information 102 and the use case information 101 are added or deleted. That is, the database creation unit 104 functions as an information changing unit that changes or deletes the parallel operation information, the power consumption information, and the use case information. In this case, step S3 functions as an information changing step.

  As described above, when the power consumption of the block is changed, the use case that maximizes the power consumption may change. In the initial stage of design, such a specification change is frequently performed, and the block power consumption information 100 is also frequently changed. Further, as the design progresses, it becomes possible to set the power consumption information of the block with higher accuracy, so that such a database is effective.

  Next, in step S6, it is determined whether or not to check the validity of the input pattern. If the check is performed (Y), the process proceeds to step S7, and if the check is not performed (N), the process ends. . For example, in the case of initial estimation, it may be selected that the check is not performed in this step.

Next, in step S7, circuit information 110 and input pattern information 111 are read, a logic simulation is performed by the logic simulation means 112, and the process proceeds to step S8. The result of the logic simulation is output as simulation result information 113.
That is, the storage device 14 storing the circuit information 110 and the input pattern information 111 functions as a circuit information storage unit and an input signal pattern information storage unit, and the logic simulation unit 112 functions as a simulation unit. Further, this step functions as a simulation process.

  FIG. 11 shows an example of the simulation result information 113. FIG. 11 shows the signal state of the port of the block for each time in the logic simulation. From this result, the signal (1) that reached the input port (A1.I1) of the block A1 at time 100 ns propagates to the output port (A1.O1) of the block A1 in 200 ns of the next cycle. Further, the signal propagated to the output port (A1.O1) of the block A1 is propagated to the input port (A2.I1) of the block A2 at the same time (200 ns). Similarly, at time 300 ns, the output signal of the output port 1 (A2.O1) of the block A2 is propagated to the input port (A3.I1) of the block A3.

  FIG. 12 shows another example of the simulation result information 113. FIG. 12 represents the number of changed signals in the block within a particular clock cycle. At time 0-100 ns, 20 internal signals change in block A1 and block A2. There are no changed signals in block A3 and block A4. That is, the block A1 and the block A2 operate simultaneously. Similarly, it is shown that the block A1 and the block A2 operate simultaneously at times 100-200ns, 200-300ns, and 500-600ns. In addition, at time 300 to 400 ns, ten signals inside the block A4 are changed, but no change of the internal signal is observed at the blocks A1, A2 and A3. That is, only the block A4 operates. The same applies at time 400-500ns.

  Next, in step S8, the validity of the input pattern indicated by the input pattern information 111 is checked and the process ends. The validity of the input pattern is checked (evaluated) by the power consumption estimation check unit 114 based on the simulation result information 113 output in step S7, the database information 106, the power consumption estimation information 109, and the block diagram information 107. That is, the power consumption estimation check unit 114 functions as a validity evaluation unit. Moreover, this step functions as a validity evaluation process.

  For example, in the case of the logic simulation result shown in FIG. 11, when the data flow is traced, it can be seen that the data is propagated from the block A1 to the block A3 via the block A2. It can be seen from the database information 106 (use case information 101) that this input pattern is use case 1. Therefore, the validity of the input pattern can be evaluated by determining whether the power consumption of use case 1 is the maximum display power based on the power consumption estimation information 109. That is, if the input pattern is a use case with the maximum power consumption, the input pattern is evaluated as valid. If the input pattern is not the use case with the maximum power consumption, the input pattern is evaluated as invalid. This evaluation result is displayed on the display device 12, for example.

  In the case of the logic simulation result shown in FIG. 12, the block A1 and the block A2 operate simultaneously. Further, it can be read that the block A4 operates alone. It can be seen from the database information 106 (block parallel operation information 102) that this input pattern is use case 2. Thereafter, as in the case of FIG. 11, if the input pattern is a use case with the maximum power consumption, the input pattern is evaluated as valid. If the input pattern is not the use case with the maximum power consumption, the input Assess the pattern is not valid.

  According to this embodiment, the block power consumption information 100, the use case information 101, and the block parallel operation information 102 are read to create the database information 106, and the system configuration information is read to create the block diagram information 107. Then, the power consumption in each use case is obtained based on the database information 106 and the block diagram information 107 to obtain the maximum power consumption. In this way, in order to comprehensively estimate the power consumption in all use cases, the power consumption estimation at the initial stage of the design eliminates the oversight of information necessary for use cases and power consumption estimation, and high-precision consumption. Power estimation is possible.

  In addition, the circuit information 110 and the input pattern information 111 are read, a logic simulation is performed, and the validity of the input pattern is evaluated based on the result, the database information 106, the power consumption estimation information 109, and the block diagram information 107. Yes. By doing so, it is possible to confirm whether the input pattern used for the power consumption estimation is the input pattern of the use case with the largest power consumption when estimating the power consumption in the latter half of the design.

  Further, the database creation means 104 reads the block power consumption information 100, the use case information 101, and the block parallel operation information 102 to create the database information 106. By doing so, even when a design change occurs, it is possible to estimate the power consumption by correcting only the changed information.

  In addition, it is possible to check whether the parallel operation of the blocks is as expected by determining the use case of the input pattern by evaluating the validity.

  In the above-described embodiment, the database information 106 is created, but each information may be read each time the power consumption is estimated without creating the database information 106. In addition, each piece of information may be stored in a separate storage device or storage medium.

  Further, when the system configuration information 103 can be block diagram information as shown in FIG. 4 showing the block configuration and the connection state of the input port and output port, the block diagram creation means 105 Is not necessary.

  The present invention is not limited to the above embodiment. That is, those skilled in the art can implement various modifications in accordance with conventionally known knowledge without departing from the scope of the present invention. Of course, such modifications are included in the scope of the present invention as long as the configuration of the power consumption estimation apparatus of the present invention is provided.

1 Power consumption estimation device 100 Block power consumption information (power consumption information)
101 Use case information 102 Block parallel operation information (parallel operation information)
104 Database creation means (information change means)
106 Database information (parallel operation information storage means, power consumption information storage means, use case information storage means)
107 Block diagram information (module configuration information storage means)
108 power consumption estimation means 109 power consumption estimation information 110 circuit information (circuit information storage means)
111 Input pattern information (input signal pattern information storage means)
112 Logic simulation means (simulation means)
113 Simulation result information 114 Power consumption estimation check means (validity evaluation means)
S3 Database creation (information change process)
S4 Power consumption estimation (power consumption estimation process)
S7 Logic simulation (simulation process)
S8 Validity evaluation of input pattern (validity evaluation process)

JP 2001-142927 A

Claims (6)

A power consumption estimation device for estimating power consumption of a semiconductor integrated circuit,
Module configuration information storage means for storing module configuration information indicating the module configuration of the semiconductor integrated circuit;
Parallel operation information storage means storing parallel operation information for each use case of the module;
Module power consumption information storage means for storing the power consumption information of the module;
The module configuration information stored in the module configuration information storage means, the parallel operation information stored in the parallel operation information storage means, and the power consumption information stored in the power consumption information storage means , Power consumption estimation means for estimating the power consumption of the semiconductor integrated circuit based on
A power consumption estimation apparatus comprising: Use case information storage means for storing use case information indicating use cases in the module configuration;
Circuit information storage means for storing circuit information of the semiconductor integrated circuit;
Input signal pattern information storage means in which an input signal pattern to be given to the circuit information is stored;
Simulation means for performing simulation based on the circuit information and the input signal pattern information;
The simulation result output from the simulation unit, the power consumption estimation result output from the power consumption estimation unit, the use case information stored in the use case information storage unit, and the parallel operation information storage unit Validity evaluation means for evaluating the validity of the input signal pattern information based on the parallel operation information being
The power consumption estimation apparatus according to claim 1, wherein:   The parallel operation information stored in the parallel operation information storage means, the power consumption information stored in the module power consumption information storage means, and the use case information stored in the use case information storage means The apparatus for estimating power consumption according to claim 2, further comprising information changing means for changing or deleting. A power consumption estimation method for a power consumption estimation device for estimating power consumption of a semiconductor integrated circuit, comprising:
Based on the module configuration information indicating the module configuration of the semiconductor integrated circuit, the parallel operation information indicating parallel operation information for each use case of the module, and the power consumption information of the module, the power consumption of the semiconductor integrated circuit is calculated. A power consumption estimation method comprising a power consumption estimation step of estimating. A simulation step of performing simulation based on circuit information and input signal pattern information of the semiconductor integrated circuit;
Based on the simulation result output from the simulation step, the power consumption estimation result output from the power consumption estimation step, the use case information indicating the use case in the module configuration, and the parallel operation information A validity evaluation step of evaluating the validity of the input signal pattern information;
The power consumption estimation method according to claim 4, further comprising:   The power consumption estimation method according to claim 5, further comprising an information changing step of changing or deleting the parallel operation information, the power consumption information, and the use case information.

Images