CN114627958A

CN114627958A - Storage device testing method and device, electronic device and readable medium

Info

Publication number: CN114627958A
Application number: CN202210167992.1A
Authority: CN
Inventors: 汝峰; 陈德强; 刘健全
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-02-23
Filing date: 2022-02-23
Publication date: 2022-06-14

Abstract

The embodiment of the invention discloses a method and a device for testing storage equipment, electronic equipment and a storage medium. The test method comprises the following steps: dividing a group of storage devices to be tested into a first set and a second set; the first set comprises non-abnormal first storage equipment to be tested in the group of storage equipment to be tested; the second set comprises abnormal second storage equipment to be tested in the group of storage equipment to be tested; configuring a first volume address for the first storage device to be tested in the first set, and configuring a second volume address for the second storage device to be tested in the second set; sending a selection command to each storage device to be tested in the group of storage devices to be tested; the selection command is used for selecting only the first set corresponding to the first volume address; and enabling the first storage device to be tested in the first set to execute a preset testing step.

Description

Storage device testing method and device, electronic device and readable medium

Technical Field

The present invention relates to the field of memory technologies, and in particular, to a method and an apparatus for testing a storage device, an electronic device, and a readable medium.

Background

In the testing of FLASH memory (FLASH), there is often a Burn-In Test (BIT) to find some early failing chips. In the Burn-In test, a Burn-In Board (Burn-In Board) is used. The number of Test channels of the Test host on the burn-in board is relatively small, and some DUTs of a plurality of memory Devices Under Test (DUTs) on the burn-in board need to share the Test channels. In this case, when any one of the DUTs sharing the test channel is abnormal, the other DUTs sharing the test channel need to wait for the abnormal DUT to complete the same test item or operation as the other DUTs before performing the next test item or operation, so that the whole test time is long, and the test efficiency is seriously affected.

Disclosure of Invention

In view of this, embodiments of the present invention provide a method and an apparatus for testing a storage device, an electronic device, and a storage medium, so as to optimize the testing time for the FLASH aging test and achieve cost saving.

In a first aspect, an embodiment of the present invention provides a method for testing a storage device, where the method includes:

dividing a group of storage devices to be tested into a first set and a second set; the first set comprises non-abnormal first storage equipment to be tested in the group of storage equipment to be tested; the second set comprises abnormal second storage equipment to be tested in the group of storage equipment to be tested; some memory devices to be tested in the group of memory devices to be tested share the same test signal;

configuring a first volume address for the first storage device to be tested in the first set, and configuring a second volume address for the second storage device to be tested in the second set;

sending a selection command to each storage device to be tested in the group of storage devices to be tested, wherein the selection command is used for selecting only the first set corresponding to the first volume address;

and enabling the first storage device to be tested in the first set to execute a preset testing step.

In a second aspect, an embodiment of the present invention further provides an apparatus for testing a storage device, where the apparatus includes: the device comprises a distinguishing module, a configuration module, a sending module and an execution module, wherein the distinguishing module is used for distinguishing the data;

the distinguishing module is used for distinguishing a group of storage devices to be tested into a first set and a second set; the first set comprises non-abnormal first storage equipment to be tested in the group of storage equipment to be tested; the second set comprises abnormal second storage equipment to be tested in the group of storage equipment to be tested; some memory devices to be tested in the group of memory devices to be tested share the same test signal;

the configuration module is configured to configure a first volume address for the first storage device to be tested in the first set, and configure a second volume address for the second storage device to be tested in the second set;

the sending module is configured to send a selection command to each storage device to be tested in the group of storage devices to be tested, where the selection command is used to select only the first set corresponding to the first volume address;

the execution module is configured to enable the first storage device under test in the first set to execute a preset test step.

In a third aspect, an embodiment of the present invention further provides an electronic device, where the electronic device includes a memory and a processor, where the memory stores instructions;

the processor is used for executing the instructions in the memory, and when the instructions are executed by the processor, the method is realized.

In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program implements the method described in any one of the above

The embodiment of the invention provides a method and a device for testing storage equipment, electronic equipment and a storage medium. Wherein the method comprises the following steps: dividing a group of storage devices to be tested into a first set and a second set; the first set comprises non-abnormal first storage equipment to be tested in the group of storage equipment to be tested; the second set comprises abnormal second storage equipment to be tested in the group of storage equipment to be tested; some memory devices to be tested in the group of memory devices to be tested share the same test signal; configuring a first volume address for the first storage device to be tested in the first set, and configuring a second volume address for the second storage device to be tested in the second set; sending a selection command to each storage device to be tested in the group of storage devices to be tested, wherein the selection command is used for selecting only the first set corresponding to the first volume address; and enabling the first storage device to be tested in the first set to execute a preset testing step. According to the testing method and device provided by the embodiment of the invention, the storage devices to be tested are divided into two different sets (a first set and a second set) according to the testing result of the previous round of testing, different volume addresses (a first volume address and a second volume address) are configured for the storage devices to be tested in each set, then the first set corresponding to the first volume address is selected based on the selection command, the first storage devices to be tested in the first set are enabled to execute the preset testing items of the round, the second set corresponding to the second volume address is not selected, and testing is not carried out without selection, so that the second storage devices to be tested with the abnormality in the previous round are not tested again, normal testing of other storage devices without the abnormality is not influenced, testing time is saved, and the purpose of saving cost is achieved.

Drawings

In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in this document.

FIG. 1 is a schematic diagram illustrating a related art burn-in board;

FIG. 2 is a schematic diagram of a burn-in test mass production system according to the related art;

FIG. 3 shows two polling methods in the related art;

fig. 4 is a first flowchart illustrating a method for testing a storage device according to an embodiment of the present invention;

fig. 5 is a second flowchart illustrating a method for testing a storage device according to an embodiment of the present invention;

FIGS. 6A and 6B are schematic diagrams illustrating exemplary structures of a mass storage device according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating the connection relationship between ENi pins and ENo pins on a single DUT (or referred to as a single NAND Flash) on a BIB board according to an embodiment of the present invention;

FIG. 8 is a schematic view showing a typical test flow (flow) of a mass production system based on the conventional burn-in test in the related art;

FIG. 9 is a schematic diagram of a test flow of a method for testing a memory device according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of the polling mode in FIG. 3 using the duration of the ready/busy state as the polling time, after the DUT2 has a test timeout, the Cycle being tested by the test method provided by the embodiment of the invention;

FIG. 11 is a schematic structural diagram of a testing apparatus for a memory device according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

Various embodiments of the present invention are described in more detail below with reference to the accompanying drawings. Other embodiments that are variations of any of the disclosed embodiments may be formed by differently configuring or arranging the elements and features of the present invention. Accordingly, the present invention is not limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. It should be noted that references to "an embodiment," "another embodiment," and the like do not necessarily refer to only one embodiment, and different references to any such phrases are not necessarily referring to the same embodiment. It will be understood that, although the terms first, second, third, etc. may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar designation. Thus, a first element in one embodiment may also be referred to as a second or third element in another embodiment without departing from the spirit and scope of the present invention.

The drawings are not necessarily to scale and, in some instances, may be exaggerated in scale to clearly illustrate features of embodiments. When an element is referred to as being connected or coupled to another element, it will be understood that the former may be directly connected or coupled to the latter, or may be electrically connected or coupled to the latter via one or more intervening elements therebetween. In addition, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The articles "a" and/or "an" as used herein and in the appended claims should be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. It will be further understood that the terms "comprises," "comprising," "includes" and "including," when used in this specification, specify the presence of stated elements and do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Unless defined otherwise, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs in view of the present invention. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the present invention and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, and the present invention may be practiced without some or all of these specific details. In other instances, well known process structures and/or processes have not been described in detail in order to not unnecessarily obscure the present invention. It will also be understood that, in some instances, features or elements described in connection with one embodiment may be used alone or in combination with other features or elements of another embodiment, unless specifically stated otherwise, as would be apparent to one skilled in the relevant art. Hereinafter, various embodiments of the present invention are described in detail with reference to the accompanying drawings. The following description focuses on details to facilitate an understanding of embodiments of the invention. Well-known technical details may be omitted so as not to obscure the features and aspects of the present invention.

Based on the description of the background art, in testing FLASH, there is often a burn-in test, wherein the burn-in test may refer to a process of repeatedly performing data ERASE (E, ERASE), data READ (R, READ) and data write (or PROGRAM P, PROGRAM) on a storage device (or a storage device, or a storage chip, i.e. the aforementioned DUT) (each ERASE, READ and write test process is referred to as a Cycle) so as to observe the performance of the storage device changing with the passage of time. The DUT may be a Flash chip including an Open NAND Flash Interface (ONFI) such as NAND.

The test hosts currently used for burn-in test have fewer test channels, and multiple DUTs on the burn-in board need to share these test channels, ultimately appearing as shared test signals. For example, in the mass burn-in system shown in fig. 1 and2, the burn-in board can simultaneously test 16 rows by 16 columns of DUTs, some of which share the same test signal. The burn-in test system includes a master Controller (Site Controller), which controls the whole burn-in test system, i.e., manages the test of the 256 DUTs.

In such a test environment, in the erasing, reading, and writing processes of the DUT, a polling (polling) method is generally adopted to determine whether the erasing, reading, and writing operations are completed, so under such a condition, on one burn-in board, any one of the memory devices to be tested (i.e., DUTs) sharing the same test signal has a test timeout, and the other memory devices to be tested need to wait for the completion of the overtime DUT to execute the next operation, which results in a longer test time and seriously affects the test efficiency. Among them, the concept of polling is: in the embodiment of the present invention, the polling refers to a process of repeatedly performing data erasing (E, ERASE), data reading (R, READ), and data writing (or programming P, PROGRAM) (each test process of erasing, reading, and writing is referred to as a Cycle), that is, sequentially performing each Cycle and E, P, R operations in each Cycle.

Two polling manners shown in fig. 3 are described in detail below, wherein the upper polling manner in fig. 3 is a polling manner according to a fixed polling time; the lower polling scheme in fig. 3 is a polling scheme in which the duration of the Ready/Busy (Ready/Busy) state is the polling time. In fig. 3, reference numeral (1) denotes: the time required for addressing, accepting commands (command or CMD) to input data into the buffer before writing data into the memory cell; reference numeral (2) denotes: the fixed waiting time, namely the fixed polling time is waited from the writing command, then after the fixed polling time is reached, the writing is judged to be finished, and then the next operation is executed; reference numeral (3) denotes: the time required to wait for data to be written in a polled manner with a polling time of the duration of the Ready/Busy (Ready/Busy) state; the reference numeral (4) denotes: a polling scheme that employs the duration of the Ready/Busy (Ready/Busy) state reduces latency over a fixed latency polling scheme.

It should be noted that, because the time required for erasing and the time required for programming (writing) of different tested storage devices are very different, the fixed polling time is set to the maximum value in the tested DUT, and the typical value is generally only half of the maximum value, i.e., the polling method using the duration of the Ready/Busy (Ready/Busy) state requires less time than the polling method using the fixed polling time.

No matter which polling method in fig. 3 is adopted, on one burn-in board, any one of the memory devices to be tested sharing the same test signal is overtime, and other memory devices to be tested need to wait for the overtime DUT to complete before executing the next operation, so the test time is longer, and the test efficiency is seriously affected, for example, when the DUT2 in fig. 3 is overtime, other memory devices to be tested need to wait for the overtime DUT to complete before executing the next operation, so the test time is longer, and the test efficiency is seriously affected.

Moreover, in the foregoing system for mass production of talk-spurt tests, because there is only one controller, on a BIB, as long as there is a test timeout of one DUT, all other DUTs on the whole BIB need to wait for the end of the test timeout of the DUT with the test timeout to continue the next operation (which may be any of ERASE, READ, and PROGRAM), which results in very long whole test time. Although the test signal of the DUT with overtime test can be cut off by using the resources inside the tester system in the software manner at present, the test time is increased, because the test signal may be shared by a plurality of DUTs, the test signal of the DUT with overtime test is cut off without affecting the normal test of other DUTs, at this time, the test signal which can be originally in parallel needs to be sent in series, so as to achieve the purpose of software isolation between the test signals, so that the test time is greatly increased, and the test cost is greatly increased due to the long test time.

Based on the foregoing description, a problem that exists at present is that, when a FLASH memory is subjected to an aging test, E/P/rs of a plurality of cycles are tested, since a plurality of DUTs share a same test signal, in a certain Cycle, if a test failure (Fail) occurs due to test timeout in a certain DUT, in the next Cycle, the test signal is further sent to the DUT that fails to be tested, and the DUT that fails to be tested may continuously affect the test time of other DUTs, that is, when an aging test is performed on FLASH, the DUT Fail often occurs in the test process of the E/P/R.

In view of the above problems, the basic idea of the embodiment of the present invention is to eliminate the DUT of Fail in the subsequent test Cycle, and only test the normal DUT, and the specific test flow may be as shown in fig. 4. It should be understood that during the testing of the E/P/R, a connection test is required to ensure that the hardware connection is working properly.

How to cull the DUTs of Fail. In some embodiments, the input and output control signals of the DUT that has a test timeout may be physically masked by a special BIB design, such as physically masking the Chip Enable (CE) signals, Ready/Busy (R/B, Ready/Busy), etc. of the DUT that has a test timeout. This approach requires hardware modifications and may increase costs.

The embodiment of the invention also provides a test method based on the ONFI standard, which can remove the DUTs with Fail without modifying hardware and only reserve normal DUTs for subsequent aging tests.

Specifically, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

Fig. 5 is a schematic flowchart of a method for testing a storage device according to an embodiment of the present invention. As shown in fig. 5, the testing method may specifically include:

s501: dividing a group of storage devices to be tested into a first set and a second set; the first set comprises non-abnormal first storage equipment to be tested in the group of storage equipment to be tested; the second set comprises abnormal second storage equipment to be tested in the group of storage equipment to be tested; some memory devices to be tested in the group of memory devices to be tested share the same test signal;

s502: configuring a first volume address for the first storage device to be tested in the first set, and configuring a second volume address for the second storage device to be tested in the second set;

s503: sending a selection command to each storage device to be tested in the group of storage devices to be tested; the selection command is used for selecting only the first set corresponding to the first volume address;

s504: and enabling the first storage device to be tested in the first set to execute a preset testing step.

The basic concept of the test method provided by the embodiment of the invention can be summarized as follows: when a group of storage devices to be tested is subjected to aging test, the group of storage devices to be tested is distinguished into a first set containing a first storage device to be tested which is not abnormal and a second set containing a second storage device to be tested which is abnormal, then configuring a first Volume Address (Volume Address) for a first storage device to be tested in the first set and a second Volume Address for a second storage device to be tested in the second set, sending a selection command (the selection command of the current round) to the group of storage devices to be tested, under the selection command, only each first storage device to be tested having the first volume address is selected, and enabling the first memory device under test in the first set to perform a predetermined testing step, and each second storage device to be tested with the second volume address is not selected, and the preset test step is not executed. By processing in this way, the abnormal second storage equipment to be tested can be removed, and only the first storage equipment to be tested which is not abnormal is tested, so that the normal aging test of the first storage equipment to be tested which is not abnormal is not influenced.

The sharing of the same test signal by the memory devices under test in the group of memory devices under test may refer to that some of the memory devices under test in the group of memory devices under test share the same test signal, for example, the burn-in board shown in fig. 1 may simultaneously test 16 rows by 16 columns of DUTs, and the number of test channels of the burn-in board is relatively small, and the DUTs inevitably need to share the test signal, that is, some of the DUTs share the same test signal, another part of the DUTs share another test signal, and so on.

In some embodiments, the exception may be a test timeout.

In some embodiments, the test signals sharing the same may be at least one of: a Chip Enable (CE) signal, a Write Enable (WE) signal, a Read Enable (RE) signal, a Command Latch Enable (CLE) signal, an Address Latch Enable (ALE) signal, and a Ready/Busy (R/B) signal, and the like.

It should be noted that the storage device under test is the foregoing DUT. The test method can be applied to at least one of the tests of E/P/R as shown in FIG. 4, which is not the first test, because the test mode provided herein adopts the idea that the test result of the previous test guides the current test, and the specific reason is described later. The wheel described here is also the Cycle described above. The predetermined test step may be a test step in the original test item. That is, the embodiment of the present invention only rejects the DUT with the exception, and other test items may not be changed as before.

In some embodiments, the distinguishing the set of storage devices under test into the first set and the second set may include:

obtaining a test result of each storage device to be tested in the previous round of test; the test result is used for indicating whether each storage device to be tested is abnormal in the previous round of test;

distinguishing the group of storage devices to be tested into a first set and a second set based on the test result of each storage device to be tested;

the first storage equipment to be tested contained in the first set is the storage equipment to be tested, which is not abnormal in the previous round of testing, in the group of storage equipment to be tested; the second storage device under test included in the second set is a storage device under test in which an abnormality occurs in the previous round of testing in the group of storage devices under test.

Here, the previous round of test may refer to a previous test Cycle adjacent to the present round of test.

It should be understood that, when the anomaly is a test timeout, the obtaining of the test result of each storage device under test in the set of storage devices under test in the previous test may be determined by the Site Controller of the test system according to whether feedback information of the storage device under test responding to the test command is received within a preset time, where the test command is sent to the storage device under test by the Site Controller. The preset time may be set according to an empirical value. In some embodiments, feedback information of the storage device to be tested is not received within the preset time, and the test result is that the storage device to be tested has overtime in a previous test; and receiving feedback information of the storage equipment to be tested in the preset time, wherein the test result is that the storage equipment to be tested does not have test overtime in the previous round of test.

At this time, the DUT which has not been tested overtime in the previous round of test is called as a first storage device to be tested, and all the first storage devices to be tested form a first set; and (4) calling the DUT with the overtime test in the previous round of test as a second storage device to be tested, and combining all the second storage devices to be tested into a second set.

Thereafter, in some embodiments, the configuring a first volume address for the first storage device under test in the first set and a second volume address for the second storage device under test in the second set may include:

configuring the first to-be-tested storage device in the first set with the first volume address line by using a configuration mechanism in the ONFI standard; and configuring the second volume address for the second storage device to be tested in the second set line by using the configuration mechanism in the ONFI standard;

or, the first volume address is configured for the first storage device to be tested in the first set column by utilizing the configuration mechanism in the ONFI standard; and configuring the second volume address for the second storage device to be tested in the second set column by using the configuration mechanism in the ONFI standard.

It should be understood that when the interface unit of the NAND Flash chip adopts the ONFI standard, as shown in fig. 6A and 6B, one or more DIE selected by sharing the same CEn signal is called a Target, such as NAND0, NAND1, NAND2, NAND 3; each Target may contain a Volume (Volume) that is configured with a Volume Address (Volume Address). In practical use, a mass storage device may include one or more NAND Flash chips, and each NAND Flash chip may include one DIE or multiple DIEs. In the ONFI standard, a host coupled to a storage device may address a specified Volume (Volume) via a Volume Select Command (Volume Select Command). It should be noted that, as shown in fig. 6A and 6B, in a storage device, sometimes a plurality of NAND Flash chips share one pin for receiving an external command, at this time, whether the NAND Flash chip can receive a command sent by a host is determined by a level state of an ENi pin on the NAND Flash chip and a CE _ n signal state, only a signal state of a connected CE _ n pin is valid, and if the level state on the ENi pin on the chip is valid, the NAND Flash chip can receive a Volume Configuration command sent by the host, and the Volume Address carried in the command is a Volume Address of a selected chip; once configured with the Volume address, the chip output ENo becomes valid so that the chip of its base connection can receive the next Volume Configuration command; after the Volume address is configured, in order to enable a NAND Flash chip to normally receive and execute a BIT test Command, after CE _ n is valid each time, the NAND Flash chip needs to be selected through the Volume Select Command, and then the BIT Command is sent to perform a test.

For example, in the test method provided by the embodiment of the present invention, as shown in fig. 7, a connection relationship diagram of an ENi pin and an ENo pin on a single DUT (or referred to as a single NAND Flash) on a BIB board is shown. According to fig. 7, the level at the ENi pin of the NAND DIE2 in the NAND Flash is pulled up inside the NAND package, that is, the level state is high (active state), and the CE2 transmitted by the test channel is also active, at this time, the NAND DIE2 can receive the Command such as the Volume Configuration Command and the Volume Select Command sent by the Site Controller.

The Configuration mechanism herein may refer to a Volume Configuration (Volume Configuration) mechanism in the ONFI standard that can configure a Volume address to the aforementioned NAND Flash. The first volume address and the second volume address are two different volume addresses, that is, a DUT which has not timed out in the previous test round is set to have the first volume address; the DUT which has timed out in the previous round of test is set to have the second Volume address, so that the DUT with the first Volume address is selected by using the Volume Select Command to perform the subsequent burn-in test.

It should be understood that the first storage devices under test in the first set may be distributed in different rows and different columns, and thus, when configuring the first volume address for each first storage device under test in the first set, the configuration needs to be performed row by row or column by column. And similarly, configuring the second storage device to be tested in the second set.

It should be noted that, when Volume addresses are configured for the first storage device under test in the first set and the second storage device under test in the second set, because the first storage device under test in the first set and the second storage device under test in the second set may be in different rows or different columns in the test board, that is, the states of the DUTs in the test board may be different, when sending the Volume Configuration command, it is necessary to distinguish the DUTs in different rows in the test board using a disk selection function (DSEL) of the test host, and it is also necessary to set the Volume addresses of different DUT states in the same row using the function of the Data DUT to the test host.

Based on the ONFI standard, in some embodiments, before the distinguishing the set of storage devices under test into the first set and the second set, the method may further include:

and activating a configuration and selection mechanism of each storage device to be tested, wherein the configuration and selection mechanism is a specific function in an open NAND flash memory interface unit ONFI standard.

The configuration and selection mechanism may refer to a volume configuration mechanism and a volume selection mechanism, where the volume configuration mechanism is the function of configuring a volume address for the NAND Flash; the Volume selection mechanism is a function for addressing a designated Volume (Volume) by using the Volume Select Command as described above.

In an actual application process, the activating the configuration and selection mechanism of each storage device to be tested may include:

after the power is on, a read state command is sent to each storage device to be tested, and then each storage device to be tested is reset so as to activate the configuration and selection mechanism of each storage device to be tested.

It should be noted that the Read Status command is a command in the ONFI standard command set, and is used to obtain the operation result Status of the previous operation. The RESET referred to herein is a RESET (0xFF) command of the ONFI standard command set. Specifically, a read state command is sent to each memory device to be tested in the group of memory devices to be tested, and a RESET (RESET) step is performed on each memory device to be tested in the group of memory devices to be tested, so as to activate a configuration and selection mechanism in each memory device to be tested. It should be noted that the purpose of sending the Read Status command is not to Read the Status, but to activate the configuration and selection mechanism in each memory device under test in conjunction with RESET (RESET).

In some embodiments, before the sending the selection command to each of the set of storage devices under test, the method further comprises:

and reselecting each storage device to be tested in the group of storage devices to be tested.

It should be noted that, in the reselection of each storage device to be tested in the set of storage devices to be tested, the level of each CE signal is pulled up and then pulled down again, so as to select each storage device to be tested in the set of storage devices to be tested.

In some embodiments, the method may further comprise:

judging whether the test of the current round is the last test round or not; whether to end the test is determined based on the determination result.

In some embodiments, the method may further comprise:

when the judgment result is that the test of the current round is the last test, ending the test;

when the judgment result is that the current round of test is not the last round of test, continuously distinguishing the first storage equipment to be tested in the first set into different sets, and ending the test on the storage equipment to be tested in the different sets until one of the following conditions: the judgment result is that the test of the current round is the last test; the first set is an empty set.

Expressed here is the condition for ending the test for the loop test as E/P/R in fig. 4, one is to reach the maximum test loop, i.e. to reach the last round of test; it can also be that when the first set is an empty set, that is, all the DUTs are abnormal, it is not necessary to test the DUTs on the BIB again because all the DUTs are not qualified.

To understand the testing mode of the present invention, the testing environment may be as follows, by way of example: the conventional burn-in test mass production system is described above. A typical test flow (flow) based on this existing burn-in test mass production system can be seen in fig. 8. Based on the foregoing, DUT fail often occurs during the testing of the E/P/R cycle. A conventional E/P/R cycle may typically include: power on (Poweron), Reset (Reset), erase Block, Prog (program) pages and Read (Read) pages.

With the testing method provided by the embodiment of the present invention, the step of testing the E/P/R cycle in the flow may be as shown in fig. 9, and may specifically include:

the first step, Power on;

secondly, sending a Read Status command;

third, Reset.

It should be noted that the second and third steps are used to activate the configuration and selection mechanism in the DUT.

Fourthly, the Volume Configuration configures the Volume addresses of the DUTs row by row, and specifically configures the Volume addresses of the first to-be-tested storage devices in the first set as X; the Volume Address of the second storage device under test in the second set is configured as Y.

And step five, pulling up the CE and then pulling down the CE again so as to select all DUTs on the test board.

And sixthly, sending a Volume select command, and executing the test according to the steps in the test item in FIG. 8 after selecting the DUT with the Volume Address of X.

It should be noted that the whole description herein describes the flow of the test, and the specific implementation principle has been described in detail in the foregoing, which is not repeated herein.

According to the method for testing the storage device, provided by the embodiment of the invention, the storage device to be tested is divided into two different sets (a first set and a second set) according to the test result of the previous round of test, different volume addresses (a first volume address and a second volume address) are configured for the storage device to be tested in each set, then, the first set corresponding to the first volume address is selected based on the selection command, the preset test item of the round is executed on the first storage device to be tested in the first set, the second set corresponding to the second volume address is not selected, and the test is not performed without selection, so that the second storage device to be tested with the abnormality in the previous round is not executed again, the normal test of other storage devices without abnormality is not influenced, the test time is saved, and the purpose of saving the cost is achieved. Fig. 10 is a schematic diagram showing the Cycle test provided by the embodiment of the invention after the test timeout of the DUT2 in the polling mode of fig. 3, which uses the duration of the ready/busy state as the polling time. In FIG. 3, DUT2 has a longer polling time due to test timeout, and has a longer test time in the subsequent Cycle. Thereafter, after the testing method provided by the embodiment of the present invention is adopted, as shown in FIG. 10, the DUT2 will not execute the test command issued to the first volume address, and thus will not cause the command to time out.

Based on the same inventive concept, as shown in fig. 11, a schematic structural diagram of a testing apparatus for a memory device according to an embodiment of the present invention is shown. In fig. 11, the apparatus 110 includes: a distinguishing module 1101, a configuration module 1102, a sending module 1103 and an execution module 1104, wherein;

the distinguishing module 1101 is configured to distinguish a group of storage devices to be tested into a first set and a second set; the first set comprises non-abnormal first storage equipment to be tested in the group of storage equipment to be tested; the second set comprises abnormal second storage equipment to be tested in the group of storage equipment to be tested; some memory devices to be tested in the group of memory devices to be tested share the same test signal;

the configuring module 1102 is configured to configure a first volume address for the first storage device to be tested in the first set, and configure a second volume address for the second storage device to be tested in the second set;

the sending module 1103 is configured to send a selection command to each storage device to be tested in the set of storage devices to be tested, where the selection command selects the first set of the first volume addresses;

the executing module 1104 is configured to enable the first storage device under test in the first set to execute a preset testing procedure.

In some embodiments, the apparatus 110 further includes an activation module, configured to activate a configuration and selection mechanism of each storage device under test, where the configuration and selection mechanism is a specific function in the open NAND flash memory interface unit ONFI standard.

In some embodiments, the activation module is specifically configured to: and sending a reading state command to each storage device to be tested, and resetting each storage device to be tested so as to activate a configuration and selection mechanism of each storage device to be tested.

In some embodiments, the distinguishing module is specifically configured to: obtaining a test result of each storage device to be tested in the previous round of test; the test result is used for indicating whether each storage device to be tested is abnormal in the previous round of test; dividing the group of storage devices to be tested into a first set and a second set based on the test result of each storage device to be tested; the first storage equipment to be tested contained in the first set is the storage equipment to be tested, which is not abnormal in the previous round of testing, in the group of storage equipment to be tested; the second storage device under test included in the second set is a storage device under test in which an abnormality occurs in the previous round of testing in the group of storage devices under test.

In some embodiments, the configuration module is specifically configured to: configuring the first to-be-tested storage device in the first set with the first volume address line by using a configuration mechanism in the ONFI standard; and configuring the second volume address for the second storage device to be tested in the second set line by using the configuration mechanism in the ONFI standard;

or, the first volume address is configured for the first storage device to be tested in the first set column by utilizing the configuration mechanism in the ONFI standard; and configuring the second volume address for the second storage device to be tested in the second set column by utilizing the configuration mechanism in the ONFI standard.

In some embodiments, the apparatus further includes a re-setting module, where the re-setting module is configured to re-select each storage device under test in the set of storage devices under test.

In some embodiments, the apparatus further comprises a determining module and a determining module, wherein;

the judging module is used for judging whether the test of the current round is the last test;

and the determining module is used for determining whether to finish the test or not based on the judgment result.

In some embodiments, the determining module is specifically configured to: when the judgment result is that the test of the current round is the last test, ending the test; when the judgment result is that the current round of test is not the last round of test, continuously distinguishing the first storage equipment to be tested in the first set into different sets, and testing the storage equipment to be tested in the different sets until one of the following conditions is met: the judgment result is that the test of the current round is the last test; the first set is an empty set.

In some embodiments, the exception is a test timeout.

It should be noted that the testing apparatus provided in the embodiment of the present invention and the testing method provided in the embodiment of the present invention belong to the same inventive concept, and the meanings of the words appearing herein have been described in detail in the foregoing, and are not described herein again.

Embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the foregoing method embodiments, and the foregoing storage medium includes: a mobile storage device, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

An embodiment of the present invention further provides an electronic device, where the electronic device includes: a processor and a memory for storing a computer program capable of running on the processor, wherein the processor is configured to execute the steps of the above-described method embodiments stored in the memory when running the computer program.

Fig. 12 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention, where the electronic device 120 includes: the at least one processor 1201, the memory 1202, and optionally the electronic device 120 may further include at least one communication interface 1203, and the various components in the electronic device 120 are coupled together by a bus system 1204, it being understood that the bus system 1204 is used to implement the connection communication between these components. The bus system 1204 includes a power bus, a control bus, and a status signal bus, in addition to a data bus. For clarity of illustration, however, the various buses are labeled as bus system 1204 in fig. 12.

It will be appreciated that the memory 1202 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic Random Access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical Disc, or a Compact Disc Read-Only Memory (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced Synchronous Dynamic Random Access Memory), Synchronous linked Dynamic Random Access Memory (DRAM, Synchronous Link Dynamic Random Access Memory), Direct Memory (DRmb Random Access Memory). The memory 1202 described in connection with the embodiments of the present invention is intended to comprise, without being limited to, these and any other suitable types of memory.

The memory 1202 in embodiments of the present invention is used to store various types of data to support the operation of the electronic device 120. Examples of such data include: any computer program for operating on electronic device 120, such as an implementation that configures a first volume address for the first storage device under test in the first set and configures a second volume address for the second storage device under test in the second set, may be embodied in memory 1202 for implementing the method of an embodiment of the present invention.

The method disclosed by the embodiment of the invention can be applied to the processor 1201 or implemented by the processor 1201. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The Processor may be a general purpose Processor, a Digital Signal Processor (DSP), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present invention. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed by the embodiment of the invention can be directly implemented by a hardware decoding processor, or can be implemented by combining hardware and software modules in the decoding processor. The software modules may be located in a storage medium having a memory and a processor reading the information in the memory and combining the hardware to perform the steps of the method.

In an exemplary embodiment, the electronic Device 120 may be implemented by one or more Application Specific Integrated Circuits (ASICs), DSPs, Programmable Logic Devices (PLDs), Complex Programmable Logic Devices (CPLDs), Field Programmable Gate Arrays (FPGAs), general purpose processors, controllers, Micro Controllers (MCUs), microprocessors (microprocessors), or other electronic components for performing the above-described methods.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment. In addition, all the functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A method of testing a memory device, the method comprising:

sending a selection command to each storage device to be tested in the group of storage devices to be tested; the selection command is used for selecting only the first set corresponding to the first volume address;

2. The method of claim 1, wherein prior to said distinguishing a set of storage devices under test into a first set and a second set, the method further comprises:

3. The method of claim 2, wherein the activating the configuration and selection mechanism of each storage device under test comprises:

and sending a reading state command to each storage device to be tested, and resetting each storage device to be tested so as to activate a configuration and selection mechanism of each storage device to be tested.

4. The method of claim 2, wherein the distinguishing the set of storage devices under test into a first set and a second set comprises:

dividing the group of storage devices to be tested into a first set and a second set based on the test result of each storage device to be tested;

5. The method of claim 4, wherein configuring a first volume address for the first storage device under test in the first set and a second volume address for the second storage device under test in the second set comprises:

6. The method of claim 1, wherein before sending the selection command to each of the set of storage devices under test, the method further comprises:

7. The method of claim 1, further comprising:

judging whether the test of the current round is the last test; whether to end the test is determined based on the determination result.

8. The method of claim 7, further comprising:

9. The method of claim 1, wherein the exception is a test timeout.

10. The method of any one of claims 1 to 9, wherein the test signal is at least one of: a chip enable signal, a write enable signal, a read enable signal, a command latch enable signal, an address latch enable signal, a ready/busy signal.

11. An apparatus for testing a memory device, the apparatus comprising: the system comprises a distinguishing module, a configuration module, a sending module and an execution module, wherein the distinguishing module is used for distinguishing the data;

the sending module is used for sending a selection command to each storage device to be tested in the group of storage devices to be tested; the selection command is used for selecting only the first set corresponding to the first volume address;

12. An electronic device comprising a memory and a processor, wherein the memory has instructions stored therein;

the processor is configured to execute instructions in the memory, and when executed by the processor, the processor implements the method of any one of claims 1 to 10.

13. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, carries out the method of any one of claims 1 to 10.