KR100609573B1 - Flash memory device and method for testing the same - Google Patents

Abstract

The present invention relates to a flash memory device and a test method thereof. The present invention relates to an address and a redundancy cell of a main cell array through an address counter during a program and read operation for a test of a flash memory device. The address of the array is sequentially counted, and the program or read operation of the main cell array and the redundant cell array are simultaneously performed. Therefore, in the present invention, it is possible to reduce the test cost by shortening the test time.

Flash memory device, test, program, lead

Description

Flash memory device and its test method {FLASH MEMORY DEVICE AND METHOD FOR TESTING THE SAME}

1 is a block diagram illustrating a flash memory device according to a preferred embodiment of the present invention.

FIG. 2 is a flowchart illustrating a program operation of the flash memory device shown in FIG. 1.

3 is a flowchart illustrating a read operation of the flash memory device illustrated in FIG. 1.

<Explanation of symbols for main parts of drawing>

10: main memory cell array

11, 21: page buffer

20: redundancy memory cell array

12, 22: Y-decoder

31: address counter

32: test setting unit

34: I / O pad part

The present invention relates to a flash memory device and a test method thereof, and more particularly, to a flash memory device and a test method thereof that can shorten the test time (test time) of the flash memory device.

In a memory device such as a DRAM (Dynamic Random Access Memory) or a flash memory device, a repair that replaces a defective cell with a redundancy cell when a failure occurs in the main cell. The repair method is used. To this end, a cell array includes a main memory cell array composed of a plurality of main cells and a redundant memory cell array composed of a plurality of redundant cells.

On the other hand, before performing the repair operation of the semiconductor memory device, a test operation for confirming whether a redundancy cell is defective is performed. This is to prevent a defective cell from being replaced by a redundant memory cell array in which a defective cell is generated during a repair operation. The test operation is performed through a program and a read operation. Currently, the main memory cell array and the redundancy memory cell array are separated from each other. That is, after the test for the main memory cell array is completed, the test for the redundant memory cell array is performed.

In this case, the program (or write / read) operation speed is very high in DRAM, so even if the main memory cell array and the redundant memory cell array are tested separately, a test time is required. This does not increase significantly. However, since a flash memory device has a long program time and a read time, when a main memory cell array and a redundant memory cell array are separately tested, a very large test time is required.

For reference, the program time of an entire chip main memory cell array required for testing a 512M flash memory device is 327,688,000 ㎲ (250 ㎲ 32 4096). Here, the program time per page is 250 ms. Of course, the program time of the redundant memory cell array also needs almost the same time as the program time of the main memory cell array. The lead time is 1,572,864 ㎲ (12 ms x 32 x 4096). Here, the lead time per page is 12 ms. Of course, the read time of the redundant memory cell array is the same as that of the main memory cell array. As a result, when the tests of the main memory cell array and the redundancy memory cell array are separately performed, the test time is almost twice as long.

Accordingly, an object of the present invention is to provide a flash memory device and a test method thereof that can reduce the test time of a flash memory device.

According to an aspect of the present invention for realizing the above object, a first memory cell array, a second memory cell array for replacing defective cells of the first memory cell array, and receives the first data A first page buffer for programming to a first memory cell array or for reading the first data stored in the first memory cell array and receiving second data to program the second memory cell array; A second page buffer for reading the second data stored in the memory cell array, an address counter for sequentially counting addresses of the first and second memory cell arrays according to a test bit setup signal, and from the address counter Sequentially order the first data transmitted from the I / O pad unit according to the address of the first memory cell array to be counted A first decoder unit configured to load into the first page buffer or sequentially output the first data from the first page buffer to the I / O pad unit, and after counting addresses of the first memory cell array are completed. Sequentially load the second data transmitted from the I / O pad unit into the second page buffer according to the test bit setup signal and the redundancy test signal and the address of the second memory cell array counted from the address counter; And a second decoder unit configured to sequentially output the second data from the second page buffer to the I / O pad unit.

In addition, according to another aspect of the present invention for implementing the above object, the step of enabling the test bit setup signal to enter the flash memory device in the redundant active mode, and inputting the program setup command to set up the program operation And sequentially counting addresses of the first and second memory cell arrays through the address counter unit, and sequentially transmitting data transmitted from the I / O pad unit through the first and second decoder units controlled according to the counted addresses. Loading into a first page buffer connected to the first memory cell array and a second page buffer connected to the second memory cell array, and simultaneously using data loaded into the first and second page buffers by a program confirm command. Flash memo comprising programming the first and second memory cell arrays It provides a way to test the device.

 In addition, according to another aspect of the present invention for implementing the above object, the step of enabling the test bit setup signal to enter the flash memory device in the redundancy active mode, inputting the read setup command to set up the read operation And sequentially counting addresses of the first and second memory cell arrays through the address counter unit, and connecting data stored in the first and second memory cell arrays to the first memory cell array by a read confirm command. Reading the first page buffer and the second page buffer connected to the second memory cell array, and sequentially reading the data read into the first and second page buffers through the first and second decoder sections controlled according to the counted address; Provided is a method of testing a flash memory device comprising outputting to an I / O pad portion. .

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 is a block diagram of a flash memory device according to a preferred embodiment of the present invention.

Referring to FIG. 1, a flash memory device according to an exemplary embodiment of the present invention may include a main memory cell array 10, a redundancy memory cell array 20, page buffers 11 and 21, and a Y-decoder Y. decorders 12 and 22, an address counter 31 and a test setup section 32;

The main memory cell array 10 consists of a plurality of memory cells. The redundancy memory cell array 20 is composed of a plurality of memory cells to replace defective cells of the main memory cell arrays 10. Typically, the redundancy memory cell array 20 consists of smaller memory cells than the main memory cell array 10.

The page buffer 11 stores data transmitted through the Y-decoder 12 during a program operation, and then transfers the stored data to the main memory cell array 10 when a program confirm command is input. Perform. In the read operation, data stored in the main memory cell array 10 is read by a read confirm command.

The page buffer 21 stores data transmitted through the Y-decoder 22 at the same time as the page buffer 11 during a program operation, and then transfers the stored data to the redundancy memory cell array 20 when a program confirm command is input. Run the program. In the read operation, data stored in the redundancy memory cell array 20 is read out simultaneously with the page buffer 11 by a read confirm command.

The Y-decoder 12 loads the data transferred from the I / O pad unit 34 into the page buffer 11 according to the address of the main memory cell array provided from the address counter 31 during the program operation. In the read operation, the data read into the page buffer 11 is output to the I / O pad unit 34.

The Y-decoder 22 performs an address counter 31 after the loading operation of the main memory cell array 10 by the Y-decoder 12 (that is, the operation of loading data into the page buffer 11) is completed. The data transferred from the I / O pad unit 34 is loaded into the page buffer 21 in accordance with the address of the redundancy memory cell array 20 counted from the main memory array array 20. Redundancy memory cell array 20 counted from address counter 31 after the output operation of memory cell array 10 (i.e., outputting data from page buffer 11 to I / O pad 34) is complete. The data transmitted from the page buffer 21 is output to the I / O pad section 34 in accordance with the address of.

The address counter 31 adjusts the address of the main memory cell array 10 and the address of the redundancy memory cell array 20 according to a test bit set-up signal TREDFORCEr provided from the test setting unit 32. Counting sequentially. That is, after counting the addresses of the main memory cell array 10 first, when the counting of the addresses of the main memory cell array 10 is completed, the addresses of the redundancy memory cell array 20 are automatically counted sequentially.

Hereinafter, a test method of the flash memory device shown in FIG. 1 will be described. 2 and 3 are flowcharts illustrating a test method of a flash memory device according to an exemplary embodiment of the present invention. 2 is a flowchart illustrating a program operation, and FIG. 3 is a flowchart illustrating a read operation.

Program behavior

1 and 2, first, prior to performing a program operation, a test mode is entered to test a flash memory device. In this state, the test bit setup signal TREDFORCEr is enabled through the test setting unit 32. The test bit setup signal TREDFORCEr is a test bit signal and is a signal forcibly entering a redundancy active mode.

The redundancy active mode refers to a mode that automatically enters a redundancy test mode for testing the redundancy memory cell array 20 when the test operation on the main memory cell array 10 is completed. That is, when address counting of the main memory cell array 10 is completed by the address counter 31, the address counter 31 automatically counts the address of the redundancy memory cell array 20 by the test bit setup signal TREDFORCEr. Then, the Y-decoder 22 is opened to sequentially load data from the I / O pad 34 into the page buffer 21.

Meanwhile, after the test bit setup is completed, when a program set-up command is input as shown in FIG. 1, the program operation is set up (S10). Then, an address is set in units of pages through the address counter 31 (S11). This is because in the case of a flash memory device, a program operation is performed in units of pages. The address setting process is a process of sequentially counting the addresses of the main memory cell array 10 to the addresses of the redundancy memory cell array 11 by the address counter 31. The address counter 31 automatically counts the addresses of the redundancy memory cell array 20 when the counting of the addresses of the main memory cell array 10 is completed.

When the page address is set by the address counter 31, data is sequentially loaded into the page buffer 11 from the I / O pad unit 34 through the Y-decoder 12. After the main memory cell array data is loaded into the page buffer 11, the address counter 31 assigns an address of the redundancy memory cell array 20 so that the redundancy memory cell array data is set to Y- from the I / O pad 34. Loading into the page buffer 21 through the decoder 22 begins (S12). In this process, after the address of the main memory cell array 10 is set by the address counter 31, the address of the redundancy memory cell array 20 is automatically set, and the test bit setup signal of the test setting unit 32 is set. The TREDFORCEr and the redundancy test signal TREDr are enabled by the enable. As described above, the test bit setup signal TREDFORCEr is previously enabled before the input step S10 of the program setup command is executed.

Then, when a program confirm command is input, the main memory cell array data or the redundancy memory cell array data loaded in the page buffers 11 and 21, respectively, is simultaneously displayed in the main memory cell array 10 or the redundant memory cell. The program is executed by loading into the array 20 (S13 and S14). In this case, the program operation is performed in units of pages as described above.

Then, a program verification operation is performed to determine whether the program operation is normally performed (S15 and S16). Here, the program operation S14 and the program verifying operations S15 and S16 are repeatedly performed until the program is normally performed.

Lead behavior

1 and 3, first, prior to performing a read operation, a test mode is entered to test a flash memory device. In this state, the test bit setup signal TREDFORCEr is enabled through the test setting unit 32. The test bit setup signal TREDFORCEr is a test bit signal and is a signal forcibly entering a redundancy active mode.

The redundancy active mode refers to a mode that automatically enters a redundancy test mode for testing the redundancy memory cell array 20 when the test operation on the main memory cell array 10 is completed. In the redundancy active mode, when address counting of the main memory cell array 10 is completed by the address counter 31, the address counter 31 is automatically redundancy by the test bit setup signal TREDFORCEr. Performs address counting. Accordingly, when data is read from the main memory cell array 10 to the page buffer 11 and then the address of the redundancy memory cell array 20 is counted, the data of the redundancy memory cell array 20 is replaced by the redundancy memory cell array 20. ) Is sequentially read into the page buffer 21.

On the other hand, after the test bit setup is completed, when a read set command (read set-up command) is input, the read operation is set up (S20). Then, the address is set in units of pages through the address counter 31 (S21). The address setting process is performed in the same way as the program operation. That is, the address counter 31 sequentially counts the addresses from the main memory cell array 10 to the addresses of the redundant memory cell array 20. The address counter 31 automatically counts the addresses of the redundancy memory cell array 20 when the counting of the addresses of the main memory cell array 10 is completed.

Then, when a read confirm command is input as shown in FIG. 3, the main memory cell array 10 and the redundancy are enabled by the enabled test bit setup signal TREDFORCEr and the redundancy test signal TREDr. Data is simultaneously read from the memory cell array 20 into the page buffers 11 and 21, respectively.

Then, the data read into the respective page buffers 11 and 21 are output to the I / O pad portion 34 through the respective Y-decoders 12 and 22. At this time, the data read into the page buffers 11 and 21 are sequentially output to the I / O pad unit 34 according to the toggle of / RE. That is, the address counter 31 counts the address of the main memory cell array 10, and when / RE is toggled, data output is sequentially performed from the first data among the data programmed in the main memory cell array 10. Then, when all data of the main memory cell array 10 is output, the address counter 31 allocates the address of the redundancy memory cell array 20 to count the address of the redundancy memory cell array 20. In this state, when / RE is toggled, data output is sequentially performed from the first data among the data of the redundancy memory cell array 20. In fact, data transmitted from the page buffers 11 and 21 and output through the Y-decoder 12 and 22 is transferred to the I / O pad section through an I / O multi-plexer (not shown). It is outputted to 34.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the address of the main memory cell array and the address of the redundancy memory cell array are sequentially controlled through an address counter during a program and a read operation for a test of the flash memory device. By simultaneously performing a program or read operation of the main memory cell array and the redundant memory cell array, the test time can be shortened, thereby reducing the test cost.

Claims (3)

A first memory cell array; A second memory cell array for replacing defective cells of the first memory cell arrays; A first page buffer for receiving first data to program the first memory cell array or to read the first data stored in the first memory cell array; A second page buffer configured to receive second data to program the second memory cell array or to read the second data stored in the second memory cell array; An address counter for sequentially counting addresses of the first and second memory cell arrays according to a test bit setup signal; The first data transmitted from the I / O pad unit may be sequentially loaded into the first page buffer according to the address of the first memory cell array counted from the address counter, or the first data may be loaded from the first page buffer. A first decoder unit sequentially outputting the I / O pad unit; And The first data transmitted from the I / O pad unit according to the test bit setup signal and the redundancy test signal and the address of the second memory cell array counted from the address counter after the counting of the address of the first memory cell array is completed; And a second decoder unit configured to sequentially load data into the second page buffer or sequentially output the second data from the second page buffer to the I / O pad unit. 1. A method of testing a flash memory device comprising a first memory cell array and a second memory cell array for replacing defective cells of the first memory cell arrays. (a) enabling the test bit setup signal to enter the flash memory device in a redundant active mode; (b) entering a program setup command to set up a program operation; (c) sequentially counting addresses of the first and second memory cell arrays through an address counter unit; (d) a first page buffer and the second memory cell array sequentially connecting data transmitted from an I / O pad unit through the first and second decoder units controlled according to the address to be counted to the first memory cell array; Loading to a second page buffer coupled to; And (e) programming the first and second memory cell arrays simultaneously using data loaded into the first and second page buffers by a program confirm command. 1. A method of testing a flash memory device comprising a first memory cell array and a second memory cell array for replacing defective cells of the first memory cell arrays. (a) enabling the test bit setup signal to enter the flash memory device into a redundant active mode; (b) inputting a read setup command to set up a read operation; (c) sequentially counting addresses of the first and second memory cell arrays through an address counter unit; (d) reading data stored in the first and second memory cell arrays into a first page buffer connected to the first memory cell array and a second page buffer connected to the second memory cell array by a read confirm command; ; And and (e) sequentially outputting data read into the first and second page buffers to the I / O pad unit through the first and second decoder units controlled according to the address being counted. How to.

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