CN113723045A - Design method of digital integrated circuit - Google Patents
Design method of digital integrated circuit Download PDFInfo
- Publication number
- CN113723045A CN113723045A CN202111004448.7A CN202111004448A CN113723045A CN 113723045 A CN113723045 A CN 113723045A CN 202111004448 A CN202111004448 A CN 202111004448A CN 113723045 A CN113723045 A CN 113723045A
- Authority
- CN
- China
- Prior art keywords
- edge
- trigger
- double
- library
- library file
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 90
- 238000013461 design Methods 0.000 title claims abstract description 44
- 230000008569 process Effects 0.000 claims abstract description 66
- 238000004088 simulation Methods 0.000 claims abstract description 35
- 230000000630 rising effect Effects 0.000 claims abstract description 33
- 238000012795 verification Methods 0.000 claims abstract description 17
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 15
- 238000003786 synthesis reaction Methods 0.000 claims abstract description 15
- 230000009977 dual effect Effects 0.000 claims description 6
- 238000007689 inspection Methods 0.000 claims description 3
- 238000012938 design process Methods 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 3
- 230000006870 function Effects 0.000 description 21
- 238000010586 diagram Methods 0.000 description 7
- 239000013256 coordination polymer Substances 0.000 description 6
- 230000001960 triggered effect Effects 0.000 description 6
- 230000006399 behavior Effects 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Architecture (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The design method comprises the steps of extracting the time sequence characteristics of the rising edge and the falling edge of a double-edge dynamic trigger, obtaining a first library with larger time sequence characteristic parameters, unifying the first library into a rising edge trigger type, obtaining a first process library file, and executing design input, logic synthesis, form verification, layout and wiring, time sequence check and physical verification of the traditional design process and a corresponding simulation process according to a double-edge dynamic trigger functional model and the first process library file. The design method of the digital integrated circuit of the invention manufactures the first process library file according to the time sequence characteristic parameter with larger parameter in the time sequence characteristics of the rising edge and the falling edge, and executes the traditional design flow according to the first process library file, thereby simplifying the integration of the double-edge dynamic trigger in the digital integrated circuit design while ensuring the reliability of the designed circuit, and providing convenience for the application of the double-edge dynamic trigger in the digital integrated circuit.
Description
Technical Field
The invention relates to the technical field of digital integrated circuit design, in particular to a design method of a digital integrated circuit.
Background
With the widespread application of digital signal processing, filter units, convolution operations and the like are required in the design of digital signal processing circuits, and these operation units consume a lot of triggers.
According to the statistical data in the chip design, the power consumption of the trigger unit in the digital signal processing design can account for more than 50% of the whole chip.
The traditional triggers are all single-edge triggers, while the double-edge dynamic trigger can trigger data twice in one clock cycle to process different data, compared with the single-edge trigger, the double-edge dynamic trigger can reduce the frequency of a clock signal to a half, and the area and the power consumption of a clock path and the trigger can be effectively reduced.
Therefore, the double-edge dynamic trigger is applied to the design of a digital integrated circuit, the overall power consumption of a system can be effectively reduced, and the double-edge dynamic trigger has considerable practical value.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a method for designing a digital integrated circuit, so as to apply a dual-edge dynamic flip-flop to the design of the digital integrated circuit, thereby facilitating the reduction of system power consumption for designing a chip.
According to an aspect of the present invention, there is provided a method of designing a digital integrated circuit, comprising:
respectively extracting the characteristics of the rising edge and the falling edge of the double-edge dynamic trigger to obtain a first library and a second library, wherein the time sequence characteristic parameter of the first library is greater than that of the second library;
modifying the first library into a rising edge trigger type to obtain a first process library file;
adding a double-edge trigger characteristic to a double-edge dynamic trigger of the simulation library to obtain a double-edge dynamic trigger functional model with the double-edge trigger characteristic;
sequentially performing design input, logic synthesis, formal verification, layout and wiring, timing inspection, and physical verification to complete design according to the double-edge dynamic trigger function model and the first process library file,
performing RTL function simulation according to the RTL level circuit description file obtained in the design input step;
performing netlist functional simulation according to the first gate-level netlist obtained in the logic synthesis step;
and performing netlist time sequence simulation according to the second gate-level netlist and the digital layout obtained in the step of laying out and wiring.
Optionally, in the step of extracting the characteristics of the rising edge and the falling edge of the dual-edge dynamic trigger respectively, the characteristics of the timing sequence and the power consumption of the rising edge and the falling edge of the dual-edge dynamic trigger are extracted respectively.
Optionally, the method further comprises:
modifying the second library to a rising edge trigger type to obtain a second process library file,
modifying both the first library and the second library to be of a falling edge trigger type to obtain a third process library file and a fourth process library file respectively,
and the time sequence checking step is used for simultaneously checking the time sequence according to the first process library file, the second process library file, the third process library file and the fourth process library file.
Optionally, in the steps of logic synthesis, formal verification, and layout and routing, the corresponding dual-edge dynamic trigger of the dual-edge dynamic trigger function model is used as a single-edge trigger, and the data trigger frequency is the same as the data trigger frequency of the dual-edge dynamic trigger.
Optionally, in the step of performing netlist function simulation according to the first gate-level netlist obtained in the logic synthesis step, and performing netlist timing sequence simulation according to the second gate-level netlist and the digital layout obtained in the layout and routing step, the double-edge dynamic trigger of the corresponding double-edge dynamic trigger function model is a double-edge dynamic trigger behavior.
Optionally, the method further comprises:
modifying the second library to a rising edge trigger type to obtain a second process library file,
and in the wiring step, automatic wiring and layout processes are carried out simultaneously according to the first process library file and the second process library file.
Optionally, in the step of adding the double-edge trigger characteristic to the double-edge dynamic trigger of the emulation library, the method further includes performing timing sequence check on the maximum time of the clock according to the requirement of the double-edge dynamic trigger on the length of the clock.
The design method of the digital integrated circuit provided by the invention collects the rising edge time sequence characteristics and the falling edge time sequence characteristics of the double-edge dynamic trigger, obtains a first library with larger time sequence requirements, unifies the first library into rising edge trigger types to obtain a first process library file, then executes the design input, logic synthesis, form verification, layout wiring, time sequence check and physical verification of the traditional design process according to the double-edge dynamic trigger function model and the first process library file, and executes the RTL function simulation, netlist function simulation and netlist time sequence simulation process, integrates the double-edge dynamic trigger into the design of the digital integrated circuit, manufactures the first process library file according to the time sequence characteristics with larger time sequence requirements in the rising edge time sequence characteristics and the falling edge time sequence characteristics, executes the traditional design process according to the first process library file, guarantees the reliability of the designed circuit, and simplifies the double-edge dynamic trigger in the digital integrated circuit The integration in the circuit design provides convenience for the application of the double-edge dynamic trigger in the digital integrated circuit, and reduces the power consumption of the digital integrated circuit system obtained by design.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a schematic diagram of a dual edge dynamic flip-flop according to the prior art;
FIG. 2 shows a data trigger diagram of a double-edge dynamic flip-flop according to the prior art;
fig. 3 shows a flow chart of a design method of a digital integrated circuit according to an embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 1 shows a schematic diagram of a dual-edge dynamic flip-flop according to the prior art.
Referring to fig. 1, the dual edge dynamic flip-flop includes a transistor MP1, a transistor MP2, a transistor MN1, and a transistor MN2 connected in series between a first reference voltage source and a second reference voltage source, the transistor MP3 and the transistor MN3 are connected in series and then connected in parallel with a series structure of a transistor MP2 and a transistor MN1, gates of the transistor MP1 and the transistor MN2 are connected to an input terminal D of the dual edge dynamic flip-flop, gates of the transistor MP2 and the transistor MN3 receive a second clock signal CK2, gates of the transistor MN1 and the transistor MP3 receive a first clock signal CK1, a first level signal OUT1 is provided at an intermediate node between the transistor MP1 and the transistor MN1, and a second level signal OUT2 is provided at an intermediate node between the transistor MP3 and the transistor MN 3.
In this embodiment, the transistors MP1, MP2, and MP3 are PMOS (P-Metal-Oxide-Semiconductor) transistors, and the transistors MN1, MN2, and MN3 are NMOS (N-Metal-Oxide-Semiconductor) transistors.
The clock signal CP received by the clock signal input end is converted into a first clock signal CK1 and a second clock signal CK2 which are mutually inverted through an inverter A1 and an inverter A2 which are connected in series, when the first clock signal CK1 is at a high level and the second clock signal CK2 is at a low level, a transistor MP2 and a transistor MN1 are turned on, and according to the state of input data, a first level signal OUT1 is at a first level VDD (high level reference, corresponding to 1 of a digital signal) or a second level VSS (low level reference, corresponding to 0 of the digital signal), so that rising edge triggering is realized; when the first clock signal CK1 is at a low level and the second clock signal CK2 is at a high level, the transistor MP3 and the transistor MN3 are turned on, and the second level signal OUT2 is at the first level VDD or the second level VSS according to the state of the input data, thereby realizing falling edge triggering.
The first level signal OUT1 is transmitted to the output end Q of the double-edge dynamic flip-flop through the latch A3, the second level signal OUT2 is transmitted to the output end Q of the double-edge dynamic flip-flop through the latch A4, the latch A3 and the latch A4 are controlled to be opened in a time sharing mode according to the first clock signal CK1 and the second clock signal CK2, when the first clock signal CK1 is at a high level and the second clock signal CK2 is at a low level, rising edge triggering is carried OUT, meanwhile, the latch A3 is opened, the first level signal OUT1 is output, and rising edge triggering data output is achieved; when the first clock signal CK1 is at low level and the second clock signal CK2 is at high level, the falling edge triggers and the latch a4 is turned on, and the second level signal OUT2 realizes the falling edge triggered data output.
Fig. 2 shows a data triggering diagram of a double-edge dynamic flip-flop according to the prior art.
Referring to fig. 2, when data is input at the input end D, corresponding data output is provided at the output end Q according to the triggering of the input clock signal CP, data a is collected and data Aq is output at the output end Q when a first rising edge of the clock signal CP is triggered, data B is collected and data Bq is output at the output end Q when a first falling edge is triggered, and data C is collected and data Cq is output at the output end Q when a rising edge of a second period of the clock signal CP is triggered. The single-edge dynamic trigger can acquire data twice in one clock cycle, the clock cycle is equal to twice the unit length of the data, one clock cycle of the single-edge trigger acquires data once, and the clock cycle is equal to the unit length of the data, namely the clock cycle of the double-edge dynamic trigger is long, low in frequency and low in power consumption.
The design method of the digital integrated circuit mainly adopts the double-edge dynamic trigger, the number of the transistors is small, the occupation of the double-edge dynamic trigger on the area of a chip layout can be reduced, the wiring complexity is reduced, the area of the chip is optimized, and the cost is reduced.
Fig. 3 shows a flow chart of a design method of a digital integrated circuit according to an embodiment of the invention.
Referring to fig. 3, the method for designing a digital integrated circuit according to the embodiment of the present invention includes:
in step S11, a timing feature extraction is performed on the dual-edge dynamic trigger circuit to obtain a first library file and a second library file (or simply referred to as a first library and a second library).
The dual-edge dynamic flip-flop circuit in step S11 is the dual-edge dynamic flip-flop circuit shown in fig. 1.
In step S11, the timing characteristics (including timing characteristics and power consumption characteristics) of the rising edge and the falling edge of the dual-edge dynamic trigger circuit are extracted respectively, that is, two times of timing characteristic extraction operations are performed, and classification is performed according to the extracted timing characteristic parameters (delay information, driving capability, and the like) of the library file, so as to obtain a first library file and a second library file after classification, where the timing characteristic parameter of the first library file is greater than the timing characteristic parameter of the second library file.
In step S11, the extracted timing characteristic parameters of the dual-edge dynamic trigger include, but are not limited to, setup time, hold time, rise time (level rise time), and fall time (level fall time), for example:
the time sequence characteristic parameters extracted by the simulation of the rising edge trigger time sequence are as follows: setting 0.50 for setimite, 0.20 for holdtimite, 0.30 for risetime, 0.25 for falltime, and the time sequence characteristic parameters of simulation extraction of falling edge trigger time sequence are as follows: setuptime ═ 0.44, holdtime ═ 0.22, risetime ═ 0.31, and falltime ═ 0.23, where the units are nanoseconds (ns).
Correspondingly, processing is carried out according to the size of each parameter, and the obtained time sequence characteristic parameters of the first library file are as follows: setuptime is 0.50, holdtime is 0.22, risetime is 0.31, falltime is 0.25, and the time sequence characteristic parameters of the second library file are as follows: setuptime ═ 0.44, holdtime ═ 0.20, risetime ═ 0.30, and fallmetime ═ 0.23. And unifying the trigger types of the first library file and the second library file into rising edge trigger or falling edge trigger, and obtaining the corresponding process library file.
In step S12, find the timing requirement greater value and smaller value, and uniformly make the process library according to the rising edge, i.e., modify the first library file and the second library file to be obtained into the rising edge trigger type, to obtain the first process library file and the second process library file, where the first process library file is the greater value process library and the second process library file is the smaller value process library.
The first process library file and the second process library file correspond to process library files of a model library of the double-edge dynamic trigger.
Step S12 further includes making a process library from the first library file and the second library file according to the falling edge, so as to obtain a third process library file and a fourth process library file, respectively.
Step S20: RTL design input (design input for short).
In the design input step, the designer completes the design of the circuit as required. The design process may describe the behavior and/or structure of the circuit in a textual and/or graphical manner, forming a circuit description file at the RTL (Register-Transfer Level) Level. The text mode is, for example, Hardware Description Language (HDL) such as Verilog and VHDL, the graphic mode is, for example, schematic diagram and state diagram, the circuit behavior refers to the relationship between the input and output of the circuit and the timing relationship thereof, and the circuit structure refers to the functional modules, units, gates and the connection relationship therebetween.
In step S13, the dual-edge dynamic trigger in the emulation library is added with the dual-edge trigger characteristic, and a dual-edge dynamic trigger function model is obtained. And the time sequence of the maximum time of the clock is checked according to the requirement of the double-edge dynamic trigger on the length of the clock.
Step S21: logical synthesis (logic synthesis). Specifically, the RTL level circuit description file obtained in the RTL design input step is converted into a gate level netlist consisting of specific logic units, wherein the conversion process is determined by the first process library file.
Wherein, step S21 uses the description of the dual-edge dynamic trigger in the RTL level circuit description file to replace the single-edge trigger uniformly. The first process library file is converted to obtain a first gate-level netlist file, and the double-edge dynamic trigger can be integrated into a traditional digital integrated circuit design under the condition that the traditional logic synthesis tool does not support the double-edge dynamic trigger.
Step S22: and (5) form verification. That is, it is statically determined whether the first gate-level netlist file is functionally consistent with the RTL-level circuit description file according to the circuit structure.
In step S21 and step S22, the trigger characteristic of the related double-edge dynamic trigger is a single-edge trigger, and corresponds to the first process library file triggered by the rising edge.
Step S23: and laying out the wiring. In this embodiment, the layout and the wiring are performed simultaneously according to the first process library file and the second process library file to obtain the digital layout and the second gate-level netlist corresponding to the digital layout one by one, where the second gate-level netlist is consistent with the logic function of the first gate-level netlist file obtained in step S21, but the driving capability and the clock distribution of the second gate-level netlist are matched with the digital layout, and thus have a certain difference with the driving capability and the clock distribution in the first gate-level netlist file.
Step S24: and (5) physical verification. The method comprises the steps of design rule checking, netlist output of a layout, electrical rule checking, parasitic parameter extraction, circuit diagram and layout comparison and the like so as to verify the effectiveness of the generated digital layout.
Step S25: and (6) timing sequence checking. In this embodiment, the first process library file, the second process library file, the third process library file and the fourth process library file are used simultaneously for performing the timing check, that is, the large library and the small library on the rising edge and the large library and the small library on the falling edge are used simultaneously for performing the timing check, so that the verification reliability of the timing convergence can be improved.
After the physical verification and the time sequence inspection are qualified, the corresponding design is finished, and the chip can be subjected to tape-out.
Step S30: and (5) RTL function simulation. Namely, the function simulation is performed on the RTL level circuit description file obtained in step S20 to test whether the function is consistent with the design requirement. RTL Function Simulation is also called Function Simulation, and a simulator simulates circuit behaviors through interpretation of an RTL description file, and usually has no timing information or user-defined delay information.
Step S31: netlist function Simulation, also known as Pre-Layout Simulation, usually has no timing information or simply defines the delay time as a unit of time. Performing netlist function simulation on the first gate-level netlist obtained in the step S21, and verifying the correctness of the netlist function. In this embodiment, the netlist functional simulation uses the simulation library of the dual-edge dynamic trigger functional model obtained in step S13, and the clock uses the functional clock of the dual-edge dynamic trigger, i.e. the clock period of the clock signal (consistent with the clock signal CP shown in fig. 2) is twice the unit length of the data.
Step S32: netlist timing Simulation, also known as Post-Layout Simulation. Namely, the second gate-level netlist obtained in step S23 is simulated, and the netlist timing simulation adds timing information corresponding to the second gate-level netlist to determine whether the timing thereof is consistent with the design requirement. In the present embodiment, the netlist timing simulation uses the simulation library of the dual-edge dynamic flip-flop functional model obtained in step S13, and the clock uses the functional clock of the dual-edge dynamic flip-flop, i.e. the clock period of the clock signal (consistent with the clock signal CP shown in fig. 2) is twice the unit length of the data.
In the steps of logic synthesis, form verification and layout wiring, the trigger mode of the correspondingly used double-edge dynamic trigger is single-edge trigger, and the clock period of the corresponding clock signal is consistent with the unit length of data, namely the data trigger frequency of the single-edge trigger is the same as the data trigger frequency of the double-edge dynamic trigger.
In this embodiment, the dual-edge dynamic flip-flop is a dynamic dual-edge dynamic flip-flop, and the dynamic flip-flop has a small number of transistors and low power consumption, and a combination design can effectively reduce timing deviation between individuals, and can conveniently implement timing refresh according to a clock triggered by the dual-edge, and the dual-edge trigger can reduce clock frequency, thereby effectively reducing power consumption of a data path and an area of a designed chip while ensuring data timing refresh.
The design method of the digital integrated circuit collects the rising edge time sequence characteristics and the falling edge time sequence characteristics of the double-edge dynamic trigger to obtain a first library with larger time sequence requirements, unifies the first library into rising edge trigger types to obtain a first process library file, then executes design input, logic synthesis, form verification, layout wiring, time sequence check and physical verification of the traditional design process according to the function model of the double-edge dynamic trigger and the first process library file, and executes RTL (real time logging) function simulation, netlist function simulation and netlist time sequence simulation processes, integrates the double-edge dynamic trigger into the design of the digital integrated circuit, manufactures the first process library file according to the time sequence characteristics with larger time sequence requirements in the rising edge time sequence characteristics and the falling edge time sequence characteristics, executes the traditional design process according to the first process library file, guarantees the reliability of the designed circuit, and simplifies the design of the double-edge dynamic trigger on the digital integrated circuit The integration in the meter provides convenience for the application of the double-edge dynamic trigger in the digital integrated circuit, and reduces the overall power consumption of the digital integrated circuit system obtained by design.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (7)
1. A method of designing a digital integrated circuit, comprising:
respectively extracting the characteristics of the rising edge and the falling edge of the double-edge dynamic trigger to obtain a first library and a second library, wherein the time sequence characteristic parameter of the first library is greater than that of the second library;
modifying the first library into a rising edge trigger type to obtain a first process library file;
adding a double-edge trigger characteristic to a double-edge dynamic trigger of the simulation library to obtain a double-edge dynamic trigger functional model with the double-edge trigger characteristic;
sequentially performing design input, logic synthesis, formal verification, layout and wiring, timing inspection, and physical verification to complete design according to the double-edge dynamic trigger function model and the first process library file,
performing RTL function simulation according to the RTL level circuit description file obtained in the design input step;
performing netlist functional simulation according to the first gate-level netlist obtained in the logic synthesis step;
and performing netlist time sequence simulation according to the second gate-level netlist and the digital layout obtained in the step of laying out and wiring.
2. The method of claim 1, wherein the step of separately extracting the characteristics of the rising edge and the falling edge of the dual-edge dynamic flip-flop comprises separately extracting the timing and the power consumption of the rising edge and the falling edge of the dual-edge dynamic flip-flop.
3. The method of claim 1, further comprising:
modifying the second library to a rising edge trigger type to obtain a second process library file,
modifying both the first library and the second library to be of a falling edge trigger type to obtain a third process library file and a fourth process library file respectively,
and the time sequence checking step is used for simultaneously checking the time sequence according to the first process library file, the second process library file, the third process library file and the fourth process library file.
4. The method of claim 1, wherein the step of designing the digital integrated circuit,
in the steps of logic synthesis, form verification and layout wiring, the corresponding double-edge dynamic trigger of the double-edge dynamic trigger function model is used as a single-edge trigger, and the data trigger frequency is the same as that of the double-edge dynamic trigger.
5. The method of claim 1, wherein the step of designing the digital integrated circuit,
and performing netlist function simulation according to the first gate-level netlist obtained in the logic synthesis step, and performing netlist timing sequence simulation according to the second gate-level netlist and the digital layout obtained in the layout and wiring step, wherein the double-edge dynamic trigger of the corresponding double-edge dynamic trigger function model is a double-edge dynamic trigger behavior.
6. The method of claim 1, further comprising:
modifying the second library to a rising edge trigger type to obtain a second process library file,
and in the wiring step, automatic wiring and layout processes are carried out simultaneously according to the first process library file and the second process library file.
7. The method of claim 1, wherein the step of adding the dual edge trigger feature to the dual edge dynamic trigger of the emulation library further comprises performing a timing check on a maximum time of the clock according to a requirement of the dual edge dynamic trigger on a length of the clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111004448.7A CN113723045A (en) | 2021-08-30 | 2021-08-30 | Design method of digital integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111004448.7A CN113723045A (en) | 2021-08-30 | 2021-08-30 | Design method of digital integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113723045A true CN113723045A (en) | 2021-11-30 |
Family
ID=78679098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111004448.7A Pending CN113723045A (en) | 2021-08-30 | 2021-08-30 | Design method of digital integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113723045A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023245719A1 (en) * | 2022-06-22 | 2023-12-28 | 长鑫存储技术有限公司 | Performance check method for timing logic element, and device |
| WO2024000730A1 (en) * | 2022-06-30 | 2024-01-04 | 长鑫存储技术有限公司 | Inspection method and apparatus for data processing circuit, and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110133806A1 (en) * | 2009-12-03 | 2011-06-09 | Cadence Design Systems, Inc. | Integrated clock gating cell for circuits with double edge triggered flip-flops |
| JP2012243137A (en) * | 2011-05-20 | 2012-12-10 | Nec Corp | Cad system for logical integrated circuit and design method for spintronics logical integrated circuit |
| CN102831272A (en) * | 2012-08-30 | 2012-12-19 | 锐迪科科技有限公司 | DFT (Design for Testability) method for double-edge trigger |
-
2021
- 2021-08-30 CN CN202111004448.7A patent/CN113723045A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110133806A1 (en) * | 2009-12-03 | 2011-06-09 | Cadence Design Systems, Inc. | Integrated clock gating cell for circuits with double edge triggered flip-flops |
| JP2012243137A (en) * | 2011-05-20 | 2012-12-10 | Nec Corp | Cad system for logical integrated circuit and design method for spintronics logical integrated circuit |
| CN102831272A (en) * | 2012-08-30 | 2012-12-19 | 锐迪科科技有限公司 | DFT (Design for Testability) method for double-edge trigger |
Non-Patent Citations (1)
| Title |
|---|
| 章专;周威;: "双边沿动态触发器的设计及其应用", 浙江大学学报(理学版), no. 02, 25 March 2007 (2007-03-25), pages 67 - 70 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023245719A1 (en) * | 2022-06-22 | 2023-12-28 | 长鑫存储技术有限公司 | Performance check method for timing logic element, and device |
| WO2024000730A1 (en) * | 2022-06-30 | 2024-01-04 | 长鑫存储技术有限公司 | Inspection method and apparatus for data processing circuit, and electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108830008B (en) | Test method and test system for full model of standard cell library | |
| US6499131B1 (en) | Method for verification of crosstalk noise in a CMOS design | |
| US6378109B1 (en) | Method of simulation for gate oxide integrity check on an entire IC | |
| US6278964B1 (en) | Hot carrier effect simulation for integrated circuits | |
| US20090030665A1 (en) | Automatic, Hierarchy-Independent Partitioning Method For Transistor-Level Circuit Simulation | |
| US7139988B2 (en) | Modeling metastability in circuit design | |
| US20100017187A1 (en) | Random initialization of latches in an integrated circuit design for simulation | |
| CN113723045A (en) | Design method of digital integrated circuit | |
| US9563734B2 (en) | Characterizing cell using input waveform generation considering different circuit topologies | |
| Boliolo et al. | Gate-level power and current simulation of CMOS integrated circuits | |
| US7254793B2 (en) | Latch modeling technique for formal verification | |
| CN111581899A (en) | Generation method of yield parameter file and gate-level netlist and development process of chip | |
| CN109753675B (en) | Logic gate false signal modeling method | |
| US8893068B1 (en) | Techniques to generate a more accurate simulation model | |
| US20080141200A1 (en) | Methods and apparatuses for timing analysis of electronic circuits | |
| Srivastava et al. | Interdependent latch setup/hold time characterization via Euler-Newton curve tracing on state-transition equations | |
| US6249899B1 (en) | System and method for detecting pass FETs | |
| WO2023245719A1 (en) | Performance check method for timing logic element, and device | |
| US20220327269A1 (en) | Computing device and method for detecting clock domain crossing violation in design of memory device | |
| CN116611386A (en) | Transforming local threading resistance into global distribution resistance | |
| US20030084410A1 (en) | SPICE to Verilog netlist translator | |
| CN114371387A (en) | Method, system, device, storage medium and program product for testing signal of chip | |
| US11017138B2 (en) | Timing analysis for parallel multi-state driver circuits | |
| US6718522B1 (en) | Electrical rules checker system and method using tri-state logic for electrical rule checks | |
| US20170024504A1 (en) | Logical to Multi-Variable-Record Connect Element to Interface Logical Signals Between Analog and Digital Simulations |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20220223 Address after: 100015 b3005, 3rd floor, building 21, 2 Wanhong West Street, xibajianfang, dongzhimenwai, Chaoyang District, Beijing Applicant after: Haojun Technology (Beijing) Co.,Ltd. Address before: 215211 east side of FenHu Avenue, Lili Town, Wujiang District, Suzhou City, Jiangsu Province Applicant before: Suzhou Haojun Technology Co.,Ltd. |
|
| TA01 | Transfer of patent application right |