CN101778049A - Router and transmission method thereof on packet-circuit switching chip - Google Patents
Router and transmission method thereof on packet-circuit switching chip Download PDFInfo
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Abstract
The invention discloses a router and a transmission method thereof on a packet-circuit switching chip forming networks on chips. An input state device in the router controls the work state of an input channel and transmits received requisite signals to a priority encoder; the priority encoder encodes the request signals according to the set fixed priority and transforms input target node address signals to route direction signals by an address decoder to be output; an arbiter receives decoding results of the address decoder, outputs interconnected signals of an input port and an output port and occupation signals of the input port according the sequence of the fixed priority and the occupation condition of the ports until selecting a proper route to reach the target node; and a crossbar switch receives the interconnected signals output by the arbiter and realizes the correct interconnection between the input port and the output port. The invention has the advantages of little resource consumption and small transmission time delay. The invention is suitable for forming networks on chips with high performance, and can be applied to complicated systems on chips adopting on-chip network structure.
Description
Technical field
The present invention relates to router on a kind of bag-circuit switching chip that is applied to network-on-chip, router and transmission method thereof on specifically a kind of low consumption of resources that constitutes network-on-chip, the high-performance bag-circuit switching chip.
Background technology
Network-on-chip (NoC) by resource node (Resource), router (Router), passage (Channel) and network interface (Network Interface NI) forms, as shown in Figure 1:
11 is resource node: the node of carrying out calculating and store tasks.
12 are router: be also referred to as switching node or communication node, the executive communication task.
13 for passage: refer between resource node and the switching node, the line (E among Fig. 1, W, N, S and L) between switching node and the switching node.
14 are network interface: refer to the interface between resource node and the switching node, be divided in the resource node usually.Having only the resource node that has been equipped with network interface just can be connected on the network communicates with other resource nodes.
The most outstanding advantage of NoC is extensibility and reusability.NoC adopts distributed topological structure, and resource node and switching node are separate, and resource node is by a standard interface access network (linking to each other with switching node).That is to say, if resource node possess network interface just can be on network any one switching point access network, and each switching node all is identical.The architectural feature of this regularization of NoC makes the shared bandwidth of resource can not descend along with extension of network on the one hand; On the other hand, make IP reuse and reuse and all become possibility with the network architecture.Just because of this flexibility, all significantly reduced based on appear on the market time and R﹠D costs of the complication system chip of NoC.
In NoC design, the quality of router design will directly influence the performance of whole NoC system on the sheet, so particularly important.The packet switch router is a topmost router type in the research at present, and its function and structure are the simplification of router in the macro network.The packet switch router generally uses buffer that packet is temporarily stored, and the size and the network performance of buffer are closely related, so the area of packet switch router is bigger usually.The transfer of data time-delay of packet switch router is relevant with network condition, and its time-delay long usually (tens of to the thousands of cycles, the time-delay of the ideal of each router is between four to seven cycles) is difficult for satisfying the system real time requirement.
Along with the increase of integrated scale, router will be present among the NoC in a large number on the sheet, therefore require its area less, and in order to obtain high-performance, router must have less and foreseeable communication time-delay on the bag-circuit switching chip simultaneously.
Summary of the invention
For area and the performance requirement that satisfies network-on-chip, the purpose of this invention is to provide router and transmission method thereof on a kind of bag-circuit switching chip that constitutes network-on-chip, this router resource consumption is low, performance is high, can satisfy the area and the performance requirement of network-on-chip.
Purpose of the present invention is achieved through the following technical solutions:
Router on a kind of bag-circuit switching chip, it is characterized in that: this router comprises input state machine, output state machine, priority encoder, address decoder, moderator and cross bar switch, the input state machine is controlled the operating state of input channel, and sends the request signal that receives to priority encoder; Priority encoder is encoded to request signal according to the fixed priority of setting, and is the output of route direction signal by address decoder with the destination node address signal transition of input; Moderator is accepted the decoded result of address decoder, takies situation according to fixed priority order and port, and I/O mouth and output port interconnect signal and output port Seize ACK message are up to selecting suitable path to arrive destination node; Cross bar switch receives the interconnect signal of moderator output, realizes the correct interconnection between input, the output port.
Among the present invention, the input state machine comprises five operating states: idle, request, half locks, locks and failure; The input state machine receives request package at Idle state, and enters solicited status; If this route requests is authorized, then the input state machine enters half lock-out state, if this route requests is out of court, then the input state machine enters the routing failure state; The input state machine becomes function signal if receive link establishment when half lock-out state, then the input state machine enters lock-out state, if receive the link establishment failure signal, then the input state machine enters the routing failure state.
The priority orders of each input channel that priority encoder is set is: this locality＞east＞south＞west＞north.
Output state machine has free time, two operating states of locking, and idle expression output channel is current available, and locking expression output channel is occupied; When a control signal of source node is 0 or reset signal when effective, output state machine enters Idle state; Output state machine is when Idle state, if this channel transmission data of arbiter grants, then output state machine enters lock-out state, discharges this passage up to moderator, and output state machine is got back to Idle state.
The input channel quantity of described input state machine be one group several; The output channel quantity of output state machine also be one group several.
The transmission method of router on a kind of bag-circuit switching chip is characterized in that this transmission course is divided into three phases: link establishment phase, data transfer phase and link discharge the stage.
Link establishment phase, router is at first stored request package, carries out precedence level code, address decoder, arbitration then, request package is forwarded to next router again, in case link establishment success, this link can not be used by other routers on the network with regard to becoming special circuit.
Data transfer phase, router do not carry out any processing to packet, directly packet are sent to next router through a level production line, and data only are a clock cycle by the time-delay of each router.
Link discharges the stage, after transfer of data is finished, circuit is become idle condition by special use, can use for all the other routers.
In bag-circuit switching, have only the routing delay when setting up link relevant with network condition, in case and after the link establishment, transfer of data does not just rely on network condition, the data communication time-delay is very little and measurable, and this makes, and bag-circuit switching can be satisfied in a large number, the hard real-time requirement of continuous data transmission; On the area because each input of router on the bag-circuit switching chip (or output) passage only need be stored a packet, so its area is less.Router realizes that simply resource consumption is few on bag-circuit switching chip disclosed by the invention, and transmission delay is little, is applicable to constitute the high-performance network-on-chip, can be used to adopt the complicated SOC (system on a chip) of network-on-chip structure.
Description of drawings
Fig. 1 is the NoC structural representation;
Fig. 2 is a structural representation of the present invention;
Fig. 3 is an input state machine state transition graph among the present invention;
Fig. 4 is a medium priority encoder encodes schematic diagram of the present invention;
Fig. 5 is a dynamic XY routing algorithm schematic diagram among the present invention;
Fig. 6 is an address decoder principle schematic among the present invention;
Fig. 7 is an output state machine state transition graph among the present invention;
Fig. 8 is the link establishment schematic flow sheet;
Fig. 9 is a path schematic diagram among the present invention;
Figure 10 is an interface schematic diagram of the present invention;
Figure 11 is a data packet format schematic diagram among the present invention;
Figure 12 is the hardware configuration schematic diagram that adopts two-dimensional grid of the present invention (3 * 3) NoC system;
Embodiment
Router on a kind of bag-circuit switching chip, as shown in Figure 2.This router comprises input state machine 1, output state machine 2, priority encoder 3, address decoder 4, moderator 5 and cross bar switch 6, and input state machine 1 is controlled the operating state of input channel, and sends the request signal that receives to priority encoder 3; Priority encoder 3 is encoded to request signal according to the fixed priority of setting, and is the output of route direction signal by address decoder 4 with the destination node address signal transition of input; Moderator 5 is accepted the decoded result of address decoder 4, takies situation according to fixed priority order and port, and I/O mouth and output port interconnect signal and output port Seize ACK message are up to selecting suitable path to arrive destination node; Cross bar switch 6 receives the interconnect signal of moderator 5 outputs, realizes the correct interconnection between input, the output port.
The realization of this router is easy to upgrading, and by the extra input of exampleization, output state machine, the input of router, output port can increase easily, and the resource node that is connected to router can increase easily.Owing to once only handle a request package, address decoder does not change with the resource node number is different.Simultaneously, use parameterized method for designing, priority encoder, moderator and cross bar switch also can be realized the relevant parameters configuration.
Each composition module of router is as follows on the bag-circuit switching chip.
The function of input state machine is the operating state of control input channel.The input state machine has five operating states: idle (IDLE), request (REQ), half locking (PRELOCK), locking (LOCK) and failure (FAIL), its state exchange schematic diagram as shown in Figure 3.
When the control signal (Stb) of source node is 0 or reset signal when effective, the input state machine enters Idle state.The input state machine receives request package at Idle state, and enters solicited status; If this route requests authorized (Grant), state machine enters half lock-out state, if this route requests (Deny) out of court, state machine enters the routing failure state.At the routing failure state, state machine will be from the unconditional rebound Idle state of status of fail, and upstream nodes sends routing failure signal (nAck), and source node is changed to 0 with source node control signal (Stb) after receiving the routing failure signal, the cancellation request for building link.State machine becomes function signal (Ack) if receive link establishment when half lock-out state, state machine enters lock-out state; If receive link establishment failure signal (nAck), state machine enters the routing failure state.After the input state machine is locked, but just efficient transfer data bag, and this moment, the Fwd signal was corresponding with packet Data, represent that when the Fwd signal is 1 packet is effective, otherwise packet was invalid.State machine is got back to Idle state after lock-out state is received link cancel message (Cancel).
The route utensil has a plurality of input channels on the bag-circuit switching chip, and has only a route path.Five input channels of router are endowed fixed priority, and when a plurality of input channels were sent route requests simultaneously, priority encoder was encoded to request signal according to fixed priority.In the router, the priority orders of each input channel is on bag-circuit switching chip: (L＞E＞S＞W＞N), promptly priority orders is followed successively by: this locality, east, south, west, north in this locality＞east＞south＞west＞north.Fig. 4 is the coding schematic diagram of priority encoder.
Router adopts dynamic XY routing algorithm on the bag-circuit switching chip.So-called dynamically XY route is exactly that request package is earlier along the directions X route, when the directions X route takes place to block, promptly send route requests to the Y direction, if obtaining replying, request transmits request package to this direction, otherwise upstream nodes is returned the routing failure signal, and the schematic diagram of this dynamic XY routing algorithm as shown in Figure 5.Regulation does not allow data to the direction motion away from destination node, so dynamically the XY route does not have deadlock simultaneously.
The input of address decoder is a destination node address, and output is the route direction signal.According to dynamic XY routing algorithm, address decoder makes a choice to L, E, S, W and five directions of N by comparing destination address and local address, and the address decoder principle schematic as shown in Figure 6.Wherein, Xd, Yd represent X, the Y direction address of destination node respectively; X, Y represent X, the Y direction address of this node respectively; ReqL, reqE, reqS, reqW, reqN represent route direction.For example, when destination address be (Xd, Yd)=(2,3), local address be (X, Y)=(1,1) time, reqL=1 ' b0, reqE=1 ' b1, reqS=1 ' b1, reqW=1 ' b0, reqN=1 ' b0, these possible route direction are all given moderator and are arbitrated, moderator will attempt setting up a circuit, point in this both direction.
The decoded result of moderator module receiver address decoder is according to fixed priority order (L＞E＞S＞W＞N) take situation, I/O mouth and output port interconnect signal and output port Seize ACK message with port.At a time, an output port can only link to each other with an input port, and after data transmission end output port was released, other input eloquence can be selected this output port.If the output port of certain input port all possible options is all occupied, route requests signal (Deny) is rejected in moderator output, the input state machine enters the routing failure state, and upstream nodes or network interface send routing failure signal (nAck), discharges the link of having set up; If it is occupied that a certain output port that may select of this port does not have, this output port is selected, moderator output authorization signal (Grant), by that analogy, up to selecting suitable path to arrive destination node.
Cross bar switch receives the interconnect signal of moderator output, realizes the correct interconnection between input, the output port.At data transfer phase, the data-signal of input port directly passes to next node by data path, and without the route path, data path only comprises a level production line, thereby the time delays of data-signal by a router only is a clock cycle.When destination node discharged link, the annexation of respective input mouth and output port was undone in the data path.
The function of output state machine is the operating state of control output channel.Output state machine only has two operating states: idle (IDLE), locking (LOCK), and the former represents that output channel is current available, and the latter represents that output channel is occupied, and its state exchange schematic diagram is as shown in Figure 7.When the Stb signal is 0 or reset signal when effective, output state machine enters Idle state.Output state machine is when Idle state, if this channel transmission data of arbiter grants (Occupied), state machine enters lock-out state.Discharge this passage up to moderator, state machine is got back to Idle state.
The transmission course of router is divided into three phases on the bag-circuit switching chip: link establishment phase, data transfer phase and link discharge the stage.
Link establishment phase, router is at first stored request package, carries out precedence level code, address decoder, arbitration then, request package is forwarded to next router again, in case link establishment success, this link can not be used by other routers on the network with regard to becoming special circuit.
Data transfer phase, router do not carry out any processing to packet, directly packet are sent to next router through a level production line, and data only are a clock cycle by the time-delay of each router.
Link discharges the stage, after transfer of data is finished, circuit is become idle condition by special use, can use for all the other routers.
In the router, the foundation of link is finished by sending request package on bag-circuit switching chip, and data communication then adopts circuit form.Fig. 8 has shown the flow process of link establishment.
Shown in Fig. 8 (a), once successful transmission comprises 5 stages: (1) source node sends route requests with the form of request package to network, and when this request package was passed through network, link was temporarily locked, and therefore can not be used by other transmission courses; (2) when request package arrived the destination, an Ack signal was passed back along link, and temporary transient simultaneously locking is set as permanent locking (only depending on current Transmission Time Interval locking time); (3) when Ack turns back to source node, the beginning secured transmission of payload data; (4) after transfer of data is finished, source node sends end packet; (5) last, after destination node was received end packet, destination node was sent the Cancel signal, discharged the locking link.Summary is got up, and (1-2) is link establishment phase, and (3) are data transfer phase, (4-5) is that link discharges the stage.
If link gets clogged at a node place, block node and send the nAck signal to source node, and the cancellation established link; Source node will resend route requests after receiving the nAck signal, shown in Fig. 8 (b).
The functional characteristics of router determines it that two paths are arranged on the bag-circuit switching chip: route path and data path, as shown in Figure 9.A router has only a route path, and the route path is set up network link according to request package, routing delay relevant with network condition (the desirable routing delay of each router is seven cycles); Data path is controlled by the route path, is responsible for transfer of data, and delaying time less only is one-period, and a router can have a plurality of data paths.
The interface schematic diagram of router as shown in figure 10 on the bag-circuit switching chip.This router respectively has one group of input, output channel on 5 directions, corresponding respectively local (L), east (E), south (S), west (W), north (N) 5 directions.Wherein, Stb is a control signal, is to represent that the source node request for building link was effective at 1 o'clock, is to begin to discharge immediately the locking link from source node at 0 o'clock; Fwd is a transmission data effective marker signal; Data is 34 bit data bus, transmits with packet format shown in Figure 11; Ack is a positive response signal, is to represent the link establishment success at 1 o'clock; HAck is a Negative Acknowledgment signal, is to represent the link establishment failure at 1 o'clock, the cancellation established link; Cancel is a feedback signal, is to represent to receive end packet at 1 o'clock, and transfer of data is finished, and discharges the locking link.
Adopt the RTL model of router formation two-dimensional grid (3 * 3) NoC system on the bag-circuit switching chip, its hardware configuration schematic diagram as shown in figure 12.NoC is made up of router, link and local subsystem on the bag-circuit switching chip.Router is the server parts on the bag-circuit switching chip; Local subsystem comprises a data generator and a data receiver, is respectively applied for to send data and receive data.The function of this enforcement use-case is that local subsystem transmits and receive data by the NoC system.
Carry out functional simulation with Modelsim, obtain seven cycle/routers of link establishment time-delay average out to of this NoC system, wherein six cycles route path time-delay that is router, one-period is link establishment response (Ack) time-delay; The transfer of data time-delay is irrelevant with network condition, only is one-period/router.Data can obtain high efficiency of transmission by this NoC system.And the time-delay of the transfer of data of conventional bag switch router is relevant with network condition, its time-delay is long usually (tens of to the thousands of cycles, the ideal time-delay of each router is between four to seven cycles), therefore say that router has improved the performance of NoC system greatly on the bag-circuit switching chip.
Adopt SMIC 0.18 μ m standard cell lib to carry out logic synthesis, wrapped-circuit switching chip on the clock frequency of router be 500MHz, the throughput of each passage reaches 16Gbps.The resource consumption of each router is the 4.3K door.Compare the conventional bag switch router, the area of router reduces on the bag-circuit switching chip, and throughput improves more than the twice.
At different application, local subsystem can be to have processing unit or memory cell or the combination of the two, to support concrete application.In addition, because the link establishment time-delay of router is relevant with network condition on the bag-circuit switching chip, and the transfer of data time-delay has nothing to do with network condition and only is one-period, so router is more suitable in application in enormous quantities, the continuous data transmission on this bag-circuit switching chip.
The route utensil has low hardware resource consumption, high performance advantage on bag-circuit switching chip of the present invention, is applicable to consist of the high-performance network-on-chip, can be used for adopting the complicated SOC(system on a chip) of network-on-chip structure.
Claims (6)
1. router on the bag-circuit switching chip, it is characterized in that: this router comprises input state machine (1), output state machine (2), priority encoder (3), address decoder (4), moderator (5) and cross bar switch (6), input state machine (1) is controlled the operating state of input channel, and sends the request signal that receives to priority encoder (3); Priority encoder (3) is encoded to request signal according to the fixed priority of setting, and is that the route direction signal is exported by address decoder (4) with the destination node address signal transition of input; Moderator (5) is accepted the decoded result of address decoder (4), takies situation according to fixed priority order and port, and I/O mouth and output port interconnect signal and output port Seize ACK message are up to selecting suitable path to arrive destination node; Cross bar switch (6) receives the interconnect signal of moderator (5) output, realizes the correct interconnection between input, the output port.
2. router on bag-circuit switching chip according to claim 1 is characterized in that: input state machine (1) comprises five operating states: idle, request, half locks, locks and failure; Input state machine (1) receives request package at Idle state, and enters solicited status; If this route requests is authorized, then input state machine (1) enters half lock-out state, if this route requests is out of court, then input state machine (1) enters the routing failure state; Input state machine (1) becomes function signal if receive link establishment when half lock-out state, then input state machine (1) enters lock-out state, if receive the link establishment failure signal, then input state machine (1) enters the routing failure state.
3. router on bag-circuit switching chip according to claim 1 is characterized in that: the priority orders of each input channel that priority encoder (3) is set is: this locality＞east＞south＞west＞north.
4. router on bag-circuit switching chip according to claim 1 is characterized in that: output state machine (2) has free time, two operating states of locking, and idle expression output channel is current available, and locking expression output channel is occupied; When a control signal of source node is 0 or reset signal when effective, output state machine (2) enters Idle state; Output state machine (2) is when Idle state, if moderator (5) is authorized this channel transmission data, then output state machine (2) enters lock-out state, discharges this passage up to moderator (5), and output state machine (2) is got back to Idle state.
5. router on bag-circuit switching chip according to claim 1 is characterized in that: the input channel quantity of described input state machine (1) is one group; The output channel quantity of output state machine (2) is one group.
6. the transmission method of router on the described bag-circuit switching chip of claim 1 is characterized in that this transmission course is divided into three phases: link establishment phase, and data transfer phase and link discharge the stage;
Link establishment phase, router is at first stored request package, carries out precedence level code, address decoder, arbitration then, request package is forwarded to next router again, in case link establishment success, this link can not be used by other routers on the network with regard to becoming special circuit;
Data transfer phase, router do not carry out any processing to packet, directly packet are sent to next router through a level production line, and data only are a clock cycle by the time-delay of each router;
Link discharges the stage, after transfer of data is finished, circuit is become idle condition by special use, can use for all the other routers.
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| US11321087B2 (en) | 2018-08-29 | 2022-05-03 | Cerebras Systems Inc. | ISA enhancements for accelerated deep learning |
| US11328207B2 (en) | 2018-08-28 | 2022-05-10 | Cerebras Systems Inc. | Scaled compute fabric for accelerated deep learning |
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| US11734224B2 (en) | 2020-09-28 | 2023-08-22 | Tenstorrent Inc. | Overlay layer hardware unit for network of processor cores |
| CN117714388A (en) * | 2024-02-04 | 2024-03-15 | 极芯通讯技术(安吉)有限公司 | Hybrid circuit transmission and packet transmission method and system |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101383712A (en) * | 2008-10-16 | 2009-03-11 | 电子科技大学 | Routing node microstructure for on-chip network |
| KR20090092421A (en) * | 2008-02-27 | 2009-09-01 | 한국과학기술원 | Network on chip router by using systemc and its routing method |
| TW201001990A (en) * | 2008-06-20 | 2010-01-01 | Yuan-Long Jeang | A hierarchical mesh-tree architecture for network-on-a-chip and method thereof for transmitting packets |
-
2010
- 2010-03-04 CN CN201010118591A patent/CN101778049A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090092421A (en) * | 2008-02-27 | 2009-09-01 | 한국과학기술원 | Network on chip router by using systemc and its routing method |
| TW201001990A (en) * | 2008-06-20 | 2010-01-01 | Yuan-Long Jeang | A hierarchical mesh-tree architecture for network-on-a-chip and method thereof for transmitting packets |
| CN101383712A (en) * | 2008-10-16 | 2009-03-11 | 电子科技大学 | Routing node microstructure for on-chip network |
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