CN218273390U - SOC prototype verification device based on FPGA - Google Patents
SOC prototype verification device based on FPGA Download PDFInfo
- Publication number
- CN218273390U CN218273390U CN202222869662.5U CN202222869662U CN218273390U CN 218273390 U CN218273390 U CN 218273390U CN 202222869662 U CN202222869662 U CN 202222869662U CN 218273390 U CN218273390 U CN 218273390U
- Authority
- CN
- China
- Prior art keywords
- interface
- fpga chip
- fpga
- soc
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012795 verification Methods 0.000 title claims abstract description 39
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 238000004891 communication Methods 0.000 claims description 6
- 238000012360 testing method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000007781 pre-processing Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The utility model discloses a SOC prototype verification device based on FPGA, be used for improving the commonality of device, wherein, the device includes first FPGA chip, second FPGA chip, power module and clock module, first FPGA chip is provided with the interface of being connected with the equipment of different grade type, and first FPGA chip respectively with the host computer, second FPGA chip, power module and clock module signal connection, second FPGA chip respectively with power module and clock module signal connection, when verifying light-weight SOC, adopt first FPGA chip to verify, when verifying complicated level SOC, adopt first FPGA chip and second FPGA chip to verify. Because the device comprises two FPGA chips, the first FPGA chip comprises an interface which can be connected with different types of equipment, and different FPGA chips are adopted for verification aiming at the light SOC and the complex SOC, the device can perform prototype verification on different SOCs, and the universality of the device is enhanced.
Description
Technical Field
The utility model relates to an integrated circuit technical field, in particular to SOC prototype verification device based on FPGA.
Background
With the rapid development of the semiconductor industry, a multi-functional, small-sized, low-power-consumption, and low-cost System On Chip (SOC) is applied in various fields, and the design scale of the SOC is getting larger and larger. The SOC is fully verified before the flow sheet, so that the design error can be effectively reduced, the research and development period of the chip is shortened, and the cost is reduced.
At present, when prototype verification is carried out on the SOC, different prototype verification devices can be made for the SOCs with different magnitudes, and the universality is poor.
SUMMERY OF THE UTILITY MODEL
The utility model provides a SOC prototype verification device based on Field Programmable Gate Array (Field Programmable Gate Array, FPGA) for solve the poor problem of SOC prototype verification device commonality that exists among the prior art.
The utility model provides a SOC prototype verification device based on FPGA, include: the device comprises a first FPGA chip, a second FPGA chip, a power supply module and a clock module;
the first FPGA chip is provided with interfaces connected with different types of equipment, and is respectively in signal connection with the upper computer, the second FPGA chip, the power supply module and the clock module;
the second FPGA chip is respectively in signal connection with the power module and the clock module;
and if the SOC to be tested is a light-weight SOC, verifying by using the first FPGA chip, and if the SOC to be tested is a complex-level SOC, verifying by using the first FPGA chip and the second FPGA chip.
In one implementation, the interface to connect with different types of devices includes:
a first interface connected with the storage device;
the second interface is connected with the communication equipment;
a third interface connected with the data conversion device;
and a fourth interface connected with the dedicated device.
In one implementation, the first FPGA chip is a medium-scale FPGA chip; the second FPGA chip is a large-scale FPGA chip.
In one implementation, the first FPGA chip and the second FPGA chip are connected by a high-speed GTX interface signal.
In one implementation, the first interface includes some or all of the following:
a UART interface;
an I2C interface;
an SPI interface;
an SDIO interface;
and a GPIO interface.
In one implementation, the second interface includes a JTAG interface and/or an IIS1 interface.
In one implementation, the third interface includes an RBDP and/or JESD204B interface.
In one implementation, the third interface includes two RBDP and two JESD204B interfaces.
In one implementation, the fourth interface includes some or all of the following:
an I2C interface;
an SPI interface;
a GPIO interface;
a USIM interface;
a UART interface;
an SDIO interface;
a USB interface;
a GMAC interface;
a GTX interface.
In one implementation, the apparatus further includes a test chip in signal connection with the first FPGA chip.
In one implementation, the test chip includes an ARM chip or a DSP chip.
The utility model discloses beneficial effect as follows:
the embodiment of the utility model provides a SOC prototype verification device, including first FPGA chip, second FPGA chip, power module and clock module, wherein, first FPGA chip is provided with the interface of being connected with the equipment of different grade type, and first FPGA chip respectively with the host computer, second FPGA chip, power module and clock module signal connection, second FPGA chip respectively with power module and clock module signal connection, and, when verifying light level SOC, adopt first FPGA chip 11 to verify, when verifying complex level SOC, adopt first FPGA chip 11 and second FPGA chip 12 to verify. Because the SOC prototype verification device comprises two FPGA chips, the interface of the first FPGA chip can be connected with different types of equipment, and different FPGA chips are adopted for verification aiming at the light-weight SOC and the complex and SOC, the verification device can perform prototype verification on different SOCs, and the universality of the device is enhanced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive effort.
Fig. 1 is a schematic structural diagram of an SOC prototype verification apparatus based on FPGA according to the present invention;
fig. 2 is a schematic structural diagram of another SOC prototype verification apparatus based on FPGA according to the present invention;
fig. 3 is a schematic structural diagram of another SOC prototype verification apparatus based on FPGA according to the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings, and it is to be understood that the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Unless defined otherwise, technical or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the description herein do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely illustrative of the present invention. And like reference numerals refer to like or similar elements or elements having like or similar functions throughout.
In order to solve the poor problem of SOC prototype verification device commonality among the correlation technique, the utility model discloses a device is verified to SOC prototype based on FPGA, it is right below the utility model discloses a device is verified to SOC prototype based on FPGA carries out detailed description.
As shown in fig. 1, for the utility model discloses a SOC prototype verification device based on FPGA, include: the device comprises a first FPGA chip 11, a second FPGA chip 12, a power module 13 and a clock module 14;
the first FPGA chip 11 is provided with interfaces connected with different types of equipment, and the first FPGA chip 11 is respectively in signal connection with the upper computer, the second FPGA chip 12, the power module 13 and the clock module 14;
the second FPGA chip 12 is respectively in signal connection with the power module 13 and the clock module 14;
if the to-be-tested SOC is a lightweight SOC, the first FPGA chip 11 is used for verification, and if the to-be-tested SOC is a complex SOC, the first FPGA chip 11 and the second FPGA chip 12 are used for verification.
The embodiment of the utility model provides a SOC prototype verification device, including first FPGA chip 11, second FPGA chip 12, power module 13 and clock module 14, wherein, first FPGA chip 11 is provided with the interface of being connected with the equipment of different grade type, and first FPGA chip 11 respectively with the host computer, second FPGA chip 12, power module 13 and clock module 14 signal connection, second FPGA chip 12 respectively with power module 13 and clock module 14 signal connection, and, when verifying light-weight SOC, adopt first FPGA chip 11 to verify, when verifying complicated level SOC, adopt first FPGA chip 11 and second FPGA chip 12 to verify. Because the SOC prototype verification device comprises two FPGA chips, the interface of the first FPGA chip can be connected with different types of equipment, and different FPGA chips are adopted for verification aiming at the light-weight SOC and the complex SOC, the verification device can perform prototype verification on different SOCs, and the universality of the device is enhanced.
In addition, since the first FPGA chip 11 includes an interface for connecting a plurality of devices of different types, the sufficiency of verification can be improved.
The embodiment of the utility model provides an in, power module 13 can close or open the power of corresponding module according to SOC's low-power consumption strategy and requirement, can step up the reduction and verify the low-power function of chip, and clock management also can effectually carry out the directional pre-estimation of low-power function simultaneously.
In a specific implementation, as shown in fig. 1, the interfaces connected to the different types of devices may include a first interface 111 connected to the storage device, a second interface 112 connected to the communication device, a third interface 113 connected to the data conversion device, and a fourth interface 114 connected to the dedicated device.
In one or more embodiments, the first FPGA chip 11 may be a medium-scale FPGA chip, and the second FPGA chip 12 may be a large-scale FPGA chip, for example, the first FPGA chip 11 is an XC7VX690T chip, and the second FPGA chip 12 is an XCVU13P chip.
The first FPGA chip 11 is provided with interfaces for connecting different types of devices, and receives data through the interfaces for connecting different types of devices, so that data preprocessing at the digital front end is realized, and the second FPGA chip 12 can process data transmitted from the first FPGA chip 11 to the second FPGA chip 12.
In specific implementation, the first FPGA chip 11 may be used for prototype verification for a lightweight SOC, that is, only a medium-scale FPGA chip is used, and the first FPGA chip 11 and the second FPGA chip may be used for prototype verification for a complex-scale SOC, that is, the medium-scale FPGA chip and the large-scale FPGA chip are used, wherein the first FPGA chip 11 mainly implements data preprocessing at a digital front end, the first FPGA chip 11 transmits data to the second FPGA chip 12 through a high-speed GTX interface, and the second FPGA chip 12 processes received data.
The embodiment of the utility model provides a device both can carry out prototype verification to the SOC of lightweight, can also carry out prototype verification to the SOC of complicated level to can improve the commonality of device.
Specifically, as shown in fig. 2, the first FPGA chip 11 and the second FPGA chip 12 are in signal connection via a high-speed GTX interface, and the first FPGA chip 11 and the second FPGA chip 12 perform high-bandwidth data transmission via the high-speed GTX interface.
As can be seen from fig. 2, the first FPGA chip 11 and the second FPGA chip 12 may be connected through an IO interface signal in addition to the high-speed GTX interface signal, and the first FPGA chip 11 and the second FPGA chip 12 send signals such as an interrupt signal and a reset signal to each other through the IO interface.
In specific implementation, the first FPGA chip 11 and the second FPGA chip 12 both include a CLK terminal, the CLK terminal of the first FPGA chip 11 is connected to the CLK terminal of the second FPGA chip 12 and is connected to the clock module 14, and the clock module 14 sends a clock signal to the first FPGA chip 11 and the second FPGA chip 12, where the clock signal may be used as a synchronous clock signal.
As shown in fig. 3, for another SOC prototype verification device based on FPGA provided by the embodiment of the present invention, the device may further include a reset module 16, the reset module 16 is respectively connected to the first FPGA chip 11 and the second FPGA chip 12, and resets the first FPGA chip 11 and the second FPGA chip 12.
In a specific implementation, as shown in fig. 3, the storage device may include a first backup unit 16, a second backup unit 17, a third backup unit 18, a fourth backup unit 19, a sensor backup unit 20, a memory card 21, a NAND FLASH22, a NOR FLASH23, an external DDR24, and an EMMC37; the communication device may include a host computer and an audio device 25, the data conversion device may include a transceiver converter 26, such as transceiver 1 and transceiver2 in fig. 3, and the dedicated device may include a display unit (screen) 27, a status indication module 28, a SIM card 29, a bluetooth module 30, a beidou module 31, a sensor 32, a USB device 33, a WIFI module 34, an encryption module 35, and an ethernet module 36.
In particular implementations, the first interface 111 may include some or all of the following: a UART interface; an I2C interface; an SPI interface; an SDIO interface; and a GPIO interface.
The second interface 112 may include a JTAG interface and/or an IIS1 interface.
The third interface 113 may include an RBDP interface and/or a JESD204B interface.
The fourth interface 114 may include some or all of the following: an I2C interface; an SPI interface; a GPIO interface; a USIM interface; a UART interface; an SDIO interface; a USB interface; a GMAC interface; a GTX interface.
For example, as shown in fig. 3, a first backup unit 16 in the storage device is connected to 2 UART interfaces in a first FPGA chip, and a second backup unit 17 is connected to 2I 2C interfaces in the first FPGA chip; the third backup unit 18 is connected with 2 SPI interfaces in the first FPGA chip; the fourth backup unit 19 is connected with 8 GPIO interfaces in the first FPGA chip; the sensor backup unit 20 is connected with an I2C interface in the first FPGA chip; the memory card 21 is connected with 8 SDIO interfaces in the first FPGA chip; the NAND FLASH22 is connected with an SDIO interface in the first FPGA chip; the NOR FLASH23 is connected with an SDIO interface in the first FPGA chip; the external DDR24 is connected with an SDIO interface in the first FPGA chip; the EMMC37 is connected with an SDIO interface in the first FPGA chip.
An upper computer in the communication equipment is connected with a JTAG interface in the first FPGA chip; the audio device 25 is connected to the IIS interface in the first FPGA chip.
The transceiver converter 26 in the data conversion device is connected with an RBDP interface or a JESD204B interface in the first FPGA chip.
A display unit 27 in the special equipment is connected with an I2C interface or an SPI interface in the first FPGA chip; the state indicating module 28 is connected with a GPIO interface in the first FPGA chip; the SIM card 29 is connected with a USIM interface in the first FPGA chip; the Bluetooth module 30 is connected with a UART interface in the first FPGA chip; the Beidou module 31 is connected with a UART interface in the first FPGA chip; the sensor 32 is connected with an I2C interface in the first FPGA chip; the USB device 33 is connected with 4 USB interfaces in the first FPGA chip; the WIFI module 34 is connected with an SDIO interface in the first FPGA chip; the encryption module 35 is connected with an SDIO interface in the first FPGA chip; ethernet module 36 interfaces with the GMAC in the first FPGA chip.
In a particular implementation, the third interface 113 may include two RBDP interfaces and two JESD204B interfaces.
The embodiment of the utility model provides an in two RBDP interfaces and two JESD204B interfaces, 4 receive 4 digital analog conversion interfaces that send promptly, 4 receive 4 digital analog conversion interfaces that send and need not external expansion equipment just can high-efficiently verify partial MIMO physique communication chip, improve the commonality of device.
It should be noted that, in the embodiment of the present application, the interfaces that are arranged on the first FPGA chip and connected to different types of devices select an interface to be used according to the priority of the interface if there is a mutual exclusion condition between the interfaces.
For example, the I2C interface and the SPI interface in the first interface are both connected to the device, and the device connected to the I2C interface and the device connected to the SPI interface cannot operate simultaneously, and if the priority of the I2C interface is higher than the priority of the SPI interface, the device connected to the I2C interface may operate, and the device connected to the SPI interface may not operate.
As shown in fig. 3, the SOC prototype verification apparatus according to an embodiment of the present invention may further include a GTX interface connected to the extension platform 38.
The embodiment of the utility model provides a SDIO interface of being connected with extension platform 38 can expand the device to improve the device's commonality.
In one embodiment, the apparatus may further include a test chip, such as an ARM chip or a DSP chip, in signal connection with the first FPGA chip 11.
The embodiment of the utility model provides an in, SOC prototype verification device connects ARM chip or DSP chip through first FPGA chip 11 to can realize the processing to high bandwidth data, thereby can reduce cost, improve the commonality of device.
Various modifications and alterations of this invention may be made by those skilled in the art without departing from the spirit and scope of this invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (11)
1. An SOC prototype verification device based on FPGA is characterized by comprising: the device comprises a first FPGA chip, a second FPGA chip, a power supply module and a clock module;
the first FPGA chip is provided with interfaces connected with different types of equipment, and is respectively in signal connection with the upper computer, the second FPGA chip, the power supply module and the clock module;
the second FPGA chip is respectively in signal connection with the power module and the clock module;
if the SOC to be tested is a lightweight SOC, the first FPGA chip is adopted for verification, and if the SOC to be tested is a complex SOC, the first FPGA chip and the second FPGA chip are adopted for verification.
2. The apparatus of claim 1, wherein the interface to connect with different types of devices comprises:
a first interface connected with the storage device;
the second interface is connected with the communication equipment;
a third interface connected with the data conversion device;
and a fourth interface connected with the special equipment.
3. The apparatus of claim 1, wherein the first FPGA chip is a medium-scale FPGA chip; the second FPGA chip is a large-scale FPGA chip.
4. The apparatus of claim 1, wherein the first FPGA chip and the second FPGA chip are connected by high speed GTX interface signals.
5. The apparatus of claim 2, wherein the first interface comprises some or all of:
a UART interface;
an I2C interface;
an SPI interface;
an SDIO interface;
and a GPIO interface.
6. The apparatus of claim 2, wherein the second interface comprises a JTAG interface and/or an IIS1 interface.
7. The apparatus of claim 2, wherein the third interface comprises an RBDP and/or JESD204B interface.
8. The apparatus of claim 7, wherein the third interface comprises two RBDP and two JESD204B interfaces.
9. The apparatus of claim 2, wherein the fourth interface comprises some or all of:
an I2C interface;
an SPI interface;
a GPIO interface;
a USIM interface;
a UART interface;
an SDIO interface;
a USB interface;
a GMAC interface;
a GTX interface.
10. The apparatus of any one of claims 1-9, further comprising a test chip in signal connection with the first FPGA chip.
11. The apparatus of claim 10, wherein the test chip comprises an ARM chip or a DSP chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222869662.5U CN218273390U (en) | 2022-10-28 | 2022-10-28 | SOC prototype verification device based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222869662.5U CN218273390U (en) | 2022-10-28 | 2022-10-28 | SOC prototype verification device based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218273390U true CN218273390U (en) | 2023-01-10 |
Family
ID=84754720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222869662.5U Active CN218273390U (en) | 2022-10-28 | 2022-10-28 | SOC prototype verification device based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218273390U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115373925A (en) * | 2022-08-31 | 2022-11-22 | 西安微电子技术研究所 | Comprehensive test method, system and storage medium for heterogeneous integrated microsystem |
-
2022
- 2022-10-28 CN CN202222869662.5U patent/CN218273390U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115373925A (en) * | 2022-08-31 | 2022-11-22 | 西安微电子技术研究所 | Comprehensive test method, system and storage medium for heterogeneous integrated microsystem |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105051706B (en) | The equipment of operation for the low-power PHY with PCIE protocol stacks, method and system | |
| CN103714029A (en) | Novel two-line synchronous communication protocol and application | |
| CN218273390U (en) | SOC prototype verification device based on FPGA | |
| KR20130050383A (en) | Incorporating an independent logic block in a system-on-a-chip | |
| CN103200081A (en) | Heterogeneous network environment oriented Internet of things gateway development platform | |
| CN205229465U (en) | Baseband chip and multimode GNSS receiver of multimode GNSS receiver | |
| CN107255975B (en) | Device and method for realizing rapid loading of FPGA (field programmable Gate array) program by utilizing high-speed bus | |
| CN104050121A (en) | Double-receiving double-emitting programmable ARINC 429 communication interface chip | |
| CN215642673U (en) | DSP program dynamic loading equipment based on ZYNQ | |
| CN110399255A (en) | A kind of debugging system of FPGA system and FPGA system | |
| US20230102085A1 (en) | Electronic device and operation method of sleep mode thereof | |
| CN210864698U (en) | Signal processing board card based on VPX structure | |
| Wan et al. | Application and implementation of CAN bus technology in industry real-time data communication | |
| CN210895420U (en) | CPU low-speed interface function automatic checkout device based on FPGA | |
| CN204189089U (en) | A kind of server | |
| CN209842616U (en) | I2C/SPI configuration IP core based on FPGA | |
| CN206559350U (en) | 4G communication modules | |
| CN208691237U (en) | A kind of broadband numerical model analysis radio-frequency module | |
| CN203287889U (en) | Control device of SD/MMC card and IIC slave device | |
| CN212572589U (en) | High-instantaneity EtherCAT hardware main station system | |
| CN111258943A (en) | Circuit, mainboard and equipment of compatible android of single input and OPS equipment internet surfing | |
| CN202976319U (en) | Central processing unit (CPU) card and embedded secure access module (ESAM) communication multiplex circuit of three-phase fee control intelligent ammeter | |
| CN220604008U (en) | Communication interface conversion device | |
| CN211321382U (en) | Split type communication device | |
| CN216285611U (en) | Motor drive equipment test circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |