CN117553786A - Navigation device - Google Patents
Navigation device Download PDFInfo
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- CN117553786A CN117553786A CN202410011337.6A CN202410011337A CN117553786A CN 117553786 A CN117553786 A CN 117553786A CN 202410011337 A CN202410011337 A CN 202410011337A CN 117553786 A CN117553786 A CN 117553786A
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- circuit
- interface
- electrically connected
- navigator
- isolation
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- 238000004891 communication Methods 0.000 claims abstract description 28
- 230000003750 conditioning effect Effects 0.000 claims abstract description 20
- 238000002955 isolation Methods 0.000 claims description 100
- 238000006243 chemical reaction Methods 0.000 claims description 39
- 239000013307 optical fiber Substances 0.000 claims description 16
- 238000005259 measurement Methods 0.000 claims description 13
- 230000001052 transient effect Effects 0.000 claims description 13
- 238000007493 shaping process Methods 0.000 claims description 11
- 230000001629 suppression Effects 0.000 claims description 11
- 230000002708 enhancing effect Effects 0.000 claims description 2
- 230000003993 interaction Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 5
- 239000000835 fiber Substances 0.000 description 4
- 238000001914 filtration Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002452 interceptive effect Effects 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C21/00—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
- G01C21/10—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration
- G01C21/12—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning
- G01C21/16—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning by integrating acceleration or speed, i.e. inertial navigation
- G01C21/165—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning by integrating acceleration or speed, i.e. inertial navigation combined with non-inertial navigation instruments
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C21/00—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
- G01C21/005—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 with correlation of navigation data from several sources, e.g. map or contour matching
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/38—Determining a navigation solution using signals transmitted by a satellite radio beacon positioning system
- G01S19/39—Determining a navigation solution using signals transmitted by a satellite radio beacon positioning system the satellite radio beacon positioning system transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/42—Determining position
- G01S19/45—Determining position by combining measurements of signals from the satellite radio beacon positioning system with a supplementary measurement
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/38—Determining a navigation solution using signals transmitted by a satellite radio beacon positioning system
- G01S19/39—Determining a navigation solution using signals transmitted by a satellite radio beacon positioning system the satellite radio beacon positioning system transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/42—Determining position
- G01S19/45—Determining position by combining measurements of signals from the satellite radio beacon positioning system with a supplementary measurement
- G01S19/47—Determining position by combining measurements of signals from the satellite radio beacon positioning system with a supplementary measurement the supplementary measurement being an inertial measurement, e.g. tightly coupled inertial
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Computer Networks & Wireless Communication (AREA)
- Position Fixing By Use Of Radio Waves (AREA)
Abstract
The invention discloses a navigator, which relates to the technical field of navigation, and the technical scheme of the invention comprises a navigation position acquisition module, a first processing module, a second processing module and an interface conditioning module, wherein the interface conditioning module comprises an interface circuit, an FPGA circuit and an isolating circuit, the FPGA circuit is electrically connected with the interface circuit, the FPGA circuit is in communication connection with the first processing module, the second processing module, the navigation position acquisition module and an external interface through the interface circuit, the isolating circuit is electrically connected with the FPGA circuit, the first processing module is electrically connected with the second processing module, the processing and interaction structure of the navigator on various signals are optimized, the processing of the navigator on various signals is simpler and more convenient, the interface of the navigator is isolated through the isolating circuit, the influence of various interference signals is reduced, meanwhile, the internal circuit of the navigator can be protected, and the reliability of the navigator is improved.
Description
Technical Field
The invention relates to the technical field of navigation, in particular to a navigator.
Background
The navigator is a product of modern technology and is used for positioning, navigation and entertainment, and with the wide application of automobiles, ships, unmanned aerial vehicles and the like and the construction of roads, the inter-city economic traffic is more frequent, and the navigator plays an increasingly important role.
Because the navigator relates to the processing of various signals, and the interactive structure between various signals is complicated, the use requirement of users can not be met gradually by the existing navigator.
Disclosure of Invention
The invention mainly aims to provide a navigator, which aims to improve the reliability of the navigator.
In order to achieve the above object, the present invention provides a navigator, including a navigation position acquisition module;
the navigation position acquisition module comprises:
the odometer is used for acquiring a first navigation position signal of a target;
the inertial measurement device is used for acquiring a second navigation position signal of the target;
the satellite positioning system is used for acquiring a third navigation position signal of the target;
the navigator further includes:
a first processing module;
a second processing module;
an interface conditioning module, the interface conditioning module comprising:
an interface circuit;
the FPGA circuit is electrically connected with the interface circuit;
the FPGA circuit is used for establishing communication connection with the first processing module, the second processing module, the navigation position acquisition module and an external interface through the interface circuit;
the isolation circuit is electrically connected with the FPGA circuit; the isolation circuit is used for realizing electrical isolation of the FPGA circuit;
the first processing module is used for processing the first navigation position signal and the second navigation position signal transmitted by the interface conditioning module;
the second processing module is electrically connected with the first processing module;
the second processing module is used for processing the third navigation position signal transmitted by the interface conditioning module or processing the fourth navigation position signal transmitted by the first processing module and displaying the third navigation position signal and the fourth navigation position signal correspondingly.
Optionally, the interface circuit further comprises:
the two ends of the mileage counting interface circuit are respectively and electrically connected with the FPGA circuit and the mileage meter;
the mileage counting interface circuit is used for collecting a first navigation position signal of a target;
the isolation circuit further includes:
the first isolation circuit is electrically connected with the mileage counting interface circuit;
and the first isolation circuit is used for realizing electrical isolation between the FPGA circuit and the odometer.
Optionally, the first isolation circuit further includes:
the input end of the transient voltage suppression circuit is electrically connected with the mileage counting interface circuit;
the transient voltage suppression circuit is used for suppressing high spike pulses in the first navigation position signal;
the input end of the filter circuit is connected with the output end of the transient voltage suppression circuit and is used for carrying out filter processing on the first navigation position signal;
the input end of the clamping circuit is connected with the output end of the filter circuit;
the clamping circuit is used for clamping the voltage of the first navigation position signal;
the input end of the shaping circuit is connected with the output end of the clamp circuit;
the shaping circuit is used for enhancing the driving capability of the first navigation position signal.
Optionally, the interface circuit further comprises:
the first end of the time system interface circuit is electrically connected with the FPGA circuit, and the second end of the time system interface circuit is respectively connected with the inertial measurement equipment and the satellite positioning system in a communication way;
the time system interface circuit is used for acquiring a second navigation position signal and a third navigation position signal;
the isolation circuit further includes:
the second isolation circuit is electrically connected with the time system interface circuit;
the second isolation circuit is used for realizing electrical isolation between the FPGA circuit and the inertial measurement device and between the FPGA circuit and the satellite positioning system.
Optionally, the interface circuit further comprises:
the RS422 interface circuit is electrically connected with the FPGA circuit;
the RS422 interface circuit is used for enabling the FPGA circuit to realize RS422 communication with an external interface;
the isolation circuit includes:
the third isolation circuit is electrically connected with the RS422 interface circuit;
and the third isolation circuit is used for realizing electrical isolation between the FPGA circuit and an external interface.
Optionally, the interface circuit further comprises:
the CAN interface circuit is electrically connected with the FPGA circuit;
the CAN interface circuit is used for enabling the FPGA circuit to realize CAN communication with an external interface;
the isolation circuit further includes:
the fourth isolation circuit is electrically connected with the CAN interface circuit;
and the fourth isolation circuit is used for realizing electrical isolation between the FPGA circuit and an external interface.
Optionally, the interface circuit further comprises:
the optical fiber interface circuit is electrically connected with the FPGA circuit;
the optical fiber interface circuit is used for enabling the FPGA circuit to realize optical fiber communication with an external interface;
a fifth isolation circuit electrically connected to the optical fiber interface circuit;
and the fifth isolation circuit is used for realizing electrical isolation between the FPGA circuit and an external interface.
Optionally, the navigator further includes a display interface conversion circuit, and an input end of the display interface conversion circuit is electrically connected with the second processing module;
the display interface conversion circuit is used for being in communication connection with the display so as to correspondingly display the signals processed by the first processing module and/or the second processing module.
Optionally, the display interface conversion circuit at least includes one of:
the LVDS interface conversion circuit comprises an LVDS conversion chip and an LVDS interface, wherein the LVDS conversion chip is electrically connected with the LVDS interface, and the input end of the LVDS interface conversion circuit is electrically connected with the second processing module;
VGA interface conversion circuit; the VGA conversion chip is electrically connected with the VGA interface, and the input end of the VGA interface circuit is electrically connected with the second processing module.
Optionally, the navigator further comprises an ethernet circuit, and the ethernet circuit is electrically connected with the second processing module;
the Ethernet circuit is used for enabling the navigator to realize Ethernet communication with external terminal equipment.
According to the technical scheme, the navigator comprises a navigation position acquisition module, a first processing module, a second processing module and an interface conditioning module, wherein the interface conditioning module comprises an interface circuit, an FPGA circuit and an isolation circuit, the FPGA circuit is electrically connected with the interface circuit, the FPGA circuit is in communication connection with the first processing module, the second processing module, the navigation position acquisition module and an external interface through the interface circuit, the isolation circuit is electrically connected with the FPGA circuit, the first processing module is electrically connected with the second processing module, the processing and interaction structure of the navigator on various signals are optimized, the processing of the navigator on various signals is simpler and more convenient, the interaction structure of various signals is more reasonable, the interface of the navigator is isolated through the isolation circuit, the influence of various interference signals is reduced, meanwhile, the internal circuit of the navigator can be protected, and the reliability of the navigator is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an embodiment of a navigator according to the present invention;
FIG. 2 is a schematic view of another embodiment of a navigator according to the present invention;
FIG. 3 is a schematic view of a navigator according to another embodiment of the present invention;
FIG. 4 is a schematic view of a navigator according to another embodiment of the present invention;
FIG. 5 is a schematic view of a navigator according to another embodiment of the present invention;
FIG. 6 is a schematic structural view of a sixth embodiment of a navigator according to the present invention;
FIG. 7 is a schematic view of a seventh embodiment of a navigator according to the present invention;
FIG. 8 is a schematic view of an eighth embodiment of a navigator according to the present invention;
FIG. 9 is a schematic view of a ninth embodiment of a navigator according to the present invention;
FIG. 10 is a schematic circuit diagram of an embodiment of a mileage counting interface circuit of the present invention;
FIG. 11 is a schematic circuit diagram of an embodiment of an odometer of the present invention;
FIG. 12 is a schematic circuit diagram of another embodiment of an odometer of the invention;
FIG. 13 is a schematic circuit diagram of an embodiment of a first isolation circuit of the present invention;
FIG. 14 is a schematic circuit diagram of one embodiment of a shaping circuit according to the present invention;
FIG. 15 is a schematic circuit diagram of an embodiment of the present invention of the time system interface circuit and the second isolation circuit;
FIG. 16 is a schematic circuit diagram of another embodiment of the present invention of a time system interface circuit and a second isolation circuit;
FIG. 17 is a schematic circuit diagram of an embodiment of an optoelectronic module according to the present invention;
FIG. 18 is a schematic circuit diagram of a VGA interface conversion circuit of the present invention;
fig. 19 is a schematic circuit diagram of the LVDS interface conversion circuit of the present invention.
Reference numerals illustrate:
the achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
The navigator is a product of modern technology and is used for positioning, navigation and entertainment, and with the wide application of automobiles, ships, unmanned aerial vehicles and the like and the construction of roads, the inter-city economic traffic is more frequent, and the navigator plays an increasingly important role.
Because the navigator relates to the processing of various signals, and the interactive structure between various signals is complicated, the use requirement of users can not be met gradually by the existing navigator.
To solve the above problems, the present invention proposes a navigator, referring to fig. 1, in one embodiment of the present invention, the navigator includes a navigation position acquisition module 10;
the terminal acquisition module 10 comprises:
an odometer 11 for acquiring a first navigation signal of the target;
an inertial measurement device 12 for acquiring a second navigation signal of the target;
a satellite positioning system 13 for acquiring a third navigation position signal of the target;
the navigator further includes:
a first processing module 30;
a second processing module 40;
an interface conditioning module 20, the interface conditioning module 20 comprising:
an interface circuit 21;
an FPGA circuit 23 electrically connected to the interface circuit 21;
the FPGA circuit 23 is configured to establish a communication connection with the first processing module 30, the second processing module 40, the navigation position acquisition module 10, and an external interface through the interface circuit 21;
an isolation circuit 22 electrically connected to the FPGA circuit 23; the isolation circuit 22 is used for realizing electrical isolation of the FPGA circuit 23;
the first processing module 30 is configured to process the first and second navigation signals transmitted by the interface conditioning module 20;
the second processing module 40 is electrically connected to the first processing module 30;
the second processing module 40 is configured to process the third navigation level signal transmitted by the interface conditioning module 20, or process the fourth navigation level signal transmitted by the first processing module 30, and perform a corresponding display.
Alternatively, the navigator may be applied to an automobile, a ship, an unmanned aerial vehicle, a robot, a mobile terminal, etc., and targets it, thereby acquiring its navigation signals.
The odometer 11 is used for acquiring the driving speed of the target and calculating the driving mileage of the target, thereby generating a first navigation position signal.
The inertial measurement device 12 is capable of generating a second dead-reckoning signal by measuring changes in acceleration and angular velocity of the target and deriving the position and attitude of the object in three-dimensional space.
The satellite positioning system 13 is capable of providing 3-dimensional coordinates and velocity and time information of the target at any point on the earth's surface or near earth space, thereby generating a third navigation position signal.
Optionally, the interface conditioning module 20 is electrically connected to the first processing module 30 and the second processing module 40 via a PCI-e bus or an I2C bus.
The FPGA circuit 23 establishes communication connection with the first processing module 30, the second processing module 40, the navigation position acquisition module 10 and the external interface through the interface circuit 21, and the FPGA circuit 23 can implement interface conditioning and matching functions with the first processing module 30, the second processing module 40, the navigation position acquisition module 10 and the external interface.
The isolation circuit 22 is electrically connected with the FPGA circuit 23, and the isolation circuit 22 is configured to electrically isolate the FPGA circuit 23 from the first processing module 30, the second processing module 40, the navigation position acquisition module 10, and the external interface, so as to reduce the influence of various interference signals, and protect the internal circuit of the navigator.
Optionally, the first processing module 30 includes a DSP chip, and in an embodiment of the present invention, the DSP chip is of a model FT-M6678H; the first processing module can perform data analysis, data calculation and other processing on the first navigation position signal acquired by the odometer 11 and the second navigation position signal acquired by the inertial measurement device 12, so as to generate current first position information of the target.
Optionally, the second processing module 40 includes a CPU, and in an embodiment of the present invention, the CPU is of a model number of 2K1000; the second processing module can analyze and process the third navigation position signal collected by the satellite positioning system 13 to generate current second position information of the target, and meanwhile, the current first position information of the target and the current second position information of the target are checked to generate final position information of the target, so that the accuracy of the position information of the target is ensured.
Optionally, referring to fig. 8, in another embodiment of the present invention, the navigator further includes a display interface conversion circuit 50, and an input terminal of the display interface conversion circuit 50 is electrically connected to the second processing module 40;
the display interface conversion circuit 50 is configured to be communicatively connected to a display, so as to perform corresponding display on the signals processed by the first processing module 30 and/or the second processing module 40.
Optionally, the display may be at least one of an LCD display screen, an LED display screen, a VGA display screen, and an XGA display screen, and the display is electrically connected to the display interface conversion circuit 50, and after the navigator obtains the final position information of the target, the navigator may perform corresponding display through the display.
Optionally, in an embodiment of the present invention, referring to fig. 18-19, the display interface conversion circuit 50 includes at least one of:
the LVDS interface conversion circuit 51 includes an LVDS conversion chip and an LVDS interface, the LVDS conversion chip is electrically connected to the LVDS interface, and an input end of the LVDS interface conversion circuit 51 is electrically connected to the second processing module 40;
VGA interface conversion circuit 52; the VGA conversion chip is electrically connected with the VGA interface, and the input end of the VGA interface circuit 52 is electrically connected with the second processing module 40.
Optionally, referring to fig. 2 and 10, the interface circuit 21 further includes:
the mileage counting interface circuit 211, two ends of the mileage counting interface circuit 211 are respectively and electrically connected with the FPGA circuit 23 and the mileage meter 11;
the mileage counting interface circuit 311 is used for collecting a first navigation position signal of a target;
the isolation circuit further includes:
a first isolation circuit 221, wherein the first isolation circuit 221 is electrically connected with the mileage counting interface circuit 211;
the first isolation circuit 221 is configured to electrically isolate the FPGA circuit from the odometer 11.
11-13, the odometer 11 may be configured as an electronic odometer and/or a Hall odometer, the first isolation circuit 221 employs an optical coupler isolation chip, optionally, the optical coupler isolation chip is a low-speed optical coupler, the model is GH320IJ-2, an output end of the odometer 11 is connected with an input end of the odometer interface circuit 211, an output end of the odometer interface circuit 211 is connected with an input end of the first isolation circuit 221, and an output end of the first isolation circuit 221 is electrically connected with an FPGA circuit, so that the first navigation position signal collected by the odometer 11 is output to the FPGA circuit through the odometer interface circuit 211 and the first isolation circuit 221, thereby completing collection of the first navigation position signal.
Optionally, the first isolation circuit 221 described with reference to fig. 3 and 14 further includes:
a transient voltage suppression circuit 2211, wherein an input end of the transient voltage suppression circuit 2211 is electrically connected with the mileage counting interface 211 circuit;
the transient voltage suppression circuit 2211 is used for suppressing high spike pulses in the first navigation level signal;
the input end of the filtering circuit 2212 is connected with the output end of the transient voltage suppression circuit 2211, and is used for filtering the first navigation position signal;
a clamp circuit 2213, wherein an input end of the clamp circuit 2213 is connected with an output end of the filter circuit 2212;
the clamping circuit 2213 is configured to clamp a voltage of the first navigation signal;
a shaping circuit 2214, wherein an input end of the shaping circuit 2214 is connected with an output end of the clamp circuit 2213;
the shaping circuit 2214 is configured to enhance a driving capability of the first navigation signal.
Optionally, the transient voltage suppression circuit 2211 includes a transient voltage suppressor, the filtering circuit 2212 includes a filter, the clamp circuit 2213 includes a zener diode, and the shaping circuit 2214 adopts a shaping chip with a model number of G54AC 14S; because the odometer 11 may have poor quality, weak signals and more signal interference, so that the driving capability of the odometer is weaker, the pulse signal of the odometer interface circuit 211 is high-level and is larger than 4V, the peak value is smaller than 12V, the low-level and is smaller than 0.8V, the signal frequency is about 10kHZ, the signal cannot directly drive the optocoupler chip, the first navigation position signal collected by the odometer in the embodiment inhibits high spike pulse through the transient voltage inhibition circuit 2211, then is filtered through the filtering circuit 2212, then clamps the voltage to be below 4.7V through the voltage clamping circuit 2213, and after being shaped through the shaping circuit 2214, the signal is input into the FPGA circuit through the first isolation circuit 221, so as to complete the collection of the first navigation position signal.
Optionally, referring to fig. 4 and fig. 15-16, the interface circuit 21 further includes:
a time system interface circuit 212, wherein a first end of the time system interface circuit 212 is electrically connected with the FPGA circuit 23, and a second end of the time system interface circuit 212 is respectively connected with the inertial measurement device 12 and the satellite positioning system 13 in a communication manner;
the time system interface circuit 212 is configured to collect a second navigation level signal and a third navigation level signal;
the isolation circuit 22 further includes:
a second isolation circuit 222, the second isolation circuit 222 being electrically connected to the time system interface circuit 212;
the second isolation circuit 222 is configured to electrically isolate the FPGA circuit 23 from the inertial measurement device 12 and the FPGA circuit 23 from the satellite positioning system 13.
Optionally, the second isolation circuit 222 includes an optocoupler isolation chip, and the model of the optocoupler isolation chip is GH3201J. The output end of the inertial measurement device 12 is connected with the first input end of the time system interface circuit 212, the output end of the satellite positioning system 13 is connected with the second input end of the time system interface circuit 212, the output end of the time system interface circuit 212 is connected with the input end of the second isolation circuit 222, and the output end of the second isolation circuit 222 is electrically connected with the FPGA circuit, so that the second navigation position signal collected by the inertial measurement device 12 is output to the FPGA circuit through the time system interface circuit 212 and the second isolation circuit 222, and the collection of the second navigation position signal is completed; the third navigation position signal collected by the satellite positioning system 13 is output to the FPGA circuit through the system interface circuit 212 and the second isolation circuit 222, thereby completing the collection of the third navigation position signal.
Optionally, referring to fig. 5, the interface circuit 21 further includes:
an RS422 interface circuit 213, the RS422 interface circuit 213 being electrically connected to the FPGA circuit 23;
the RS422 interface circuit 213 is configured to enable the FPGA circuit 23 to implement RS422 communication with an external interface;
the isolation circuit 22 includes:
a third isolation circuit 223, the third isolation circuit 223 being electrically connected to the RS422 interface circuit;
the third isolation circuit 223 is configured to electrically isolate the FPGA circuit 23 from an external interface.
Optionally, the input end of the RS422 interface circuit is connected to a first resistor, where the resistance value of the first resistor is 120The third isolation circuit 223 includes a digital isolator; the input end of the RS422 interface circuit realizes terminal matching by configuring the first resistor, the positive end and the negative end of the time difference branching line determine the signal initialization state through the pull-up resistor and the pull-down resistor, and the signal after level matching is formed byThe third isolation circuit 223 sends the FPGA circuit 23 to process, thereby realizing RS422 communication between the FPGA circuit 23 and an external interface.
Optionally, referring to fig. 6, the interface circuit 21 further includes:
a CAN interface circuit 214, the CAN interface circuit 214 being electrically connected to the FPGA circuit 23;
the CAN interface circuit 214 is used for enabling the FPGA circuit 23 to realize CAN communication with an external interface;
the isolation circuit 22 further includes:
a fourth isolation circuit 224, the fourth isolation circuit 224 being electrically connected to the CAN interface circuit 214;
the fourth isolation circuit 224 is configured to electrically isolate the FPGA circuit 23 from the external interface.
Optionally, the CAN interface circuit 214 includes a CAN interface controller and a CAN level conversion chip, the CAN interface controller is electrically connected to the CAN level conversion chip, and the fourth isolation circuit 224 includes a magnetic isolation chip; the CAN interface controller is controlled by the FPGA circuit 23 to realize the output and input of serial data, and the serial signal is matched with the signal through the CAN level conversion chip, so that the CAN communication between the FPGA circuit 23 and an external interface is realized.
Optionally, the model adopted by the CAN interface controller is SMSJA1000, and the model adopted by the CAN level conversion chip is SM82C250; optionally, the output pin of the CAN interface controller is connected with a second resistor, and optionally, the resistance value of the second resistor is 10kBy using the second resistor to pull up the voltage of the output pin of the CAN interface controller, the suspension state CAN be prevented when the power is on, and thus the circuit is protected.
Optionally, referring to fig. 7, the interface circuit 21 further includes:
a fiber interface circuit 215, the fiber interface circuit 215 being electrically connected to the FPGA circuit 23;
the optical fiber interface circuit 215 is configured to enable the FPGA circuit 23 to implement optical fiber communication with an external interface;
a fifth isolation circuit 225, the fifth isolation circuit 225 being electrically connected to the fiber optic interface circuit 215;
the fifth isolation circuit 225 is configured to electrically isolate the FPGA circuit 23 from the external interface.
Optionally, referring to fig. 17, the optical fiber interface circuit 215 includes an optical fiber bus protocol chip and an optoelectronic module, the bus protocol chip is electrically connected to the optoelectronic module through a high-speed FC channel, and the fifth isolation circuit 225 includes a magnetic isolation chip; the clock of the photoelectric module is provided by a 125M differential crystal oscillator through an optical fiber bus protocol chip, and after protocol conversion is completed in the optical fiber bus protocol chip, data interaction can be performed between the optical fiber bus and the FPGA circuit 23 through an EMIF bus, so that optical fiber communication between the FPGA circuit 23 and an external interface is realized; optionally, after the protocol conversion is completed inside the fiber bus protocol chip, data interaction can be directly implemented with the second processing module 40 through a PCIe bus, and the PCIe clock is provided by the second processing module 40.
Optionally, referring to fig. 9, the navigator further includes an ethernet circuit 60, and the ethernet circuit 60 is electrically connected to the second processing module 40;
the ethernet circuit 60 is configured to enable the navigator to implement ethernet communication with an external terminal device.
Optionally, the ethernet circuit 60 includes a PHY chip, optionally a JEM88E1111HV, and the PHY chip is electrically connected to the second processing module 40 and through an XMC connector and a network transformer, so that the navigator and the external terminal device implement ethernet communication.
The navigator comprises a navigation position acquisition module 10, a first processing module 30, a second processing module 40 and an interface conditioning module 20, wherein the interface conditioning module 20 comprises an interface circuit 21, an FPGA circuit 23 and an isolation circuit 22, the FPGA circuit 23 is electrically connected with the interface circuit 21, the FPGA circuit 23 is in communication connection with the first processing module 30, the second processing module 40, the navigation position acquisition module 10 and an external interface through the interface circuit 21, the isolation circuit 22 is electrically connected with the FPGA circuit 23, the first processing module 30 is electrically connected with the second processing module 40, the processing and interaction structure of the navigator on various signals are optimized, the processing of the navigator on various signals is simpler and more convenient, the interaction structure of various signals is more reasonable, the interface of the navigator is isolated through the isolation circuit 22, so that the influence of various interference signals is reduced, meanwhile, the internal circuit of the navigator can be protected, and the reliability of the navigator is improved.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structural changes made by the description of the present invention and the accompanying drawings or direct/indirect application in other related technical fields are included in the scope of the invention.
Claims (10)
1. A navigator comprises a navigation position acquisition module;
the navigation position acquisition module comprises:
the odometer is used for acquiring a first navigation position signal of a target;
the inertial measurement device is used for acquiring a second navigation position signal of the target;
the satellite positioning system is used for acquiring a third navigation position signal of the target;
the navigator is characterized in that the navigator further comprises:
a first processing module;
a second processing module;
an interface conditioning module, the interface conditioning module comprising:
an interface circuit;
the FPGA circuit is electrically connected with the interface circuit;
the FPGA circuit is used for establishing communication connection with the first processing module, the second processing module, the navigation position acquisition module and an external interface through the interface circuit;
the isolation circuit is electrically connected with the FPGA circuit; the isolation circuit is used for realizing electrical isolation of the FPGA circuit;
the first processing module is used for processing the first navigation position signal and the second navigation position signal transmitted by the interface conditioning module;
the second processing module is electrically connected with the first processing module;
the second processing module is used for processing the third navigation position signal transmitted by the interface conditioning module or processing the fourth navigation position signal transmitted by the first processing module and displaying the third navigation position signal and the fourth navigation position signal correspondingly.
2. The navigator of claim 1, wherein the interface circuit further comprises:
the two ends of the mileage counting interface circuit are respectively and electrically connected with the FPGA circuit and the mileage meter;
the mileage counting interface circuit is used for collecting a first navigation position signal of a target;
the isolation circuit further includes:
the first isolation circuit is electrically connected with the mileage counting interface circuit;
and the first isolation circuit is used for realizing electrical isolation between the FPGA circuit and the odometer.
3. The navigator of claim 2,
the first isolation circuit further includes:
the input end of the transient voltage suppression circuit is electrically connected with the mileage counting interface circuit;
the transient voltage suppression circuit is used for suppressing high spike pulses in the first navigation position signal;
the input end of the filter circuit is connected with the output end of the transient voltage suppression circuit and is used for carrying out filter processing on the first navigation position signal;
the input end of the clamping circuit is connected with the output end of the filter circuit;
the clamping circuit is used for clamping the voltage of the first navigation position signal;
the input end of the shaping circuit is connected with the output end of the clamp circuit;
the shaping circuit is used for enhancing the driving capability of the first navigation position signal.
4. The navigator of claim 1,
the interface circuit further includes:
the first end of the time system interface circuit is electrically connected with the FPGA circuit, and the second end of the time system interface circuit is respectively connected with the inertial measurement equipment and the satellite positioning system in a communication way;
the time system interface circuit is used for acquiring a second navigation position signal and a third navigation position signal;
the isolation circuit further includes:
the second isolation circuit is electrically connected with the time system interface circuit;
the second isolation circuit is used for realizing electrical isolation between the FPGA circuit and the inertial measurement device and between the FPGA circuit and the satellite positioning system.
5. The navigator as recited in any one of claims 1 to 4,
the interface circuit further includes:
the RS422 interface circuit is electrically connected with the FPGA circuit;
the RS422 interface circuit is used for enabling the FPGA circuit to realize RS422 communication with an external interface;
the isolation circuit includes:
the third isolation circuit is electrically connected with the RS422 interface circuit;
and the third isolation circuit is used for realizing electrical isolation between the FPGA circuit and an external interface.
6. The navigator as recited in any one of claims 1 to 4,
the interface circuit further includes:
the CAN interface circuit is electrically connected with the FPGA circuit;
the CAN interface circuit is used for enabling the FPGA circuit to realize CAN communication with an external interface;
the isolation circuit further includes:
the fourth isolation circuit is electrically connected with the CAN interface circuit;
and the fourth isolation circuit is used for realizing electrical isolation between the FPGA circuit and an external interface.
7. The navigator as recited in any one of claims 1 to 4,
the interface circuit further includes:
the optical fiber interface circuit is electrically connected with the FPGA circuit;
the optical fiber interface circuit is used for enabling the FPGA circuit to realize optical fiber communication with an external interface;
a fifth isolation circuit electrically connected to the optical fiber interface circuit;
and the fifth isolation circuit is used for realizing electrical isolation between the FPGA circuit and an external interface.
8. The navigator of claim 1,
the navigator also comprises a display interface conversion circuit, wherein the input end of the display interface conversion circuit is electrically connected with the second processing module;
the display interface conversion circuit is used for being in communication connection with the display so as to correspondingly display the signals processed by the first processing module and/or the second processing module.
9. The navigator of claim 8,
the display interface conversion circuit at least comprises one of the following:
the LVDS interface conversion circuit comprises an LVDS conversion chip and an LVDS interface, wherein the LVDS conversion chip is electrically connected with the LVDS interface, and the input end of the LVDS interface conversion circuit is electrically connected with the second processing module;
VGA interface conversion circuit; the VGA conversion chip is electrically connected with the VGA interface, and the input end of the VGA interface circuit is electrically connected with the second processing module.
10. The navigator of claim 1,
the navigator further comprises an Ethernet circuit, wherein the Ethernet circuit is electrically connected with the second processing module;
the Ethernet circuit is used for enabling the navigator to realize Ethernet communication with external terminal equipment.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410011337.6A CN117553786A (en) | 2024-01-04 | 2024-01-04 | Navigation device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410011337.6A CN117553786A (en) | 2024-01-04 | 2024-01-04 | Navigation device |
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| CN202410011337.6A Pending CN117553786A (en) | 2024-01-04 | 2024-01-04 | Navigation device |
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