CN111220152A - Navigation calculation module based on LX800 and working method - Google Patents

Abstract

The invention discloses a navigation calculation module based on LX800 and a working method, the navigation calculation module is provided with an FPGA and a south bridge, the FPGA is internally provided with a plurality of interfaces which can be configured and isolated, a plurality of pulse timing/counters, a UART protocol controller and a control/state register for timing, counting and storing, the south bridge is used for managing peripheral interfaces, and the pulse timing/counters are matched with the control/state register, so that independent GPS (global positioning system) independent positioning and navigation can be realized, and then the south bridge is combined with GPS navigation to make best use of advantages and disadvantages, and the navigation capability, precision and reliability of the system are obviously improved.

Description

Navigation calculation module based on LX800 and working method

Technical Field

The invention belongs to the field of navigation computing modules, and particularly relates to an LX 800-based navigation computing module and a working method thereof.

Background

In modern high-tech wars, aiming at the application of special vehicles in special environments, any single navigation system is often difficult to meet the navigation requirements of various carriers. By combining different navigation system technologies, the information of two or more navigation systems can be integrated, so that the advantages of the two or more navigation systems are complementary, the navigation performance of the whole system is improved, and various requirements of various users are met.

Disclosure of Invention

The invention aims to provide an LX 800-based navigation calculation module and a working method, which can be combined with inertial navigation to realize independent positioning and navigation independent of GPS.

In order to achieve the purpose, the navigation computation module based on the LX800 comprises a processor, wherein the processor is connected with an FPGA (field programmable gate array), and the FPGA is connected with a south bridge;

the FPGA comprises a plurality of paths of interfaces capable of being configured and isolated and a plurality of paths of pulse timing/counters, each interface capable of being configured and isolated corresponds to a UART protocol controller, the UART protocol controller and the pulse timing/counters are connected with a control/state register, the UART protocol controller is connected with an optical coupling isolation circuit, and the optical coupling isolation circuit is connected with a signal interface bus;

the pulse timing/counter is used for timing and counting, and sending data to the control/state register, and then resetting the timing and counting in the pulse timing/counter;

the south bridge is used for management of peripheral interfaces.

All UART protocol controllers are connected with a phase-locked loop and a control/state register through an ISA bus-Wishbone bus bridge, and the control/state register is used for receiving the pulse quantity sent by the pulse timing/counter and exchanging data with the corresponding UART protocol controller.

All UART protocol controllers are connected with the interrupt management module.

Digital isolation is arranged between the interface capable of being configured and isolated and the corresponding UART protocol controller, a 5V isolation power supply is introduced between the interface capable of being configured and isolated and the digital isolation, and 3.3V voltage is introduced between the digital isolation and the UART protocol controller.

A working method of a navigation computation module based on LX800 is used for counting through 2 16-position timing counters when a photoelectric odometer which reflects a speed value of an equipment vehicle works, clearing and counting again after reading out, and setting timing reading time through a 1ms timing interface provided by a south bridge;

when the Hall odometer works, 1 32-bit timing counter is adopted for carrying out accumulated counting, the reading time is set through a 1ms timing interface provided by a south bridge, the value of the 32-bit timing counter is a value reflecting the total driving mileage of the equipment vehicle, and the 1-way 24V switching value enters an FPGA for carrying out state real-time updating after digital isolation and level conversion.

The signals of the Hall odometer and the photoelectric odometer are generated by a pulse timing/counter.

Compared with the prior art, the invention is provided with the FPGA and the south bridge, the FPGA is internally provided with a plurality of interfaces which can be configured and isolated, a plurality of pulse timing/counters, a UART protocol controller and a control/state register which are used for timing, counting and storing, the south bridge is used for managing peripheral interfaces, and the pulse timing/counters and the control/state register are matched, so that the autonomous positioning and navigation independent of GPS can be realized, and then the south bridge is combined with GPS navigation, thereby improving the advantages and the disadvantages, and obviously improving the navigation capability, the precision and the reliability of the system.

The method adopts the photoelectric odometer to acquire the speed value of the equipment vehicle, adopts the Hall odometer to acquire the total driving mileage value of the equipment vehicle, can realize autonomous positioning and navigation without depending on a GPS, and can acquire the total driving mileage value and the driving speed of the equipment vehicle at the same time.

Drawings

FIG. 1 is a functional block diagram of the present invention;

FIG. 2 is an internal functional block diagram of the FPGA of the present invention;

FIG. 3 is a functional block diagram of an interface capable of being configured for isolation in the present invention;

FIG. 4 is a functional block diagram of a photoelectric odometer interface;

FIG. 5 is a functional block diagram of a Hall odometer interface.

Detailed Description

The invention will be further explained with reference to the drawings.

The invention is based on the general navigation computing module of AMD Geode LX800+ CS5536 processor structure, LX800 integrates a display control chip, DRGB and VGA and other display interfaces can be used, south bridge CS5536 is mainly responsible for the management of external interfaces, and the memory adopts 2GB DDR SDRAM of a plate paste, thus being capable of adapting to wide temperature environment, ultra-low power consumption, high stability and having longer life cycle. 8 independent configurable isolation RS232/RS422 interfaces and 5 pulse timing/counting interfaces are integrated externally, and functions of data acquisition and preprocessing, navigation resolving, data interaction with an upper computer and the like are achieved.

As shown in fig. 1, the LX800 PC104 module is based on an X86 architecture, and a 1-way 64-bit DDR memory with a storage capacity of 256MB is extended by 1-channel DDR controller of the AMD LX800 processor in the design; in order to enhance the reliability of the system, all the memory particles are pasted on a board without using a memory slot. The PCI bus may additionally be extended by an IT8029 PCI extension arbiter.

The south bridge CS5536 is connected with the LX800 through a PCI bus; the south bridge CS5536 is mainly responsible for management of peripheral interfaces, such as VGA, USB2.0, IDE, RS232, 10M/100M adaptive ethernet, PCI bus, etc. The VGA and the USB can be directly connected with each device after simple filtering, coupling and antistatic treatment. DRGB signals led out from the south bridge CS5536 need to be converted into LVDS signals through the DS90C387, have better anti-interference capacity and are directly connected with a plurality of displays; the USB is responsible for the management of the external pluggable equipment; the IDE bus is responsible for the management of the external mass storage device; the RS232 is responsible for low-speed communication with external equipment and printing serial port debugging information; the south bridge CS5536 is connected with the FLASH chip through an LPC bus, is used for extracting a hardware initialization code when the system is powered on, and realizes part of low-speed peripheral interfaces through a SuperIO chip; the external expansion PCI bus realizes 1-path 10M/100M self-adaptive Ethernet through a chip 82551 integrated with MAC and PHY by Intel; the add-on PCI bus translates the PCI bus to an ISA bus through an IT8888 PCI-ISA bridge.

Referring to fig. 2, the FPGA integrates 8 independent configurable isolation RS232/RS422 interfaces and 5 pulse timing/counting interfaces, and 13 circuits in total adopt an isolation mode. The UART protocol controller, pulse timing/counter and decode logic are implemented using EP1C12Q240I7 in the ALTERA company Cyclone series. All UART protocol controllers are connected with a phase-locked loop and a control/state register through an ISA bus-Wishbone bus bridge, and the control/state register is used for receiving the pulse quantity sent by the pulse timing/counter and exchanging data with the corresponding UART protocol controller. All UART protocol controllers are connected with the interrupt management module.

Referring to fig. 3, the UART protocol controller is mainly composed of configurable multi-protocol interface device LTC1387IG from the company of the brunett and isolated power device DCR010505U from the companies ISO7220, ISO7221 and BB. The 8-path UART bus transceiving signals enter the UART protocol controller for communication after being isolated by the digital isolator and subjected to level conversion through the interface device LTC1387, and the isolation power supply DCP020505U is isolated to output and is mainly used for providing power input for the LTC1387 bus transceiver and the digital isolator on one side, so that a UART bus communication interface is realized. The 8-way serial RS232 and RS422 communication interfaces are selected by controlling a MODE pin of the LTC1387IG through a jumper.

Referring to fig. 4, the photoelectric odometer adopts a 2-way pulse signal interface circuit, mainly comprises a pulse timing/counter, an optical coupler isolation and the like realized in an FPGA, adopts 2 16-bit timing counters for counting, can be cleared and recounted after being read out, the timing reading time can be set through a 1ms timing interface provided by hardware, and the values of two registers mainly reflect the speed value of the equipment vehicle.

Referring to fig. 5, the hall odometer adopts 1-path pulse signal LCJ + interface circuit which mainly comprises a pulse timing/counter, a signal amplification circuit, an optical coupler isolation and the like realized in an FPGA, and because the LCJ + signal driving current range is 1 mA-5 mA, the signal is amplified and then isolated to enter the subsequent counting processing. 1 32-bit timing counter is adopted for accumulation counting, and the reading time can be set through a 1ms timing interface provided by hardware. The value of the 32-bit timing counter mainly reflects the total mileage value of the equipment vehicle. And the 1-path 24V switching value enters the FPGA for state real-time updating after optical coupling isolation and level conversion.

Claims (6)

1. The navigation calculation module based on the LX800 is characterized by comprising a processor, wherein the processor is connected with an FPGA (field programmable gate array), and the FPGA is connected with a south bridge;

the FPGA comprises a plurality of paths of interfaces capable of being configured and isolated and a plurality of paths of pulse timing/counters, each interface capable of being configured and isolated corresponds to a UART protocol controller, the UART protocol controller and the pulse timing/counters are connected with a control/state register, the UART protocol controller is connected with an optical coupling isolation circuit, and the optical coupling isolation circuit is connected with a signal interface bus;

the pulse timing/counter is used for timing and counting, and sending data to the control/state register, and then resetting the timing and counting in the pulse timing/counter;

the south bridge is used for management of peripheral interfaces.

2. The LX 800-based navigation computation module of claim 1, wherein all UART protocol controllers are connected to the phase locked loop and the control/status register through ISA bus-Wishbone bus bridge, and the control/status register is configured to receive the pulse amount sent by the pulse timing/counter and exchange data with the corresponding UART protocol controller.

3. The LX800 based navigation computation module of claim 1, wherein all UART protocol controllers are connected to the interrupt management module.

4. The LX 800-based navigation computation module of claim 1, wherein a digital isolation is provided between the configurable and isolatable interface and the corresponding UART protocol controller, a 5V isolation power supply is provided between the configurable and isolatable interface and the digital isolation, and a 3.3V voltage is provided between the digital isolation and the UART protocol controller.

5. The working method of the LX 800-based navigation computation module of claim 1, wherein when the photoelectric odometer for reflecting the speed value of the equipped vehicle works, the photoelectric odometer counts by 2 16-bit timing counters, and after the photoelectric odometer is read out, the photoelectric odometer is cleared and recounted, and the timing reading time is set by a 1ms timing interface provided by the south bridge;

when the Hall odometer works, 1 32-bit timing counter is adopted for carrying out accumulated counting, the reading time is set through a 1ms timing interface provided by a south bridge, the value of the 32-bit timing counter is a value reflecting the total driving mileage of the equipment vehicle, and the 1-way 24V switching value enters an FPGA for carrying out state real-time updating after digital isolation and level conversion.

6. The method of claim 5, wherein the signals from the Hall odometer and the photoelectric odometer are generated by a pulse timing/counter.

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