CN210864564U - High-performance main control board with 6U CPCI specification - Google Patents
High-performance main control board with 6U CPCI specification Download PDFInfo
- Publication number
- CN210864564U CN210864564U CN202020025656.XU CN202020025656U CN210864564U CN 210864564 U CN210864564 U CN 210864564U CN 202020025656 U CN202020025656 U CN 202020025656U CN 210864564 U CN210864564 U CN 210864564U
- Authority
- CN
- China
- Prior art keywords
- pci
- processing unit
- central processing
- pcie
- cpci
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The utility model provides a high performance main control board of 6U CPCI specification, include: CPCI bus interface, PCIe-to-PCI/PCI-X bridge, central processing unit, PCIe Switch, high-speed dynamic random access memory, complex programmable logic device, Ethernet PHY chip, universal asynchronous receiver-transmitter, temperature sensor, charged erasable programmable read-only memory, real-time clock chip, nonvolatile flash memory, power management module, mSATA solid state disk, XMC connector, PMC connector and connector. The high-performance main control board with the 6U CPCI specification is designed to be in the CPCI specification, and the board card provides two serial port channels and two gigabit Ethernet ports. The board card adopts the T2080 of the Freescale as a core processing device, and the signal definition conforms to the CompactPCI standard. 4GB DDR3 SDRAM, 128MB NorFlash and 16GB NandFlash on board. An onboard SATA II interface. Meanwhile, the board card also provides 2 XMC/PMC expansion slots, a temperature monitoring function and an RTC function. The board card provides powerful calculation and IO expansion functions, and is very suitable for complex embedded control and calculation occasions.
Description
Technical Field
The utility model relates to a communication, network, computer telephony integration, real-time system control, industrial automation, real-time data acquisition, military system etc. field especially relate to the high performance main control board of 6U CPCI specification.
Background
Compact PCI (Compact Peripheral Component Interconnect) is abbreviated as CPCI, which is a high-performance industrial bus interface standard that is standardized by the PCI electrical specification. CPCI has the characteristics of hot plug, high openness, high reliability and the like. The method is widely applied to the fields of communication, network, computer telephone integration, real-time system control, industrial automation, real-time data acquisition, military systems and the like.
The high-performance main control board based on the 6U CPCI specification provides powerful calculation and IO expansion functions and is suitable for complex embedded control and calculation occasions.
Disclosure of Invention
In order to satisfy complicated embedded control and calculation occasion, the utility model provides a high performance main control board of 6U CPCI specification, this main control board is based on the T2080 PwoerPC treater of NXP, designs for 6U CPCI specification, can be applied to in all 6U CPCI cabinets.
The high-performance main control board of 6U CPCI specification includes: CPCI bus interface, PCIe-to-PCI/PCI-X bridge, central processing unit, PCIe Switch, high-speed dynamic random access memory, complex programmable logic device, Ethernet PHY chip, universal asynchronous receiver-transmitter, temperature sensor, charged erasable programmable read-only memory, real-time clock chip, nonvolatile flash memory, power management module, mSATA solid state disk, XMC connector, PMC connector and connector.
The CPCI bus interface is connected with a PCIe-to-PCI/PCI-X bridge chip, the PCIe-to-PCI/PCI-X bridge chip is connected with the central processing unit, the PCIe-to-PCI/PCI-X bridge chip realizes the conversion between a PCIe bus and a PCI/PCI-X bus, and the central processing unit realizes the PCIe bus interface.
And the central processing unit is connected with a PCIe-to-PCI/PCI-X bridge chip, a PCIe Switch, a high-speed dynamic random access memory, a complex programmable logic device, an Ethernet PHY chip, a universal asynchronous receiver-transmitter, a temperature sensor, a charged erasable programmable read-only memory, a real-time clock chip, a nonvolatile flash memory and a power management module to realize overall control.
PCIe Switch connects CPU, PCI/PCI-X bridge, Ethernet PHY chip, PMC connector, realizes the Switch between CPU and various interfaces.
The high-speed dynamic random access memory is connected with the central processing unit and is used for realizing the caching of programs, data and intermediate results.
And the complex programmable logic device is connected with the CPCI bus interface, the central processing unit and the nonvolatile memory to realize the control of partial functions.
And the Ethernet PHY chip is connected with the CPCI bus interface, the central processing unit and the connector and is used for realizing the Ethernet communication of the central processing unit.
And the universal asynchronous transceiver is connected with the CPCI bus interface, the central processing unit and the connector and is used for realizing the serial port communication function of the central processing unit.
And the temperature sensor is connected with the central processing unit and used for monitoring the temperature of the board card.
The electrified erasable programmable read-only memory is connected with the central processing unit and used for data storage.
The real-time clock chip is connected with the central processing unit and is used for providing clock signals for the central processing unit.
And the nonvolatile flash memory is connected with the central processing unit and the complex programmable logic device and is used for storing data.
And the power management module is connected with a CPCI bus interface, a PCIe-to-PCI/PCI-X bridge chip, a PCIe Switch, a central processing unit, a high-speed dynamic random access memory, an Ethernet PHY chip, a temperature sensor, a complex programmable logic device, a real-time clock chip, a universal asynchronous receiver-transmitter, a nonvolatile flash memory and a connector and is used for providing various required voltages for the high-performance main control board with the 6U CPCI specification.
And the mSATA solid state disk is connected with the central processing unit and used for large-capacity data storage (space and XMC/PMC connector daughter card multiplexing).
And the XMC connector is connected with the central processing unit and is used for realizing the connection between the central processing unit and the expansion card.
And the PMC connector is connected with the PCIe-to-PCI/PCI-X bridge chip and the CPCI bus interface and is used for realizing the connection of the expansion card, the PCIe-to-PCI/PCI-X bridge chip and the CPCI bus interface.
And the connector assembly is connected with the universal asynchronous transceiver and the Ethernet PHY chip and is a connector for external communication of the high-performance main control board with the 6U CPCI specification.
The utility model has the advantages that: the high-performance main control board with the 6U CPCI specification is designed to be in the CPCI specification, and the board card provides two serial port channels and two gigabit Ethernet ports. The board card adopts a T2080 of Fiscal as a core processing device, a CPCI bus is connected with a CPU through a bridge chip, the bus frequency is 33/66MHz, the bus bit width is 64bit, 6 slave devices are supported, a 0 slot and a non-0 slot are supported, and the signal definition conforms to the CompactPCI standard. 4GB DDR3 SDRAM, on board, supports ECC functionality for buffering of messages. 128MB NorFlash and 16GB NandFlash were onboard. And an onboard SATA II interface, which uses a solid state hard disk of mSATA specification. Meanwhile, the board card also provides 2 XMC/PMC expansion slots, a temperature monitoring function and an RTC function. The board card provides powerful calculation and IO expansion functions, and is very suitable for complex embedded control and calculation occasions.
The technical solution of the present invention is further described in detail by the accompanying drawings and examples.
Drawings
Fig. 1 is a block diagram of a high-performance main control board of the 6U CPCI specification provided by the present invention.
Detailed Description
As shown in fig. 1, the present invention provides a block diagram of a high-performance main control board with 6U CPCI standard. The high-performance main control board with the 6U CPCI specification comprises: CPCI bus interface 11, PCIe-to-PCI/PCI-X bridge 12, central processing unit 13, PCIe Switch14, high-speed dynamic random access memory 15, complex programmable logic device 16, Ethernet PHY chip 17, universal asynchronous receiver 18, temperature sensor 19, electrified erasable programmable read only memory 20, real-time clock chip 21, nonvolatile flash memory 22, power management module 23, mSATA solid state disk 24, XMC connector 25, PMC connector 26 and connector 27.
The CPCI bus interface 11 is connected with a PCIe-to-PCI/PCI-X bridge piece 12, the PCIe-to-PCI/PCI-X bridge piece 12 is connected with a central processing unit 13, the PCIe-to-PCI/PCI-X bridge piece 12 realizes the conversion between a PCIe bus and a PCI/PCI-X bus, and the central processing unit 13 realizes a PCIe bus interface.
The host interface is a CPCI bus interface, the PCIe-to-PCI/PCI-X bridge chip 12 is realized by PI7C9X130, and the host and the high-performance main control board with the 6U CPCI specification perform data transmission in a PCI bus mode.
The central processing unit 13 is connected with the PCIe-to-PCI/PCI-X bridge chip 12, the PCIe Switch14, the high-speed dynamic random access memory 15, the complex programmable logic device 16, the Ethernet PHY chip 17, the universal asynchronous receiver/transmitter 18, the temperature sensor 19, the electrified erasable programmable memory 20, the real-time clock chip 21, the nonvolatile flash memory 22 and the power management module 23; the central processing unit 13 adopts a T2080 of the ricekar as a core processor to realize the overall control.
The PCIe Switch14 is connected to the central processing unit 13, the PCIe-to-PCI/PCI-X bridge 12, the ethernet PHY chip 17, and the connector 27, so as to implement switching between the central processing unit and various interfaces.
The high-speed dynamic random access memory 15 is connected with the central processing unit 13 and is used for realizing the caching of programs, data and intermediate results; the high speed dram 15 comprises 8 DDR3 SDRAMs of 512MB, which may better perform the performance of the cpu 13.
And the complex programmable logic device 16 is connected with the CPCI bus interface 11, the central processing unit 13 and the nonvolatile memory 22 to realize control of partial functions.
The Ethernet PHY chip 17 is connected with the CPCI bus interface 11, the central processing unit 13 and the connector 27 and is used for realizing Ethernet communication of the central processing unit 13, and four Ethernet PHY chips 17 with two types are adopted and are used for realizing Ethernet communication of the central processing unit 13 to the outside and other equipment on the mainboard.
The universal asynchronous transceiver 18 is connected with the central processing unit 13, the CPCI bus interface 11 and the connector 27 and is used for realizing the serial port communication function of the central processing unit 13; two universal asynchronous transceivers 18 are used to realize serial communication between the cpu 13 and other devices on the motherboard.
And the temperature sensor 19 is connected with the central processing unit 13 and is used for monitoring the board temperature.
The electrified erasable programmable read-only memory 20 is connected with the central processing unit 13 and used for data storage.
The real-time clock chip 21 is connected with the central processing unit 13 and is used for providing a real-time clock signal for the central processing unit 13; when the power failure occurs, the power can be supplied through the onboard button battery, so that the RTC function is realized.
And the nonvolatile flash memory 22 is connected with the central processing unit 13 and the complex programmable logic device 16 and is used for data storage.
The power management module 23 is connected to the CPCI bus interface 11, the PCIe-to-PCI/PCI-X bridge 12, the central processing unit 13, the PCIe Switch14, the high speed dynamic random access memory 15, the complex programmable logic device 16, the ethernet PHY chip 17, the universal asynchronous receiver/transmitter 18, the temperature sensor 19, the live erasable programmable read only memory 20, the real time clock chip 21, the nonvolatile flash memory 22, the ata mSATA solid state disk 24, the XMC connector 25, and the PMC connector 26, and is configured to provide various voltages required by the high performance main control board of the 6U CPCI specification.
And the mSATA solid state disk 24 is connected with the central processing unit 13 and used for large-capacity data storage (space and XMC/PMC connector daughter card multiplexing).
And the XMC connector 25 is connected with the central processing unit 13 and is used for realizing the connection between the central processing unit and the expansion card.
And the PMC connector 26 is connected with the CPCI bus interface 11 and the PCIe-to-PCI/PCI-X bridge chip 12 and is used for realizing the connection between the expansion card and the CPCI bus interface 11 and the connection between the PCIe-to-PCI/PCI-X bridge chip 12.
The connector 27 is connected with the ethernet PHY chip 17 and the universal asynchronous receiver/transmitter 18, and is a connector for external communication of the high-performance main control board in the 6U CPCI specification.
The utility model has the advantages that: the high-performance main control board with the 6U CPCI specification is designed to be in the CPCI specification, and the board card provides two serial port channels and two gigabit Ethernet ports. The board card adopts NXP T2080 as a core processing device, the CPCI bus is connected with the CPU through a bridge chip, the bus frequency is 33/66MHz, the bus bit width is 64bit, 6 slave devices are supported, 0 slot and non-0 slot are supported, and the signal definition conforms to the CompactPCI standard. 4GB DDR3 SDRAM, on board, supports ECC functionality for buffering of messages. 128MB NorFlash and 16GB NandFlash were onboard. And an onboard SATA II interface, which uses a solid state hard disk of mSATA specification. Meanwhile, the board card also provides 2 XMC/PMC expansion slots, a temperature monitoring function and an RTC function. The board card provides powerful calculation and IO expansion functions, and is very suitable for complex embedded control and calculation occasions.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the preferred embodiments, those skilled in the art should understand that: the technical solution of the present invention can still be modified or replaced by other equivalent means, and the modified technical solution can not be separated from the spirit and scope of the technical solution of the present invention.
Claims (2)
1. The utility model provides a high performance master control board of 6U CPCI specification which characterized in that:
the high-performance main control board of 6U CPCI specification includes: the system comprises a CPCI bus interface, a PCIe-to-PCI/PCI-X bridge chip, a central processing unit, a PCIe Switch, a high-speed dynamic random access memory, a complex programmable logic device, an Ethernet PHY chip, a universal asynchronous receiver-transmitter, a temperature sensor, a charged erasable programmable read-only memory, a real-time clock chip, a nonvolatile flash memory, a power management module, a mSATA solid state disk, an XMC connector, a PMC connector and a connector;
the CPCI bus interface is connected with a PCIe-to-PCI/PCI-X bridge chip, the PCIe-to-PCI/PCI-X bridge chip is connected with a central processing unit, the PCIe-to-PCI/PCI-X bridge chip realizes the conversion between a PCIe bus and a PCI/PCI-X bus, and the central processing unit realizes a PCIe bus interface;
the central processing unit is connected with a PCIe-to-PCI/PCI-X bridge chip, a PCIe Switch, a high-speed dynamic random access memory, a complex programmable logic device, an Ethernet PHY chip, a universal asynchronous transceiver, a temperature sensor, a charged erasable programmable read-only memory, a real-time clock chip, a nonvolatile flash memory and a power management module to realize overall control;
PCIe Switch, connect central processing unit, PCIe to PCI/PCI-X bridge, Ethernet PHY chip, PMC connector, realize the switching between multiple interfaces and the central processing unit;
the high-speed dynamic random access memory is connected with the central processing unit and is used for realizing the caching of programs, data and intermediate results;
the complex programmable logic device is connected with the CPCI bus interface, the central processing unit and the nonvolatile memory to realize the control of partial functions;
the Ethernet PHY chip is connected with the CPCI bus interface, the central processing unit and the connector and is used for realizing the Ethernet communication of the central processing unit;
the universal asynchronous transceiver is connected with the CPCI bus interface, the central processing unit and the connector and is used for realizing the serial port communication function of the central processing unit;
the temperature sensor is connected with the central processing unit and used for monitoring the temperature of the board card;
the electrified erasable programmable read-only memory is connected with the central processing unit and used for data storage;
the real-time clock chip is connected with the central processing unit and is used for providing a clock signal for the central processing unit;
the nonvolatile flash memory is connected with the central processing unit and the complex programmable logic device and is used for storing data;
the power management module is connected with a CPCI bus interface, a PCIe-to-PCI/PCI-X bridge chip, a PCIe Switch, a central processing unit, a high-speed dynamic random access memory, an Ethernet PHY chip, a temperature sensor, a complex programmable logic device, a real-time clock chip, a universal asynchronous receiver-transmitter, a nonvolatile flash memory and a connector and is used for providing required voltage for the high-performance main control board with the 6U CPCI specification;
the mSATA solid state disk is connected with the central processing unit and used for large-capacity data storage;
the XMC connector is connected with the central processing unit and is used for realizing the connection between the central processing unit and the expansion card;
the PMC connector is connected with the PCIe-to-PCI/PCI-X bridge chip and the CPCI bus interface and is used for realizing the connection of the expansion card, the PCIe-to-PCI/PCI-X bridge chip and the CPCI bus interface;
and the connector assembly is connected with the universal asynchronous transceiver and the Ethernet PHY chip and is a connector for external communication of the high-performance main control board with the 6U CPCI specification.
2. The 6U CPCI specification high performance master control board of claim 1, wherein:
the PCIe-to-PCI/PCI-X bridge requires: supports X4 PCIe Gen1.0; the PCI bus is 33/66/133MHz, 32/64bit, and supports 6 PCI; the bridge piece supports Forward and reverse modes and transparent and non-transparent bridge modes;
the bridge chip is mounted on PCIe2 of the CPU, and PCIe2 is configured in a x2 Gen2.0 PCIe mode;
the non-volatile flash memory requires: the minimum of the pages is 8KB, and the requirement of the size of the reserved space of each page is larger than 344 Bytes; the ONFI2.2 asynchronous interface is supported, and the bit width of a data address bus is 8 bits; the Row space can not exceed 21bit, so when 32GB is selected, 2 targets are required for Flash, and the capacity of each Target is 16 GB;
the high-speed dynamic random access memory requires: the ECC function is satisfied; the frequency requires 1600MHz, the data bit width is 16 bit; two Bank designs are adopted, each Bank has 4GB, and the minimum capacity requirement is 4 GB.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020025656.XU CN210864564U (en) | 2020-01-07 | 2020-01-07 | High-performance main control board with 6U CPCI specification |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020025656.XU CN210864564U (en) | 2020-01-07 | 2020-01-07 | High-performance main control board with 6U CPCI specification |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210864564U true CN210864564U (en) | 2020-06-26 |
Family
ID=71287594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020025656.XU Active CN210864564U (en) | 2020-01-07 | 2020-01-07 | High-performance main control board with 6U CPCI specification |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210864564U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112462911A (en) * | 2020-11-18 | 2021-03-09 | 扬州船用电子仪器研究所(中国船舶重工集团公司第七二三研究所) | High-density board card control framework |
| CN113868177A (en) * | 2021-09-03 | 2021-12-31 | 中国科学院计算技术研究所 | Embedded intelligent computing system with easily-expanded scale |
| CN113886304A (en) * | 2021-09-06 | 2022-01-04 | 浪潮集团有限公司 | PXIe measurement and control backboard |
-
2020
- 2020-01-07 CN CN202020025656.XU patent/CN210864564U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112462911A (en) * | 2020-11-18 | 2021-03-09 | 扬州船用电子仪器研究所(中国船舶重工集团公司第七二三研究所) | High-density board card control framework |
| CN112462911B (en) * | 2020-11-18 | 2023-11-21 | 扬州船用电子仪器研究所(中国船舶重工集团公司第七二三研究所) | High-density board card control architecture |
| CN113868177A (en) * | 2021-09-03 | 2021-12-31 | 中国科学院计算技术研究所 | Embedded intelligent computing system with easily-expanded scale |
| CN113868177B (en) * | 2021-09-03 | 2023-03-24 | 中国科学院计算技术研究所 | Embedded intelligent computing system with easily-expanded scale |
| CN113886304A (en) * | 2021-09-06 | 2022-01-04 | 浪潮集团有限公司 | PXIe measurement and control backboard |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN210864564U (en) | High-performance main control board with 6U CPCI specification | |
| US7680968B2 (en) | Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM) | |
| CN101609442B (en) | Interface self-adapting method, device and system thereof | |
| CN102662903A (en) | Method for realizing hot-plug of PCIE equipment by CPLD or FPGA | |
| CN105335327A (en) | Reconfigurable/dual redundancy VPX3U signal processing carrier board based on Soc | |
| CN113489594A (en) | PCIE real-time network card based on FPGA module | |
| CN203179010U (en) | Storing device | |
| CN206788852U (en) | A kind of information processing system based on PowerPC+SRIO switching technologies | |
| CN103809920A (en) | Realizing method of ultra-large capacity solid state disk | |
| CN216527166U (en) | Large-capacity storage system | |
| CN218213983U (en) | Data computing system and server with built-in data computing system | |
| CN201820218U (en) | Host system and data transmission circuit | |
| CN110765065A (en) | System on chip | |
| CN203204494U (en) | Multifunctional high-stability slot structure and multifunctional card insertion module combined system | |
| CN217333334U (en) | Information processing board of 6U VPX framework | |
| US8909831B2 (en) | Logic device | |
| CN101853231B (en) | Mainboard, computer and storage device | |
| CN105630400A (en) | High-speed massive data storage system | |
| CN113824741A (en) | IIC device communication method, apparatus, device, system and medium | |
| CN204480237U (en) | A kind of connector, universal serial bus device and intelligent terminal | |
| CN112860624A (en) | Computer mainboard based on 2000-4 treater of soaring | |
| CN220543353U (en) | General signal processing module based on MPSOC | |
| CN216083550U (en) | Microcomputer system board based on high-performance embedded CPU | |
| CN216647349U (en) | Large-capacity memory and storage device | |
| CN219370267U (en) | Computer main control board of 6U VPX framework |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |