CN104132663A - FPGA based navigation computer co-processor - Google Patents

FPGA based navigation computer co-processor Download PDF

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Publication number
CN104132663A
CN104132663A CN201410228512.3A CN201410228512A CN104132663A CN 104132663 A CN104132663 A CN 104132663A CN 201410228512 A CN201410228512 A CN 201410228512A CN 104132663 A CN104132663 A CN 104132663A
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China
Prior art keywords
module
register
data
primary processor
asynchronous serial
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Inventor
王松
刘海涛
阙兴涛
刘尔静
汪守利
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Aerospace Long March Launch Vehicle Technology Co Ltd
Beijing Institute of Telemetry Technology
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Aerospace Long March Launch Vehicle Technology Co Ltd
Beijing Institute of Telemetry Technology
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Priority to CN201410228512.3A priority Critical patent/CN104132663A/en
Publication of CN104132663A publication Critical patent/CN104132663A/en
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01CMEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
    • G01C21/00Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
    • G01C21/20Instruments for performing navigational calculations

Abstract

The invention discloses an FPGA based navigation computer co-processor, which can complete real-time acquisition and processing of high-precision inertia measurement unit IMU signals, double buffering of navigation parameters and external instructions, and full duplex asynchronous serial communication. The FPGA co-processor involved in the invention overcomes the disadvantages of traditional embedded navigation computers in terms of volume, development complexity and versatility, the task distribution between the co-processor and a main processor is balanced, and the interface relationship is clear, thus greatly improving the flexibility and versatility of navigation computer development, and reducing the complexity of navigation computer system software development.

Description

A kind of navigational computer coprocessor based on FPGA
Technical field
The present invention relates to a kind of navigational computer coprocessor based on FPGA, belong to inertial navigation field.
Background technology
In recent years, high speed development along with electronic technology and inertial technology, strapdown inertial navitation system (SINS) is widely used in many tactics, strategic arms model with advantages such as its low cost, small size, high-performance, for significant contribution has been made in national defense construction, the research of high-performance strapdown inertial navitation system (SINS) and application also become one of important development direction of inertial technology gradually.Navigational computer is the core cell that guarantees inertial navigation system real-time and precision, the functions such as main data acquisition, time synchronized, navigation calculating and navigational parameter output.
Traditional navigational computer volume based on special purpose computer or industrial computer is large, complex structure, and versatility is not good enough.In order to meet miniaturization, high-precision applications requirement, the Core Feature such as the task scheduling of the navigational computer based on embedded system and navigation calculating completes by primary processor at present, often adopt two primary processor structures, DSP/ single-chip microcomputer for example, DSP/DSP, DSP/CPLD, DSP/FPGA etc., being realized by DSP primary processor of navigational computer, the limited external interface of the concentrations of task and primary processor has significantly increased the complexity of Design of System Software, also reliability and the versatility of system have been reduced, cause such navigational computer not to be suitable for data interaction amount large, the high precision navigation field of requirement of real-time harshness.
Summary of the invention
Problem to be solved by this invention: overcome prior art deficiency, a kind of navigational computer coprocessor based on FPGA is provided, by Design Navigation computing machine coprocessor, complete the Real-time Collection of high precision IMU signal and double buffering, the full duplex asynchronous serial communication of processing, navigational parameter and external command, effectively improve the performance of navigational computer.
Technical solution of the present invention:
A navigational computer coprocessor based on FPGA, implementation is as follows:
FPGA coprocessor completes the collection of IMU signal and controls and process, and IMU signal is sent to primary processor; The IMU signal that primary processor sends according to FPGA completes navigation and calculates, and the navigational parameter that navigation is calculated is sent to main control computer and other peripheral hardwares by FPGA coprocessor; Main control computer and other peripheral hardwares are sent to primary processor by FPGA by steering order and supplementary; FPGA coprocessor control AD conversion unit completes the analog to digital conversion of IMU signal, and multichannel IMU simulating signal is converted to digital signal; IMU signal comprises 3 road high-precision optical fiber gyro signals, 3 road high-precision accelerometer signals, 1 road temperature signal, and corresponding analog to digital converter way is 7 tunnels;
Wherein FPGA coprocessor comprises: IMU signal acquisition module, IMU signal processing module, communication protocol arrange module, send buffer module, receive buffer module, asynchronous serial transceiver module;
IMU signal acquisition module is carried out initialization to analog to digital converter, No. 7 analog to digital converters is carried out synchronously, and certain analog to digital conversion frequency is set; The inquiry of IMU signal acquisition module is the transition status of No. 1 analog to digital converter wherein, after inquiring analog to digital conversion, produces peek sequential, obtains the digital signal of No. 7 analog to digital converters, and is sent to IMU signal processing module;
IMU signal processing module carries out the processing of second order IIR low-pass digital filter to the translation data of No. 7 analog to digital converters and obtains filtered IMU digital signal, and the navigation that generation equates with analog to digital conversion frequency is calculated markers in order to trigger primary processor external interrupt, primary processor produces address signal and read signal in interrupt service routine, once read in the complete IMU digital signal of analog to digital conversion, complete navigation and calculate, and the target while calculating of navigating is aimed at;
Communication protocol arranges module the baud rate of asynchronous serial communication and parity checking is arranged;
The navigational parameter that transmission buffer module mails to main control computer and other peripheral hardwares to the complete preparation of primary processor navigation calculating cushions, and waits for that asynchronous serial transceiver module completes Parallel-serial convert;
Receive buffer module and cushion completed the serial command from main control computer and other peripheral hardwares and the auxiliary parameter of going here and there and changing by asynchronous serial transceiver module, wait for reading of primary processor;
Asynchronous serial transceiver module is sent to main control computer and other peripheral hardwares by sending primary processor in buffer module after the navigational parameter sending between main control computer and other peripheral hardwares carries out Parallel-serial convert; And the asynchronous serial data that receives main control computer and other peripheral hardwares and be sent to primary processor is carried out to serial parallel conversion and deliver to reception buffer module.
Described navigation is designated as the high level of a reference clock width while calculating, frequency is 1KHz, and reference clock frequency is 14.7456MHz.
The described second order IIR low-pass digital filter disposal route of carrying out is specific as follows:
Second order iir filter recursion equation is:
y(n)=a 0x(n)+a 1x(n-1)+a 2x(n-2)-b 1y(n-1)-b 2y(n-2),n=2,3,4,...,N
Wherein, the sampled value that x (n) is current time, the sampled value that x (n-1) is previous moment, x (n-2) is the sampled value of previous moment more, y (n) is the output valve of current time wave filter, y (n-1) is the output valve of previous moment wave filter, and y (n-2) is the output valve of previous moment wave filter more.
Described communication protocol arranges module and comprises baud rate configuration register, parity checking configuration register; It is as follows that communication protocol arranges the implementation that module arranges the baud rate of asynchronous serial communication and parity checking:
The peripheral hardware address that baud rate configuration register, parity checking configuration register are mapped as primary processor is expressed as 1001,1010 with binary code, primary processor writes the configuration data of baud rate and parity checking toward peripheral hardware address, communication protocol arranges module and uses address signal and the write signal edge of primary processor that configuration data is latched, Reconfigurations register, completes the setting of communication protocol;
The concrete numerical value of the configuration data of baud rate and parity checking is: reference clock 14.7456MHz adds 1 divided by the value of baud rate configuration register and is asynchronous serial communication baud rate; Parity checking configuration register Bit0 value is that ' 1 ' expression parity checking enables, and ' 0 ' represents that parity checking does not enable; When parity checking enables, parity checking configuration register Bit1 value is ' 1 ' expression odd, and ' 0 ' represents even parity check.
Described transmission buffer module comprises transmission buffer register, status register; The peripheral hardware address that transmission buffer register, status register are mapped as primary processor is expressed as 1000,1011 with binary code;
The specific implementation that transmission buffer module is carried out data buffering is as follows:
When asynchronous serial data sends, primary processor writes navigational parameter to be sent continuously toward sending buffer register, send buffer module and deposit a navigational parameter for the treatment of that sends buffer register the transmission FIFO of 512 bytes in, when asynchronous serial transceiver module sends the state free time, send buffer module and produce to send that FIFO buffer cell is read sequential and asynchronous serial transceiver module is write sequential, outgoing data is taken out and write asynchronous serial transceiver module transmitter register from sending FIFO buffer cell, by asynchronous serial transceiver module, completed the Parallel-serial convert of data; The Bit1 of status register sends the state of FIFO in order to sign, ' 1 ' represents to send FIFO non-NULL, and it is empty that ' 0 ' expression sends FIFO.
Described reception buffer module comprises reception buffer register, status register; The peripheral hardware address that reception buffer register, status register are mapped as primary processor is expressed as 1000,1011 with binary code;
The specific implementation that reception buffer module is carried out data buffering is as follows:
When asynchronous serial data receives, asynchronous serial transceiver module produces reception effective marker after completing serial parallel conversion, the complete data of the parallel conversion of serial are taken out and write from asynchronous serial transceiver module receive FIFO buffer cell, receive buffer module and deposit in and receive buffer register wait primary processor and read receiving data in FIFO buffer cell; The Bit0 of status register receives the state of FIFO in order to sign, ' 1 ' represents to receive FIFO non-NULL, and it is empty that ' 0 ' expression receives FIFO; After all data in reception FIFO buffer cell are read, Bit0 in status register is set to 0.
Described asynchronous serial transceiver module implementation is as follows:
(1) during Parallel-serial convert, if asynchronous serial transceiver module transmitter register is written into data to be sent, the clock of baud rate configuration register setting of take is benchmark, complete primary processor and to main control computer and other peripheral hardwares, send the parallel-serial conversion of data, serial data format is 1 start bit, 8 data bit, 1 bit parity check position, 1 position of rest, while sending idle condition, is output as high level;
(2) when serial walks abreast conversion, asynchronous serial transceiver module be take the level state that the clock of baud rate configuration register setting is benchmaring external series input signal, when low level being detected, think the start bit of serial input signals, order receives after 8 data bit and 1 parity check bit, judge whether current level is high level, if high level is stop bit, current byte receives; Otherwise restart to detect low level judgement start bit; Complete after the parallel conversion of serial, data are put into receiving register, put receiving register sign simultaneously, wait for and accept reading of FIFO buffer cell.
The present invention compared with prior art tool has the following advantages:
(1) the present invention has realized Real-time Collection and the processing of high precision IMU signal, and produce markers for the control of the computation period that navigates, and improved the operational efficiency of navigational computer primary processor, alleviated the task scheduling pressure of primary processor, efficiency is higher, and reliability is stronger.
(2) the present invention is based on FPGA has realized communication protocol and module is set, sends buffer module, receives buffer module, universal asynchronous serial transceiver module, avoid using special-purpose asynchronous serial communication protocol change-over circuit, volume and the cost of navigational computer have been reduced, make navigational computer primary processor interrupt carrying out information interaction without frequent response external simultaneously, improve the counting yield of primary processor, also saved its valuable external interrupt resource.
(3) the present invention is based on the function that FPGA completes navigational computer coprocessor, completed the science division of labor in functional module of itself and primary processor, make the two respectively get the chief, give full play to advantage separately.Because all peripheral hardwares all carry out information interaction by FPGA coprocessor and primary processor, therefore navigational computer interface relationship is very simple, clear, improve dirigibility and the versatility of navigational computer exploitation, reduced the complexity of navigation computer system software development.
Accompanying drawing explanation
Fig. 1 is that the present invention forms structural representation.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
As shown in Figure 1, a kind of navigational computer coprocessor based on FPGA of the present invention, implementation is as follows:
FPGA coprocessor completes the acquisition and processing of IMU signal, and IMU signal is sent to primary processor; The IMU signal that primary processor sends according to FPGA completes navigation and calculates, and the navigational parameter that navigation is calculated is sent to main control computer and other peripheral hardwares by FPGA coprocessor; Main control computer and other peripheral hardwares are sent to primary processor by FPGA by steering order and supplementary.
FPGA coprocessor control AD conversion unit completes (AD conversion unit comprises multichannel analog to digital converter) analog to digital conversion of IMU signal, and 7 road IMU simulating signals are converted to digital signal; IMU signal comprises 3 road high-precision optical fiber gyro signals, 3 road high-precision accelerometer signals, 1 road temperature signal, corresponding analog to digital converter way is high-precision optical fiber gyro signal, high-precision accelerometer signal, temperature signal way sum, and AD conversion unit comprises No. 7 analog to digital converters.
Wherein FPGA coprocessor comprises: IMU (Inertial Measurement Unit) signal acquisition module, IMU signal processing module, communication protocol arrange module, send buffer module, receive buffer module, asynchronous serial transceiver module.
IMU signal acquisition module is carried out initialization to analog to digital converter, No. 7 analog to digital converters is carried out synchronously, and certain analog to digital conversion frequency is set; The inquiry of IMU signal acquisition module is the transition status of No. 1 analog to digital converter wherein, after inquiring analog to digital conversion, produces peek sequential, obtains the digital signal of multichannel analog to digital converter, and is sent to IMU signal processing module.
IMU signal processing module carries out the processing of second order IIR (endless unit impulse response) low-pass digital filter to the translation data of No. 7 analog to digital converters and obtains filtered IMU digital signal, and the navigation calculating markers that generation equates with analog to digital conversion frequency (is designated as the high level of a reference clock width during navigation calculating, frequency is 1KHz, reference clock frequency is 14.7456MHz) in order to trigger primary processor external interrupt, primary processor produces address signal and read signal in interrupt service routine, once read in the complete IMU digital signal numeral of analog to digital conversion, completing navigation calculates, and the target while calculating of navigating is aimed at,
Second order IIR low-pass digital filter disposal route is specific as follows:
Second order iir filter recursion equation is:
y(n)=a 0x(n)+a 1x(n-1)+a 2x(n-2)-b 1y(n-1)-b 2y(n-2),n=2,3,4,...,N
Wherein, the sampled value that x (n) is current time, the sampled value that x (n-1) is previous moment, x (n-2) is the sampled value of previous moment more, y (n) is the output valve of current time wave filter, y (n-1) is the output valve of previous moment wave filter, and y (n-2) is the output valve of previous moment wave filter more.
Communication protocol arranges module the baud rate of asynchronous serial communication and parity checking is arranged;
Communication protocol arranges module and comprises baud rate configuration register, parity checking configuration register; It is as follows that communication protocol arranges the implementation that module arranges the baud rate of asynchronous serial communication and parity checking:
The peripheral hardware address that baud rate configuration register, parity checking configuration register are mapped as primary processor is expressed as 1001,1010 with binary code, primary processor writes the configuration data of baud rate and parity checking toward peripheral hardware address, communication protocol arranges module and uses address signal and the write signal edge of primary processor that configuration data is latched, Reconfigurations register, can communicate the setting of agreement;
The concrete numerical value of the configuration data of baud rate and parity checking is: reference clock 14.7456MHz adds 1 divided by the value of baud rate configuration register and is asynchronous serial communication baud rate; Parity checking configuration register Bit0 value is that ' 1 ' expression parity checking enables, and ' 0 ' represents that parity checking does not enable; When parity checking enables, parity checking configuration register Bit1 value is ' 1 ' expression odd, and ' 0 ' represents even parity check.
The navigational parameter that transmission buffer module mails to main control computer and other peripheral hardwares to the complete preparation of primary processor navigation calculating cushions, and waits for that asynchronous serial transceiver module completes Parallel-serial convert;
Send buffer module and comprise transmission buffer register, status register; The peripheral hardware address that transmission buffer register, status register are mapped as primary processor is expressed as 1000,1011 with binary code;
The specific implementation that transmission buffer module is carried out data buffering is as follows:
When asynchronous serial data sends, primary processor writes navigational parameter to be sent continuously toward sending buffer register, send buffer module and deposit a navigational parameter for the treatment of that sends buffer register the transmission FIFO (first-in first-out storehouse) of 512 bytes in, when asynchronous serial transceiver module sends the state free time, send buffer module and produce to send that FIFO buffer cell is read sequential and asynchronous serial transceiver module is write sequential, outgoing data is taken out and writes asynchronous serial transceiver module transmitter register from sending FIFO buffer cell, by asynchronous serial transceiver module, completed the Parallel-serial convert of data, the Bit1 of status register sends the state of FIFO in order to sign, ' 1 ' represents to send FIFO non-NULL, and it is empty that ' 0 ' expression sends FIFO.
Receive buffer module and cushion completed the serial command from main control computer and other peripheral hardwares and the auxiliary parameter of going here and there and changing by asynchronous serial transceiver module, wait for reading of primary processor;
Receive buffer module and comprise reception buffer register, status register; The peripheral hardware address that reception buffer register, status register are mapped as primary processor is expressed as 1000,1011 with binary code;
The specific implementation that reception buffer module is carried out data buffering is as follows:
When asynchronous serial data receives, asynchronous serial transceiver module produces reception effective marker after completing serial parallel conversion, the complete data of the parallel conversion of serial are taken out and write from asynchronous serial transceiver module receive FIFO buffer cell, receive buffer module and deposit in and receive buffer register wait primary processor and read receiving data in FIFO buffer cell; The Bit0 of status register receives the state of FIFO in order to sign, ' 1 ' represents to receive FIFO non-NULL, and it is empty that ' 0 ' expression receives FIFO; After all data in reception FIFO buffer cell are read, Bit0 in status register is set to 0.
Asynchronous serial transceiver module is sent to main control computer and other peripheral hardwares by sending primary processor in buffer module after the navigational parameter sending between main control computer and other peripheral hardwares carries out Parallel-serial convert; And occur to carry out serial parallel conversion to the data of primary processor and deliver to reception buffer module receiving main control computer and other peripheral hardwares.
Asynchronous serial transceiver module implementation is as follows:
(1) during Parallel-serial convert, if asynchronous serial transceiver module transmitter register is written into data to be sent, the clock of baud rate configuration register setting of take is benchmark, complete primary processor and to main control computer and other peripheral hardwares, send the parallel-serial conversion of data, serial data format is 1 start bit (low level), 8 data bit, 1 bit parity check position (optional), 1 position of rest (high level), while sending idle condition, is output as high level;
(2) when serial walks abreast conversion, asynchronous serial transceiver module be take the level state that the clock of baud rate configuration register setting is benchmaring external series input signal, when low level being detected, think the start bit of serial input signals, order receives after 8 data bit (optional) and 1 parity check bit, judge whether current level is high level, if high level is stop bit, current byte receives; Otherwise restart to detect low level judgement start bit; Complete after the parallel conversion of serial, data are put into receiving register, put receiving register sign simultaneously, wait for and accept reading of FIFO buffer cell.
With a specific embodiment, further illustrate the course of work of the present invention and principle of work below:
In the present embodiment, the navigational computer of take based on TMS320C6713DSP/Cyclone II FPGA is example.
The function that FPGA coprocessor completes comprises the Real-time Collection of high precision IMU signal and the double buffering of processing module, navigational parameter and external command, full duplex asynchronous serial communication module, and the information interaction of itself and navigational computer DSP primary processor is undertaken by the external memory interface (EMIF) of DSP.Wherein, IMU signal comprises 3 road high-precision optical fiber gyro signals, 3 road high-precision accelerometer signals and 1 road temperature signal, amounts to 7 tunnel simulating signals.
The present invention uses 24,7 tunnel high precision analog-digital converter ADS1210 that IMU output signal and temperature sensor output signal are gathered, processed.Collection and the treatment step of high precision IMU signal are as follows:
(1) after system powers on, FPGA carries out initialization to IMU signal mode number converter, simulating signal is set and is input as bipolarity input.The work clock of ADS1210 is 8MHz, and " Turbo Mode Rate " that configuration register is set is 16, and " Decimation Ratio " is 249, and analog-digital conversion data rate is 1KHz.The synchronizing signal DSYNC of 7 road ADS1210 is set to low level simultaneously, and 5us postposition is high level, completes the synchronous of 7 road ADS1210.
(2) FPGA inquires about the transition status sign busy signal of 1 road ADS1210, when busy is low level, show that analog-to-digital conversion is complete, produce peek sequential, deposit the data of 7 road analog-digital converters in FPGA internal storage region, and each circuit-switched data is carried out to second order IIR low-pass digital filter and process.
Second order iir filter recursion equation is,
y(n)=a 0x(n)+a 1x(n-1)+a 2x(n-2)-b 1y(n-1)-b 2y(n-2)
Analog-digital conversion data rate is 1KHz, and it is 80Hz that second order IIR low-pass digital filter cutoff frequency is set, and has a 0=0.0461318, a 1=0.0922636, a 2=0.0461318, b 1=-1.307285, b 2=0.4918122.Because FPGA can not directly carry out floating-point operation, above-mentioned coefficient is carried out to 16 word lengths and quantize, wherein decimal accounts for 14, and the binary number after corresponding quantification is respectively:
a 0=0000001011110011,a 1=0000010111100110,a 2=0000001011110011,b 1=1010110001010110,b 2=0001111101111001
FPGA completes after the second order IIR low-pass digital filter of 7 tunnel analog-to-digital conversion data, produces the high level of a basic pulse width, and frequency is 1KHz, as navigation, calculates markers.Primary processor responds the external interrupt that this markers triggers, and once reads calculatings of navigate of analog-to-digital conversion data, and target aligning while navigating calculating.
The double buffering of navigational parameter and external command, full duplex asynchronous serial communication, comprise sending/receiving buffer register, baud rate configuration register, parity checking configuration register, status register, the peripheral hardware address that is mapped as primary processor is respectively 1000,1001,1010,1011 with binary code representation, and register address and functional description are as following table:
(1) primary processor writes 00000011 in address 1010, is set to odd, in address 1001, writes 00001111, and it is 14.7456MHz/ (15+1) that baud rate is set, and is 921600bps.
(2) when asynchronous serial data sends, primary processor 1000 writes data to be sent continuously toward address, FPGA deposits the outgoing data that sends buffer register to send FIFO in, when asynchronous serial transceiver module transmitter register is empty, automatically produce and send that FIFO buffer cell is read sequential and asynchronous serial transceiver module is write sequential, outgoing data is taken out and by writing asynchronous serial transceiver module transmitter register, completes the parallel-to-serial conversion of data from sending FIFO buffer cell.
(3) when asynchronous serial data receives, asynchronous serial transceiver module produces receiving register full scale will after completing serial parallel conversion, the asynchronous serial transceiver module that triggers FPGA is read the sequential of writing of sequential and reception FIFO buffer cell, serial-to-parallel is changed to complete data and from asynchronous serial transceiver module receiving register, take out and write reception FIFO buffer cell, status register Bit0 is put to 1 simultaneously.Primary processor at one's leisure between query State register, status register Bit0 is 1 o'clock, primary processor reads reception buffer register, FPGA deposits the data in reception FIFO buffer cell in reception buffer register and waits for that primary processor reads, and after all data in reception FIFO buffer cell are read, status register Bit0 is set to 0.
(4) when asynchronous serial communication module completes Parallel-serial convert, if asynchronous serial transceiver module transmitter register is written into data to be sent, the clock of baud rate configuration register setting of take is benchmark, complete data also-string conversion, data layout is 1 start bit (low level), 8 data bit, 1 bit parity check position (optional), 1 position of rest (high level), while sending idle condition, is output as high level.When asynchronous serial transceiver module completes serial-to-parallel conversion, it is benchmaring external series input signal ground level state that asynchronous serial transceiver module be take the clock of baud rate configuration register setting, when low level being detected, think serial input signals ground start bit, order receives after 8 data bit and 1 parity check bit, judges whether current level is high level.If high level is stop bit, current byte receives, otherwise restarts to detect low level judgement start bit.Complete after serial-to-parallel conversion, data are put into receiving register, put receiving register sign simultaneously, wait for and accept reading of FIFO buffer cell.
The content not being described in detail in instructions of the present invention belongs to those skilled in the art's known technology.

Claims (7)

1. the navigational computer coprocessor based on FPGA, is characterized in that implementation is as follows:
FPGA coprocessor completes the collection of IMU signal and controls and process, and IMU signal is sent to primary processor; The IMU signal that primary processor sends according to FPGA completes navigation and calculates, and the navigational parameter that navigation is calculated is sent to main control computer and other peripheral hardwares by FPGA coprocessor; Main control computer and other peripheral hardwares are sent to primary processor by FPGA by steering order and supplementary; FPGA coprocessor control AD conversion unit completes the analog to digital conversion of IMU signal, and multichannel IMU simulating signal is converted to digital signal; IMU signal comprises 3 road high-precision optical fiber gyro signals, 3 road high-precision accelerometer signals, 1 road temperature signal, and corresponding analog to digital converter way is 7 tunnels;
Wherein FPGA coprocessor comprises: IMU signal acquisition module, IMU signal processing module, communication protocol arrange module, send buffer module, receive buffer module, asynchronous serial transceiver module;
IMU signal acquisition module is carried out initialization to analog to digital converter, No. 7 analog to digital converters is carried out synchronously, and certain analog to digital conversion frequency is set; The inquiry of IMU signal acquisition module is the transition status of No. 1 analog to digital converter wherein, after inquiring analog to digital conversion, produces peek sequential, obtains the digital signal of No. 7 analog to digital converters, and is sent to IMU signal processing module;
IMU signal processing module carries out the processing of second order IIR low-pass digital filter to the translation data of No. 7 analog to digital converters and obtains filtered IMU digital signal, and the navigation that generation equates with analog to digital conversion frequency is calculated markers in order to trigger primary processor external interrupt, primary processor produces address signal and read signal in interrupt service routine, once read in the complete IMU digital signal of analog to digital conversion, complete navigation and calculate, and the target while calculating of navigating is aimed at;
Communication protocol arranges module the baud rate of asynchronous serial communication and parity checking is arranged;
The navigational parameter that transmission buffer module mails to main control computer and other peripheral hardwares to the complete preparation of primary processor navigation calculating cushions, and waits for that asynchronous serial transceiver module completes Parallel-serial convert;
Receive buffer module and cushion completed the serial command from main control computer and other peripheral hardwares and the auxiliary parameter of going here and there and changing by asynchronous serial transceiver module, wait for reading of primary processor;
Asynchronous serial transceiver module is sent to main control computer and other peripheral hardwares by sending primary processor in buffer module after the navigational parameter sending between main control computer and other peripheral hardwares carries out Parallel-serial convert; And the asynchronous serial data that receives main control computer and other peripheral hardwares and be sent to primary processor is carried out to serial parallel conversion and deliver to reception buffer module.
2. a kind of navigational computer coprocessor based on FPGA according to claim 1, is characterized in that: described navigation is designated as the high level of a reference clock width while calculating, frequency is 1KHz, and reference clock frequency is 14.7456MHz.
3. a kind of navigational computer coprocessor based on FPGA requiring according to right 1, is characterized in that: described in to carry out second order IIR low-pass digital filter disposal route specific as follows:
Second order iir filter recursion equation is:
y(n)=a 0x(n)+a 1x(n-1)+a 2x(n-2)-b 1y(n-1)-b 2y(n-2),n=2,3,4,...,N
Wherein, the sampled value that x (n) is current time, the sampled value that x (n-1) is previous moment, x (n-2) is the sampled value of previous moment more, y (n) is the output valve of current time wave filter, y (n-1) is the output valve of previous moment wave filter, and y (n-2) is the output valve of previous moment wave filter more.
4. according to right 1, require described a kind of navigational computer coprocessor based on FPGA, it is characterized in that: described communication protocol arranges module and comprises baud rate configuration register, parity checking configuration register; It is as follows that communication protocol arranges the implementation that module arranges the baud rate of asynchronous serial communication and parity checking:
The peripheral hardware address that baud rate configuration register, parity checking configuration register are mapped as primary processor is expressed as 1001,1010 with binary code, primary processor writes the configuration data of baud rate and parity checking toward peripheral hardware address, communication protocol arranges module and uses address signal and the write signal edge of primary processor that configuration data is latched, Reconfigurations register, completes the setting of communication protocol;
The concrete numerical value of the configuration data of baud rate and parity checking is: reference clock 14.7456MHz adds 1 divided by the value of baud rate configuration register and is asynchronous serial communication baud rate; Parity checking configuration register Bit0 value is that ' 1 ' expression parity checking enables, and ' 0 ' represents that parity checking does not enable; When parity checking enables, parity checking configuration register Bit1 value is ' 1 ' expression odd, and ' 0 ' represents even parity check.
5. according to right 1, require described a kind of navigational computer coprocessor based on FPGA, it is characterized in that: described transmission buffer module comprises transmission buffer register, status register; The peripheral hardware address that transmission buffer register, status register are mapped as primary processor is expressed as 1000,1011 with binary code;
The specific implementation that transmission buffer module is carried out data buffering is as follows:
When asynchronous serial data sends, primary processor writes navigational parameter to be sent continuously toward sending buffer register, send buffer module and deposit a navigational parameter for the treatment of that sends buffer register the transmission FIFO of 512 bytes in, when asynchronous serial transceiver module sends the state free time, send buffer module and produce to send that FIFO buffer cell is read sequential and asynchronous serial transceiver module is write sequential, outgoing data is taken out and write asynchronous serial transceiver module transmitter register from sending FIFO buffer cell, by asynchronous serial transceiver module, completed the Parallel-serial convert of data; The Bit1 of status register sends the state of FIFO in order to sign, ' 1 ' represents to send FIFO non-NULL, and it is empty that ' 0 ' expression sends FIFO.
6. according to right 1, require described a kind of navigational computer coprocessor based on FPGA, it is characterized in that: described reception buffer module comprises reception buffer register, status register; The peripheral hardware address that reception buffer register, status register are mapped as primary processor is expressed as 1000,1011 with binary code;
The specific implementation that reception buffer module is carried out data buffering is as follows:
When asynchronous serial data receives, asynchronous serial transceiver module produces reception effective marker after completing serial parallel conversion, the complete data of the parallel conversion of serial are taken out and write from asynchronous serial transceiver module receive FIFO buffer cell, receive buffer module and deposit in and receive buffer register wait primary processor and read receiving data in FIFO buffer cell; The Bit0 of status register receives the state of FIFO in order to sign, ' 1 ' represents to receive FIFO non-NULL, and it is empty that ' 0 ' expression receives FIFO; After all data in reception FIFO buffer cell are read, Bit0 in status register is set to 0.
7. a kind of navigational computer coprocessor based on FPGA requiring according to right 1, is characterized in that: described asynchronous serial transceiver module implementation is as follows:
(1) during Parallel-serial convert, if asynchronous serial transceiver module transmitter register is written into data to be sent, the clock of baud rate configuration register setting of take is benchmark, complete primary processor and to main control computer and other peripheral hardwares, send the parallel-serial conversion of data, serial data format is 1 start bit, 8 data bit, 1 bit parity check position, 1 position of rest, while sending idle condition, is output as high level;
(2) when serial walks abreast conversion, asynchronous serial transceiver module be take the level state that the clock of baud rate configuration register setting is benchmaring external series input signal, when low level being detected, think the start bit of serial input signals, order receives after 8 data bit and 1 parity check bit, judge whether current level is high level, if high level is stop bit, current byte receives; Otherwise restart to detect low level judgement start bit; Complete after the parallel conversion of serial, data are put into receiving register, put receiving register sign simultaneously, wait for and accept reading of FIFO buffer cell.
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