CN101206561B - Special arithmetic unit ALU - Google Patents
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Abstract
The invention discloses a special arithmetic logic unit (ALU), comprising 12 48-bit arithmetic or logic modules of a summer, a subtracter, a multiplier (1), a multiplier (2), a divider, logarithm int, a multiplier (3), a multiplier (4), using absolute value, an anti-creeper, taking positive number, taking negative number. The special arithmetic logic unit (ALU) is operated by instructions the length of which is 27 bits including 5 bits for opecode, 6 bits for source 1 address, 6 bits for source 2 address and 10 bits for destination address. Each instruction corresponds to an arithmetic or logic operation. ALU can realize the functions required for electric energy meter design by means of external program, particularly for multi-functional high-performance electric energy meter design, with a simple structure and a high speed.
Description
Technical field
The present invention relates to a kind of special arithmetic unit ALU (arithmetic logical unti), relate in particular to a kind of being used in the electric energy computation chip to realize the special arithmetic unit ALU of electric energy metrical designing requirement.
Background technology
When electric energy computation chip function and performance reinforcement, if adopt algorithm to be mapped directly to the method for hardware, its implementation is that each data processing algorithm module directly is mapped as related circuit, and its needed hardware area can increase greatly along with the increase of the increase of computing unit quantity or signal Processing figure place.And algorithm is mapped directly to the method poor compatibility of hardware, in a single day changes to some extent on function or algorithm, just needs to increase module or modification circuit structure.Therefore must design a kind of new structure, adopt new method, satisfy the electric energy metrical designing requirement of multifunctional high-performance.
This new structure needs the arithmetic unit ALU of a special use, can carry out the arithmetic sum logical operation of 48 bit data fast, and it is simple that structure is wanted, and it is fast, relatively cheap that speed is wanted.
Summary of the invention
The object of the present invention is to provide a kind of special arithmetic unit ALU, it can realize in chip that electric energy metrical designs the function of the electric energy metrical designing requirement of desired function, particularly multifunctional high-performance.
For achieving the above object, the invention provides a kind of special arithmetic unit ALU, this special arithmetic unit ALU includes that totalizer, subtracter, multiplier 1, multiplier 2, divider, logarithm round, multiplier 3, multiplier 4, take absolute value, anti-shunt running, get positive number and get negative, totally 12 arithmetic or logical operation modules with 48 (bit) arithmetic capabilities.Special arithmetic unit ALU has two 48 data input pin to import the 1st data and the 2nd data respectively, one 48 data output end; Wherein totally 7 arithmetic or logical operation module link to each other with described two 48 data input pin for totalizer, subtracter, multiplier 1, multiplier 2, divider, multiplier 3 and multiplier 4, logarithm rounds, takes absolute value, anti-shunt running, get positive number with get negative totally 5 arithmetic or logical operation module link to each other with the data input pin of described input the 1st data, and above-mentioned 12 arithmetic or logical operation module all link to each other with one 48 data output end.Wherein multiplier 1 output " the 1st data " and " the 2nd data " is multiplied each other afterwards divided by 240 result; Multiplier 2 output " the 1st data " and " the 2nd data " is multiplied each other afterwards divided by 228 result; Multiplier 3 output " the 1st data " and " the 2nd data " is multiplied each other afterwards divided by 240 results of negate again; Multiplier 4 output " the 1st data " and " the 2nd data " multiplied result.This special arithmetic unit ALU is operated by instruction, and described instruction length is 27, and wherein operational code accounts for 5,1 address, source and accounts for 6,2 addresses, source and account for 6, destination address and account for 10.This special arithmetic unit ALU realizes that by the outside programming electric energy metrical designs the function of the electric energy metrical designing requirement of desired above-mentioned arithmetic or logical operation function, particularly multifunctional high-performance.
Special arithmetic unit ALU of the present invention, owing to adopted above-mentioned technical scheme, make it compared with prior art, have the following advantages and good effect: use a kind of special arithmetic unit ALU structure of the present invention to realize the chip of electric energy metrical designing requirement, compare with the arithmetic unit ALU that use is general, a lot of resources in the general arithmetic unit ALU are not used when realizing electric energy metrical multifunctional high-performance algorithm, cause the wasting of resources, but some electric energy metricals require distinctive algorithm not have, and do not have the ready-made ALU that can realize 48 bit arithmetics simultaneously on the market.Special arithmetic unit ALU of the present invention can realize in chip that electric energy metrical designs the function of the electric energy metrical designing requirement of desired function, particularly multifunctional high-performance, can carry out the arithmetic sum logical operation of 48 bit data fast, and simple in structure, speed is fast.
Description of drawings
By the description of a following embodiment to special arithmetic unit ALU of the present invention, can further understand purpose of the present invention, specific structural features and advantage in conjunction with its accompanying drawing.Wherein, accompanying drawing is:
Fig. 1 is the structural representation of special arithmetic unit ALU;
Fig. 2 is the instruction synoptic diagram of special arithmetic unit ALU;
Fig. 3 is the special-purpose double production line RISC architectural schematic.
Embodiment
See also shown in Figure 1ly, this is the structural representation of special arithmetic unit ALU.This special arithmetic unit ALU has two 48 data input pin, one 48 data output end.
The main modular that this special arithmetic unit ALU comprises is that totalizer, subtracter, multiplier 1, multiplier 2, divider, logarithm round, multiplier 3, multiplier 4, take absolute value, anti-shunt running, get positive number and get negative, totally 12 arithmetic or logical operation module.Wherein each module functions is as follows:
(1) totalizer (48+48): the result of output " the 1st data " and " the 2nd data " addition;
(2) subtracter (48-48): the result that output " the 1st data " and " the 2nd data " is subtracted each other;
(3) multiplier 1 (48 * 48): output " the 1st data " and " the 2nd data " is multiplied each other afterwards divided by 240 result;
(4) multiplier 2 (48 * 48): output " the 1st data " and " the 2nd data " is multiplied each other afterwards divided by 228 result;
(5) divider (48/48): the result that output " the 1st data " and " the 2nd data " is divided by;
(6) logarithm rounds (48): the log2 value of output " the 1st data " and the result who rounds;
(7) multiplier 3 (48 * 48): output " the 1st data " and " the 2nd data " is multiplied each other afterwards divided by 240 results of negate again;
(8) multiplier 4 (48 * 48): output " the 1st data " and " the 2nd data " multiplied result;
(9) (48) take absolute value: the result who takes absolute value of output " the 1st data ";
(10) anti-shunt running (48): the result of the anti-shunt running of output " the 1st data ";
(11) get positive number (48): the result who takes absolute value of output " the 1st data ";
(12) get negative (48): the result of the negate that takes absolute value of output " the 1st data ";
See also shown in Figure 2ly, this is the instruction synoptic diagram of special arithmetic unit ALU.27 of the instruction lengths of this special arithmetic unit ALU, wherein 5 of operational codes, 1 address, source account for 6,2 addresses, source and account for 6, destination address and account for 10.Wherein each several part represents function as follows:
(1) operational code (5): the indication arithmetic unit ALU is chosen a certain executable operations of 12 arithmetic or logical operation;
(2) 1 address, source (6): from 1 address, source, provide the operand " the 1st data " that is input to arithmetic unit ALU;
(3) 2 addresses, source (6): from 2 addresses, source, provide the operand " the 2nd data " that is input to arithmetic unit ALU;
(4) destination address (10): the output data of arithmetic unit ALU is stored in destination address;
See also shown in Figure 3ly, this is the special-purpose double production line RISC architectural schematic.
Therefore this double flow line is similarly 5 level structures, and every instruction all will be divided into 5 different the processing stage: obtain instruction, instruction decode, instruction execution, access memory, data and write back.
The main modular that this double flow line comprises is instruction counter, command memory, register file, arithmetic element, data-carrier store, data selector, jump forecasting module and data prediction module.Wherein the function of each module is as follows:
(1) instruction counter (PC): output is performed the position of instruction in command memory, and promptly the instruction address pointer is exported 11 signals;
(2) command memory (IR): deposit the instruction of finishing the electric energy computation chip all functions.Corresponding hardware is the double flow line storer of 2K*54 position;
(3) register file (Register): deposit a large amount of 48 intermediate data and predefined various 48 potential coefficients of computing, corresponding hardware is double flow line structure, and the data of two streamlines can exchange mutually;
(4) arithmetic element (ALU): carry out the arithmetic sum logical operation that needs.Wherein comprise: 48+48 totalizers, 48-48 subtracters, 48 multipliers of 48 *, 48/48 dividers, and some other logical operations unit.Corresponding hardware is the double flow line structure of two ALU;
(5) data-carrier store (Memory): the operation result that storage need be preserved.Article two, streamline corresponds to the data of two groups of 256*48 positions respectively.Everybody shared register file simultaneously, the data of two streamlines can exchange mutually, and about 128 8-24 register is wherein arranged, and are used for realizing and the external data exchange;
(6) data selector (MUX): from the multichannel input, select the output of a certain road;
(7) jump forecasting module: this module is mainly the jump instruction service;
(8) data prediction module: every streamline all has a data prediction module.Need the data prediction function that solves before and after in pipeline system, finishing in the instruction.
The present invention is like this work: will be used for realizing that the instruction of electric energy computation chip all functions leaves command memory according to the order of sequence in, come the operation of steering order by instruction counter, every instruction all will be divided into 5 different the processing stage: obtain instruction, instruction decode, instruction execution, access memory, data and write back.Wherein, 12 arithmetic of special arithmetic unit ALU or logical operation, corresponding 5 level production lines, execution in step is: sense order is put into register file (Register) → read source operand → carry out the computing → result is passed to data-carrier store (Memory) in arithmetic element (ALU) from register file (Register) from the command memory (IR) that instruction counter (PC) points to, and does not participate in memory access operation → result of calculation is write back to register file (Register) by data selector (MUX).Special arithmetic unit ALU of the present invention is simple in structure, and operating rate is fast, applying flexible, and the most economical realization electric energy metrical of energy designs the function of the electric energy metrical designing requirement of desired function, particularly multifunctional high-performance, makes cheap and product low in energy consumption.
In sum, the present invention realizes electric energy metrical designing institute requirement function, is applied in the electric energy computation chip, and is simple in structure, and applying flexible is economical and practical.
Claims (4)
1. the special arithmetic unit ALU of electric energy metrical design is characterized in that:
This special arithmetic unit ALU includes that totalizer, subtracter, multiplier 1, multiplier 2, divider, logarithm round, multiplier 3, multiplier 4, take absolute value, anti-shunt running, get positive number and get negative, totally 12 arithmetic or logical operation modules with 48 bit arithmetic abilities;
Special arithmetic unit ALU has two 48 data input pin to import the 1st data and the 2nd data respectively, one 48 data output end; Wherein totally 7 arithmetic or logical operation module link to each other with described two 48 data input pin for totalizer, subtracter, multiplier 1, multiplier 2, divider, multiplier 3 and multiplier 4, logarithm rounds, takes absolute value, anti-shunt running, get positive number with get negative totally 5 arithmetic or logical operation module link to each other with the data input pin of described input the 1st data, and above-mentioned 12 arithmetic or logical operation module all link to each other with one 48 data output end;
Wherein multiplier 1 output " the 1st data " and " the 2nd data " is multiplied each other afterwards divided by 240 result; Multiplier 2 output " the 1st data " and " the 2nd data " is multiplied each other afterwards divided by 228 result; Multiplier 3 output " the 1st data " and " the 2nd data " is multiplied each other afterwards divided by 240 results of negate again; Multiplier 4 output " the 1st data " and " the 2nd data " multiplied result;
This special arithmetic unit is operated by instruction, and the length of described instruction is 27, and wherein operational code accounts for 5,1 address, source and accounts for 6,2 addresses, source and account for 6, destination address and account for 10:
(1) operational code: the indication arithmetic unit ALU is chosen a certain executable operations of 12 arithmetic or logical operation;
(2) 1 address, source: from 1 address, source, provide the operand " the 1st data " that is input to arithmetic unit ALU;
(3) 2 addresses, source: from 2 addresses, source, provide the operand " the 2nd data " that is input to arithmetic unit ALU;
(4) destination address: the output data of arithmetic unit ALU is stored in destination address;
This special arithmetic unit ALU realizes that by the outside programming electric energy metrical designs desired arithmetic or logical operation function.
2. special arithmetic unit ALU as claimed in claim 1 is characterized in that, its corresponding arithmetic of each bar instruction or logical operation.
3. special arithmetic unit ALU as claimed in claim 1 is characterized in that:
Totalizer: the result of output " the 1st data " and " the 2nd data " addition;
Subtracter: the result that output " the 1st data " and " the 2nd data " is subtracted each other;
Divider: the result that output " the 1st data " and " the 2nd data " is divided by;
Logarithm rounds: the log2 value of output " the 1st data " and the result who rounds;
Take absolute value: the result who takes absolute value of output " the 1st data ";
Anti-shunt running: the result of the anti-shunt running of output " the 1st data ";
Get positive number: the result who takes absolute value of output " the 1st data ";
Get negative: the result of the negate that takes absolute value of output " the 1st data ".
4. special arithmetic unit ALU as claimed in claim 1 is characterized in that: the processing stage that described instruction being divided into 5: obtain instruction, instruction decode, instruction execution, access memory, data and write back.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2006101478321A CN101206561B (en) | 2006-12-22 | 2006-12-22 | Special arithmetic unit ALU |
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| CN2006101478321A CN101206561B (en) | 2006-12-22 | 2006-12-22 | Special arithmetic unit ALU |
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| CN101206561B true CN101206561B (en) | 2010-11-03 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102033737A (en) * | 2010-06-13 | 2011-04-27 | 苏州和迈微电子技术有限公司 | Embedded system oriented multi-stage flowing water digital signal processor system structure |
| CN103645878B (en) * | 2013-12-13 | 2017-02-08 | 广西科技大学 | Four mixed fixed point arithmetic operation control unit for multiple operands |
| CN103677740B (en) * | 2013-12-13 | 2016-09-14 | 广西科技大学 | Floating number plus/minus, multiplication and division computing perform controller |
| CN109740730B (en) * | 2018-12-14 | 2020-10-23 | 安徽寒武纪信息科技有限公司 | Operation method, device and related product |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1042999A (en) * | 1988-12-02 | 1990-06-13 | 王中元 | A kind of digital instrument or device that measures the electric power and electric energy real effective |
| CN1329301A (en) * | 2000-06-21 | 2002-01-02 | 智原科技股份有限公司 | Data processing equipment and its method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1042999A (en) * | 1988-12-02 | 1990-06-13 | 王中元 | A kind of digital instrument or device that measures the electric power and electric energy real effective |
| CN1329301A (en) * | 2000-06-21 | 2002-01-02 | 智原科技股份有限公司 | Data processing equipment and its method |
Non-Patent Citations (2)
| Title |
|---|
| CN 1329301 A,全文. |
| JP特开平8-287037A 1996.11.01 |
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