CN203746056U - Multi-operand four fundamental admixture fixed-point operation controller - Google Patents
Multi-operand four fundamental admixture fixed-point operation controller Download PDFInfo
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- CN203746056U CN203746056U CN201320832488.5U CN201320832488U CN203746056U CN 203746056 U CN203746056 U CN 203746056U CN 201320832488 U CN201320832488 U CN 201320832488U CN 203746056 U CN203746056 U CN 203746056U
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Abstract
A multi-operand four fundamental admixture fixed-point operation controller comprises a command storage and operand transient storage control module, an arithmetic operation control module and a result output control module; a hard-connection circuit of the controller is designed by applying an FPGA (Field-programmable Gate Array); the controller is enabled by a system, and can internally generate pulse sequence signals under the action of system WR signals; under the action of the internal pulse sequence signals, operation command and the operands are written, and the four fundamental admixture fixed-point operation of the multiple operands can be voluntarily completed; the third written operand to the last written operand perform the operation of the operands and the previous operation result; a medium operation result writeback operand 1 transient storage and the written operand 2 can be subjected to collateral execution; a reading request signal is sent to the system after all the operands are received, a high 32-bit operation result, a low 32-bit operation result and flag statuses are read one by one under the control of an RD signal, and the speed of a four fundamental admixture fixed-point operation command flow is improved.
Description
Technical field
The utility model relates to a kind of multioperand four fundamental rules and mixes fixed point arithmetic arithmetic and control unit, relates in particular to a kind of based on the hardwired multioperand four fundamental rules mixing fixed point arithmetic arithmetic and control unit control circuit of FPGA parallel processing circuit and sequential control thereof.
Background technology
Arithmetical unit is one of the most basic parts of microprocessor, and subtraction application of instruction complement code is achieved by totalizer, and micro-order program or the scheduling algorithm of multiplication and divide instruction application specific are achieved by totalizer; Multiplier and divider also can be applied hard connecting circuit and be achieved to improve the speed of multiplication and division arithmetic; Arithmetical unit has two operand input ends, is connected respectively 2, one temporary operands 1 of a temporary operand and operation result with the output terminal of two working storages; Its operating process is divided into two kinds of situations, situation is two working storages that internal data bus that microprocessor is passed through in timesharing transmits operand 1 and operand 2 respectively arithmetical unit, and computing finishes the internal data bus by microprocessor again and operation result write back in the working storage that leaves operand 1 in; The 2nd kind of situation is that operand 1 is the result of computing last time, after last time, operation result write back, then transmits operand 2, and operation result writes back the working storage of operand 1; It is the internal data bus time-sharing operations by microprocessor that operation result writes back with the processing procedure of the transmission of operand 2; On the other hand, in the order set of microprocessor, normally double operand instruction of arithmetical operation class instruction, in instruction, one is that 1, one of operand is operand 2, also has a register of depositing operation result; Or will deposit operation result and the shared working storage of operand 1; If there are multiple continuous addition subtraction multiplication and division computings, such as 7 operands, need 6 operational orders to be achieved, carry out these 6 instructions and need fetching and Instruction decoding 6 times, result writes back 6 times, and operand 2 to send the process that input end of arithmetical unit and result write back to operand 1 working storage to be time-division processing, be unfavorable for further improving the speed that the instruction of arithmetical operation class is carried out.
Summary of the invention
The purpose of this utility model is to provide a kind of multioperand four fundamental rules to mix fixed point arithmetic arithmetic and control unit, the hard connecting circuit that application FPGA design multioperand four fundamental rules are mixed fixed point arithmetic arithmetic and control unit; This controller is enabled by system, and under the continuous action of system WR signal, the inner pulse sequence signal that produces, under the effect of these pulse signals, writes algorithm according to sequential, operand; The 3rd operand writing until participate in operand that last operand of computing carries out to write and last time operation result computing; This controller is under the effect of internal pulses sequence signal, and the four fundamental rules that independently complete multioperand are mixed fixed point arithmetic computing, intermediate operations result write back operation number 1 working storage can with write operation number 2 executed in parallel; After receiving all operands, send and read request signal to system, system is sent RD signal as required, reads in order low 32, high 32 bit arithmetic results and operation token state; Be conducive to four fundamental rules and mix the speed that fixed point arithmetic operational order stream is carried out.
The technical scheme solving the problems of the technologies described above is: a kind of multioperand four fundamental rules are mixed fixed point arithmetic arithmetic and control unit, comprises that command register and operand keep in control module, arithmetical operation control module, result output control module;
The temporary control module of described command register and operand and arithmetical operation control module, result output control module connects;
Described arithmetical operation control module is also connected with result output control module;
The temporary control module of described command register and operand enables under " 0 " signal function at system CS, under the continuous action of system WR signal, inner produce pulse 1., pulse 2., pulse 3., 4. signal of pulse; Under the effect of these pulse signals, the temporary control module of described command register and operand writes algorithm, operand latch from system data bus DB, control computing and the result latch of arithmetical operation control module, control the operation result of result output control module and the latch of mark, after receiving all operands, send and read request signal to system;
Described arithmetical operation control module is according to the command code of command register and the temporary control module output of operand, implement two significance bits and be the adding of 64 and 32 fixed-point operation numbers, subtract, multiplication and division computing, subtraction adopts complement code to add computing, the mark of operation result is set, if operation result is abnormal, send the abnormal signal of operation result;
Described result output control module is stored intermediate result and the net result of high 32 bit arithmetics, and the mark of storage operation result, under the effect of system RD signal, exports 64 bit arithmetic results and operation token timesharing to system data bus DB; Keep under the effect of output module reset signal of control module output reset result output control module at command register and operand.
Its further technical scheme is: the temporary control module of described command register and operand comprises pulse generation and controller, not gate, and with door I ,-1 counter, shift register, operand working storage, with door II, alternative selector switch, operand 1 and operation result working storage, with door III, the enable signal input end of described pulse generation and controller is connected with system CS signal wire, pulse signal input terminal is connected with system WR signal wire, clock pulse input terminal is connected with clock signal of system line, the output terminal of reset signal input end and not gate is connected, spill over input end is connected with the output terminal that overflows of-1 counter, pulse is the presetting pulse signal input part of output terminal and-1 counter 1., shift register presetting pulse signal input part, the reset signal input end of operand working storage, the reset signal input end of operand 1 and operation result working storage, result output control module connects, pulse 2. output terminal be connected with an input end, the gating signal input end of alternative selector switch, the arithmetical operation control module of door II, pulse 3. output terminal be connected with an input end of door I, pulse 4. output terminal with another input end of door I, with door II another input end, arithmetical operation control module, result output control module be connected,
The input end of described not gate is connected with system CS signal wire; Output terminal also with the reset signal input end of-1 counter, with door III an input end be connected;
Describedly be connected with the door output terminal of I and the counting pulse signal input end of-1 counter, the shift pulse signal input part of shift register, the write signal input end of operand working storage;
The enable signal input end of described-1 counter is connected with system CS signal wire, and counting initial value input end is connected to D28 line with the D31 of system DB; Spill over output terminal is also as reading request signal output;
The command signal input end of described shift register is connected to D0 with the D27 of system DB; Command code output terminal is connected with arithmetical operation control module;
The operand input end of described operand working storage is connected to D0 line with the D31 of system DB; 32 positional operand 2 output terminals are connected with arithmetical operation control module;
Described with door II output terminal be connected with the write signal input end of operation result working storage with operand 1;
A data input pin of described alternative selector switch is connected to D0 line with the D31 of system DB, and another low 32 bit arithmetic result input ends are connected with arithmetical operation control module; Output terminal is connected with 32 bit data input ends of operation result working storage with operand 1;
Described operand 1 is connected with arithmetical operation control module, result output control module with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage;
Described with door III another input end be connected with systematic reset signal line; Output terminal is connected with arithmetical operation control module.
Its further technical scheme is: described arithmetical operation control module comprises totalizer, multiplier, divider, one-out-three selector switch I, one-out-three selector switch II, status register and control module thereof; Low 32 positional operand 1 input ends of described totalizer are connected with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage with operand 1, high 32 positional operand 1 input ends are connected with result output control module, 32 positional operand 2 input ends are connected with 32 positional operand 2 output terminals of operand working storage, command code input end is connected with the command code output terminal of shift register, arithmetical unit reset signal input end be connected with the output terminal of door III, the pulse that operand sign bit is adjusted input end and pulse generation and controller 2. output terminal is connected; Low 32 output terminals are connected with an input end of one-out-three selector switch I, and high 32 output terminals are connected with an input end of one-out-three selector switch II;
Low 32 positional operand 1 input ends of described multiplier are connected with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage with operand 1, high 32 positional operand 1 input ends are connected with result output control module, 32 positional operand 2 input ends are connected with 32 positional operand 2 output terminals of operand working storage, command code input end is connected with the command code output terminal of shift register, arithmetical unit reset signal input end be connected with the output terminal of door III, the pulse that operand sign bit is adjusted input end and pulse generation and controller 2. output terminal is connected; Low 32 output terminals are connected with an input end of one-out-three selector switch I, and high 32 output terminals are connected with an input end of one-out-three selector switch II;
Low 32 positional operand 1 input ends of described divider are connected with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage with operand 1, high 32 positional operand 1 input ends are connected with result output control module, 32 positional operand 2 input ends are connected with 32 positional operand 2 output terminals of operand working storage, command code input end is connected with the command code output terminal of shift register, arithmetical unit reset signal input end be connected with the output terminal of door III, the pulse that operand sign bit is adjusted input end and pulse generation and controller 2. output terminal is connected; Low 32 output terminals are connected with an input end of one-out-three selector switch I, and high 32 output terminals are connected with an input end of one-out-three selector switch II, and operation mistake output terminal is connected with the operation mistake input end of status register and control module thereof;
The gating control end of described one-out-three selector switch I is connected with the command code output terminal of shift register; Output terminal is connected with the low 32 bit arithmetic result input ends of status register and control module thereof, the low 32 bit arithmetic result input ends of alternative selector switch;
The gating control end of described one-out-three selector switch II is connected with the command code output terminal of shift register; Output terminal is connected with high 32 bit arithmetic result input ends, the result output control module of status register and control module thereof;
The pulse that the state of described status register and control module thereof writes input end and pulse generation and controller 4. output terminal is connected, operand 1 sign bit input end is connected with the D31 line of high 32 positional operands 1 of result output control module output, operand 2 sign bit input ends are connected with 32 positional operand 2 output terminal D31 lines of operand working storage, arithmetical unit the RESET input be connected with the output terminal of door III; Mark output end is connected with result output control module, and the abnormal output terminal of operation result is to system output operation result abnormal signal.
Its further technical scheme is: described result output control module comprises high 32 bit arithmetic result working storages, flag register, and counter-controller, one-out-three selector switch III, with door IV, 32 triple gate groups; The high 32 bit arithmetic result input ends of described high 32 bit arithmetic result working storages are connected with the output terminal of one-out-three selector switch II, the pulse that result writes input end and pulse generation and controller 4. output terminal is connected, and the pulse of output module reset signal input end and pulse generation and controller 1. output terminal is connected; Output terminal is connected with high 32 positional operand 1 input ends of totalizer, multiplier and divider, the high 32 bit arithmetic result input ends of one-out-three selector switch III;
The mark input end of described flag register is connected with the mark output end of status register and control module thereof, the pulse that result writes input end and pulse generation and controller 4. output terminal is connected, and the pulse of output module reset signal input end and pulse generation and controller 1. output terminal is connected; Operation token output terminal is connected with the operation token input end of one-out-three selector switch III;
The count pulse input end of described counter-controller is connected with system RD signal wire, and enable signal input end is connected with system CS line, and the pulse of output module reset signal input end and pulse generation and controller 1. output terminal is connected; RD1, RD2, RD3 signal output part respectively with three control input ends of one-out-three selector switch III, with door IV three input ends be connected;
The low 32 bit arithmetic result input ends of described one-out-three selector switch III are connected with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage; Output terminal is connected with the input end of 32 triple gate groups;
Described with door IV output terminal be connected with the control end of 32 triple gate groups;
32 bit data output terminals of described 32 triple gate groups are connected with system DB.
Its further technical scheme is: the pulse generation of the temporary control module of described command register and operand and controller send the pulse of synchronizeing with system WR signal 1., pulse 2., pulse 3., 4. signal of pulse;
In pulse 1. under the effect of negative edge, the D31 of the algorithm transmitting from system data bus DB writes-1 counter to an operand numerical value of D28 as counting initial value, D27 writes shift register to the command code of D0, exports the algorithm of the 1st operand and the 2nd operand; Reset operation is counted working storage, operand 1 and operation result working storage, high 32 bit arithmetic result working storages;
In pulse 2. under the effect of negative edge, the 1st operand write operation number 1 and the operation result working storage of algorithm;
In pulse, 3. under the effect of negative edge ,-1 counter subtracts 1 operation, and the command code value in shift register moves to right two, and working storage is counted in the 2nd operand write operation of algorithm;
In pulse 4. under the effect of negative edge, working storage is counted in the 3rd operand write operation of algorithm,-1 counter subtracts 1 operation, command code value in shift register moves to right two, export the algorithm of the 3rd operand and operation result, low 32 bit arithmetic result write operation numbers 1 and operation result working storage, high 32 bit arithmetic results write high 32 bit arithmetic result working storages, operation result Status Flag write state register and control module thereof;
Overflow output terminal when " 1 " when-1 counter, shown in pulse generation and controller circulation output pulse 4., in pulse 4. under the effect of negative edge, working storage is counted in the operand write operation of algorithm,-1 counter subtracts 1 operation, command code value in shift register moves to right two, export the algorithm of this operand and operation result, the low 32 bit arithmetic result write operation numbers 1 and operation result working storage of computing last time, high 32 bit arithmetic results write high 32 bit arithmetic result working storages, operation result Status Flag write state register and control module thereof,
When-1 counter overflow output terminal by " 1 " → " 0 " time, the pulse that pulse generation and controller send a clock period is 4.; Shown in the output terminal that overflows of-1 counter remain " 0 " state, until the presetting pulse receiving inputs from " 1 " → " 0 " ,-1 counter overflow output terminal by " 0 " → " 1 ".
Owing to adopting above structure, parallel work-flow arithmetical operation and the controller thereof of the utility model have following beneficial effect:
One, arithmetical operation has from main control function
This controller is enabled by system, and under the continuous action of system WR signal, the inner pulse sequence signal that produces, under the effect of these pulse signals, writes algorithm according to sequential, operand; The 3rd operand writing until participate in operand that last operand of computing carries out to write and last time operation result computing; This controller is under the effect of internal pulses sequence signal, and the four fundamental rules that independently complete multioperand are mixed fixed point arithmetic computing, operation result write back operand 1 working storage can with write operation number 2 executed in parallel; Fully apply the parallel processing function of FPGA, be conducive to improve the speed that arithmetic operation instruction stream is carried out.
Two, realize multioperand four fundamental rules and mix fixed point arithmetic computing
In the utility model, multioperand four fundamental rules are mixed fixed point arithmetic arithmetic and control unit to be had and adds, takes advantage of and division fixed point arithmetic arithmetical unit, this controller is according to the selected arithmetical unit calculating of the command code value of each computing, under the control of inner clock signal, realize multioperand four fundamental rules and mix fixed point arithmetic computing; After receiving all operands, send and read request signal to system, system is sent RD signal as required, reads in order low 32, high 32 bit arithmetic results and operation token state; The algorithm of carrying out a multioperand is equivalent to the order of the arithmetical operation of carrying out many two operands.
Three, cost performance is high
In the utility model, the hardwired multioperand four fundamental rules of application FPGA design circuit are mixed fixed point arithmetic arithmetic and control unit, under the control of inner clock signal, reach and independently complete multioperand four fundamental rules and mix fixed point arithmetic computing, operation result write back operand 1 working storage can with write operation number 2 executed in parallel; Be conducive to four fundamental rules and mix the speed that fixed point arithmetic operational order stream is carried out, there is higher cost performance.
Parallel work-flow arithmetical operation below in conjunction with drawings and Examples to the utility model and the technical characterictic of controller thereof are further described.
Brief description of the drawings
Fig. 1: more than the utility model, operand four fundamental rules are mixed the system architecture diagram of fixed point arithmetic arithmetic and control unit;
Fig. 2: more than the utility model, operand four fundamental rules are mixed the command register of fixed point arithmetic arithmetic and control unit and the circuit connection diagram of the temporary control module of operand;
Fig. 3: more than the utility model, operand four fundamental rules are mixed the circuit connection diagram of the arithmetical operation control module of fixed point arithmetic arithmetic and control unit;
Fig. 4: more than the utility model, operand four fundamental rules are mixed the circuit connection diagram of the result output control module of fixed point arithmetic arithmetic and control unit;
Fig. 5: more than the utility model, operand four fundamental rules are mixed the command execution sequential chart of fixed point arithmetic arithmetic and control unit.
In figure:
I-command register and operand are kept in control module, II-arithmetical operation control module, III-result output control module;
1-pulse generation and controller, 2-not gate, 3-with door an I, 4--1 counters, 5-shift register, 6-operand working storage, 7-with door an II, 8-alternative selector switch, 9-operand 1 and operation result working storage, 10-with door an III, 11-totalizer, 12-multiplier, 13-divider, 14-one-out-three selector switch I, 15-one-out-three selector switch II, 16-status register and control module thereof, 17-high 32 bit arithmetic result working storages, 18-flag register, 19-counter-controller, 20-one-out-three selector switch III, 21-with door an IV, 22-32 triple gate groups.
Abbreviation explanation in literary composition:
FPGA-Field Programmable Gate Array, field programmable gate array;
DB-Data Bus, data bus;
CS-Chip Select, sheet selects or enables, CS representative " enable signal " in figure;
RD-Read, reads, representative " read output signal " in figure;
WR-Write, writes, representative " write signal " in figure.
Embodiment
Embodiment:
A kind of multioperand four fundamental rules are mixed fixed point arithmetic arithmetic and control unit, as shown in Figure 1, it is characterized in that: this controller comprises command register and the temporary control module I of operand, arithmetical operation control module II, result output control module III;
The temporary control module I of described command register and operand and arithmetical operation control module II, result output control module III connects;
Described arithmetical operation control module II is also connected with result output control module III;
The temporary control module I of described command register and operand enables under " 0 " signal function at system CS, under the continuous action of system WR signal, inner produce pulse 1., pulse 2., pulse 3., 4. signal of pulse; Under the effect of these pulse signals, the temporary control module I of described command register and operand writes algorithm, operand latch from system data bus DB, control computing and the result latch of arithmetical operation control module II, control the operation result of result output control module III and the latch of mark, after receiving all operands, send and read request signal to system;
Described arithmetical operation control module II is according to the command code of command register and the temporary control module I output of operand, implement two significance bits and be the adding of 64 and 32 fixed-point operation numbers, subtract, multiplication and division computing, subtraction adopts complement code to add computing, the mark of operation result is set, if operation result is abnormal, send the abnormal signal of operation result;
Described result output control module III is stored intermediate result and the net result of high 32 bit arithmetics, and the mark of storage operation result, under the effect of system RD signal, exports 64 bit arithmetic results and operation token timesharing to system data bus DB; Keep under the effect of output module reset signal of control module I output reset result output control module III at command register and operand.
As shown in Figure 2, the temporary control module I of described command register and operand comprises pulse generation and controller 1, and not gate 2, with door I 3,-1 counter 4, shift register 5, operand working storage 6, with door II 7, alternative selector switch 8, operand 1 and operation result working storage 9, with door III 10, the enable signal input end of described pulse generation and controller 1 is connected with system CS signal wire, pulse signal input terminal is connected with system WR signal wire, clock pulse input terminal is connected with clock signal of system line, reset signal input end is connected with the output terminal of not gate 2, spill over input end is connected with the output terminal that overflows of-1 counter 4, pulse is the presetting pulse signal input part of output terminal and-1 counter 4 1., shift register 5 presetting pulse signal input parts, the reset signal input end of operand working storage 6, the reset signal input end of operand 1 and operation result working storage 9, result output control module III connects, pulse 2. output terminal be connected with an input end, the gating signal input end of alternative selector switch 8, the arithmetical operation control module II of door II 7, pulse 3. output terminal be connected with an input end of door I 3, pulse 4. output terminal with another input end of door I 3, with door II 7 another input end, arithmetical operation control module II, result output control module III be connected,
The input end of described not gate 2 is connected with system CS signal wire; Output terminal also with the reset signal input end of-1 counter 4, with door III 10 an input end be connected;
Describedly be connected with the door output terminal of I 3 and the counting pulse signal input end of-1 counter 4, the shift pulse signal input part of shift register 5, the write signal input end of operand working storage 6;
The enable signal input end of described-1 counter 4 is connected with system CS signal wire, and counting initial value input end is connected to D28 line with the D31 of system DB; Spill over output terminal is also as reading request signal output;
The command signal input end of described shift register 5 is connected to D0 with the D27 of system DB; Command code output terminal is connected with arithmetical operation control module II;
The operand input end of described operand working storage 6 is connected to D0 line with the D31 of system DB; 32 positional operand 2 output terminals are connected with arithmetical operation control module II;
Described with door II 7 output terminal be connected with the write signal input end of operation result working storage 9 with operand 1;
A data input pin of described alternative selector switch 8 is connected to D0 line with the D31 of system DB, and another low 32 bit arithmetic result input ends are connected with arithmetical operation control module II; Output terminal is connected with 32 bit data input ends of operation result working storage 9 with operand 1;
Described operand 1 is connected with arithmetical operation control module II, result output control module III with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage 9;
Described with door III 10 another input end be connected with systematic reset signal line; Output terminal is connected with arithmetical operation control module II.
As shown in Figure 3, described arithmetical operation control module II comprises totalizer 11, multiplier 12, divider 13, one-out-three selector switch I 14, one-out-three selector switch II 15, status register and control module 16 thereof, low 32 positional operand 1 input ends of described totalizer 11 are connected with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage 9 with operand 1, high 32 positional operand 1 input ends are connected with result output control module III, 32 positional operand 2 input ends are connected with 32 positional operand 2 output terminals of operand working storage 6, command code input end is connected with the command code output terminal of shift register 5, arithmetical unit reset signal input end be connected with the output terminal of door III 10, the pulse that operand sign bit is adjusted input end and pulse generation and controller 1 2. output terminal is connected, low 32 output terminals are connected with an input end of one-out-three selector switch I 14, and high 32 output terminals are connected with an input end of one-out-three selector switch II 15,
Low 32 positional operand 1 input ends of described multiplier 12 are connected with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage 9 with operand 1, high 32 positional operand 1 input ends are connected with result output control module III, 32 positional operand 2 input ends are connected with 32 positional operand 2 output terminals of operand working storage 6, command code input end is connected with the command code output terminal of shift register 5, arithmetical unit reset signal input end be connected with the output terminal of door III 10, the pulse that operand sign bit is adjusted input end and pulse generation and controller 1 2. output terminal is connected, low 32 output terminals are connected with an input end of one-out-three selector switch I 14, and high 32 output terminals are connected with an input end of one-out-three selector switch II 15,
Low 32 positional operand 1 input ends of described divider 13 are connected with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage 9 with operand 1, high 32 positional operand 1 input ends are connected with result output control module III, 32 positional operand 2 input ends are connected with 32 positional operand 2 output terminals of operand working storage 6, command code input end is connected with the command code output terminal of shift register 5, arithmetical unit reset signal input end be connected with the output terminal of door III 10, the pulse that operand sign bit is adjusted input end and pulse generation and controller 1 2. output terminal is connected, low 32 output terminals are connected with an input end of one-out-three selector switch I 14, and high 32 output terminals are connected with an input end of one-out-three selector switch II 15, and operation mistake output terminal is connected with the operation mistake input end of status register and control module 16 thereof,
The gating control end of described one-out-three selector switch I 14 is connected with the command code output terminal of shift register 5; Output terminal is connected with the low 32 bit arithmetic result input ends of status register and control module 16 thereof, the low 32 bit arithmetic result input ends of alternative selector switch 8;
The gating control end of described one-out-three selector switch II 15 is connected with the command code output terminal of shift register 5; Output terminal is connected with high 32 bit arithmetic result input ends, the result output control module III of status register and control module 16 thereof;
The pulse that the state of described status register and control module 16 thereof writes input end and pulse generation and controller 1 4. output terminal is connected, operand 1 sign bit input end is connected with the D31 line of high 32 positional operands 1 of result output control module III output, operand 2 sign bit input ends are connected with 32 positional operand 2 output terminal D31 lines of operand working storage 6, arithmetical unit the RESET input be connected with the output terminal of door III 10; Mark output end is connected with result output control module III, and the abnormal output terminal of operation result is to system output operation result abnormal signal.
As shown in Figure 4, described result output control module III comprises high 32 bit arithmetic result working storages 17, flag register 18, and counter-controller 19, one-out-three selector switch III 20, with 21,32 triple gate groups 22 of door IV; The high 32 bit arithmetic result input ends of described high 32 bit arithmetic result working storages 17 are connected with the output terminal of one-out-three selector switch II 15, the pulse that result writes input end and pulse generation and controller 1 4. output terminal is connected, and the pulse of output module reset signal input end and pulse generation and controller 1 1. output terminal is connected; Output terminal is connected with high 32 positional operand 1 input ends of totalizer 11, multiplier 12 and divider 13, the high 32 bit arithmetic result input ends of one-out-three selector switch III 20;
The mark input end of described flag register 18 is connected with the mark output end of status register and control module 16 thereof, the pulse that result writes input end and pulse generation and controller 1 4. output terminal is connected, and the pulse of output module reset signal input end and pulse generation and controller 1 1. output terminal is connected; Operation token output terminal is connected with the operation token input end of one-out-three selector switch III 20;
The count pulse input end of described counter-controller 19 is connected with system RD signal wire, and enable signal input end is connected with system CS line, and the pulse of output module reset signal input end and pulse generation and controller 1 1. output terminal is connected; RD1, RD2, RD3 signal output part respectively with three control input ends of one-out-three selector switch III 20, with door IV 21 three input ends be connected;
The low 32 bit arithmetic result input ends of described one-out-three selector switch III 20 are connected with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage 9; Output terminal is connected with the input end of 32 triple gate groups 22;
Described with door IV 21 output terminal be connected with the control end of 32 triple gate groups 22;
32 bit data output terminals of described 32 triple gate groups 22 are connected with system DB.
As shown in Figure 2, Figure 3, Figure 4, the pulse generation of the temporary control module I of described command register and operand and controller 1 send the pulse of synchronizeing with system WR signal 1., pulse 2., pulse 3., 4. signal of pulse;
In pulse 1. under the effect of negative edge, the D31 of the algorithm transmitting from system data bus DB writes-1 counter 4 to an operand numerical value of D28 as counting initial value, D27 writes shift register 5 to the command code of D0, exports the algorithm of the 1st operand and the 2nd operand; Reset operation is counted working storage 6, operand 1 and operation result working storage 9, high 32 bit arithmetic result working storages 17;
In pulse 2. under the effect of negative edge, the 1st operand write operation number 1 and the operation result working storage 9 of algorithm;
In pulse, 3. under the effect of negative edge ,-1 counter 4 subtracts 1 operation, and the command code value in shift register 5 moves to right two, and working storage 6 is counted in the 2nd operand write operation of algorithm;
In pulse 4. under the effect of negative edge, working storage 6 is counted in the 3rd operand write operation of algorithm,-1 counter 4 subtracts 1 operation, command code value in shift register 5 moves to right two, export the algorithm of the 3rd operand and operation result, low 32 bit arithmetic result write operation numbers 1 and operation result working storage 9, high 32 bit arithmetic results write high 32 bit arithmetic result working storages 17, operation result Status Flag write state register and control module 16 thereof;
Overflow output terminal when " 1 " when-1 counter 4, shown in the 1 circulation output pulse of pulse generation and controller 4., in pulse 4. under the effect of negative edge, working storage 6 is counted in the operand write operation of algorithm,-1 counter 4 subtracts 1 operation, command code value in shift register 5 moves to right two, export the algorithm of this operand and operation result, the low 32 bit arithmetic result write operation numbers 1 and operation result working storage 9 of computing last time, high 32 bit arithmetic results write high 32 bit arithmetic result working storages 17, operation result Status Flag write state register and control module 16 thereof,
When-1 counter 4 overflow output terminal by " 1 " → " 0 " time, the pulse that pulse generation and controller 1 send a clock period is 4.; Shown in the output terminal that overflows of-1 counter 4 remain " 0 " state, until the presetting pulse receiving inputs from " 1 " → " 0 " ,-1 counter 4 overflow output terminal by " 0 " → " 1 ".
Claims (5)
1. multioperand four fundamental rules are mixed a fixed point arithmetic arithmetic and control unit, it is characterized in that: this controller comprises command register and the temporary control module (I) of operand, arithmetical operation control module (II), result output control module (III);
Described command register and operand are kept in control module (I) and arithmetical operation control module (II), and result output control module (III) connects;
Described arithmetical operation control module (II) is also connected with result output control module (III);
Described command register and operand keep in control module (I) at system CS for enabling under " 0 " signal function, under the continuous action of system WR signal, inner produce pulse 1., pulse 2., pulse 3., 4. signal of pulse; Under the effect of these pulse signals, described command register and operand are kept in control module (I) and are write algorithm, operand latch from system data bus DB, control computing and the result latch of arithmetical operation control module (II), control the operation result of result output control module (III) and the latch of mark, after receiving all operands, send and read request signal to system;
Described arithmetical operation control module (II) is according to the command code of command register and temporary control module (I) output of operand, implement two significance bits and be the adding of 64 and 32 fixed-point operation numbers, subtract, multiplication and division computing, subtraction adopts complement code to add computing, the mark of operation result is set, if operation result is abnormal, send the abnormal signal of operation result;
Described result output control module (III) is stored intermediate result and the net result of high 32 bit arithmetics, and the mark of storage operation result, under the effect of system RD signal, exports 64 bit arithmetic results and operation token timesharing to system data bus DB; Keep under the effect of output module reset signal of control module (I) output reset result output control module (III) at command register and operand.
2. multioperand four fundamental rules as claimed in claim 1 are mixed fixed point arithmetic arithmetic and control unit, it is characterized in that: described command register and operand are kept in control module (I) and comprised pulse generation and controller (1), not gate (2), with door I (3) ,-1 counter (4), shift register (5), operand working storage (6), with door II (7), alternative selector switch (8), operand 1 and operation result working storage (9), with door III (10), the enable signal input end of described pulse generation and controller (1) is connected with system CS signal wire, pulse signal input terminal is connected with system WR signal wire, clock pulse input terminal is connected with clock signal of system line, reset signal input end is connected with the output terminal of not gate (2), spill over input end is connected with the output terminal that overflows of-1 counter (4), pulse is the presetting pulse signal input part of output terminal and-1 counter (4) 1., shift register (5) presetting pulse signal input part, the reset signal input end of operand working storage (6), the reset signal input end of operand 1 and operation result working storage (9), result output control module (III) connects, pulse 2. output terminal be connected with an input end, the gating signal input end of alternative selector switch (8), the arithmetical operation control module (II) of door II (7), pulse 3. output terminal be connected with an input end of door I (3), pulse 4. output terminal with another input end of door I (3), with door II (7) another input end, arithmetical operation control module (II), a result output control module (III) be connected,
The input end of described not gate (2) is connected with system CS signal wire; Output terminal also with the reset signal input end of-1 counter (4), with door III (10) an input end be connected;
Described with door I (3) an output terminal be connected with the counting pulse signal input end of-1 counter (4), the shift pulse signal input part of shift register (5), the write signal input end of operand working storage (6);
The enable signal input end of described-1 counter (4) is connected with system CS signal wire, and counting initial value input end is connected to D28 line with the D31 of system DB; Spill over output terminal is also as reading request signal output;
The command signal input end of described shift register (5) is connected to D0 with the D27 of system DB; Command code output terminal is connected with arithmetical operation control module (II);
The operand input end of described operand working storage (6) is connected to D0 line with the D31 of system DB; 32 positional operand 2 output terminals are connected with arithmetical operation control module (II);
Described with door II (7) an output terminal be connected with the write signal input end of operation result working storage (9) with operand 1;
A data input pin of described alternative selector switch (8) is connected to D0 line with the D31 of system DB, and another low 32 bit arithmetic result input ends are connected with arithmetical operation control module (II); Output terminal is connected with 32 bit data input ends of operation result working storage (9) with operand 1;
Described operand 1 is connected with arithmetical operation control module (II), result output control module (III) with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage (9);
Described with door III (10) another input end be connected with systematic reset signal line; Output terminal is connected with arithmetical operation control module (II).
3. multioperand four fundamental rules as claimed in claim 1 are mixed fixed point arithmetic arithmetic and control unit, it is characterized in that: described arithmetical operation control module (II) comprises totalizer (11), multiplier (12), divider (13), one-out-three selector switch I (14), one-out-three selector switch II (15), status register and control module thereof (16);
Low 32 positional operand 1 input ends of described totalizer (11) are connected with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage (9) with operand 1, high 32 positional operand 1 input ends are connected with result output control module (III), 32 positional operand 2 input ends are connected with 32 positional operand 2 output terminals of operand working storage (6), command code input end is connected with the command code output terminal of shift register (5), arithmetical unit reset signal input end be connected with the output terminal of door III (10), the pulse that operand sign bit is adjusted input end and pulse generation and controller (1) 2. output terminal is connected, low 32 output terminals are connected with an input end of one-out-three selector switch I (14), and high 32 output terminals are connected with an input end of one-out-three selector switch II (15),
Low 32 positional operand 1 input ends of described multiplier (12) are connected with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage (9) with operand 1, high 32 positional operand 1 input ends are connected with result output control module (III), 32 positional operand 2 input ends are connected with 32 positional operand 2 output terminals of operand working storage (6), command code input end is connected with the command code output terminal of shift register (5), arithmetical unit reset signal input end be connected with the output terminal of door III (10), the pulse that operand sign bit is adjusted input end and pulse generation and controller (1) 2. output terminal is connected, low 32 output terminals are connected with an input end of one-out-three selector switch I (14), and high 32 output terminals are connected with an input end of one-out-three selector switch II (15),
Low 32 positional operand 1 input ends of described divider (13) are connected with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage (9) with operand 1, high 32 positional operand 1 input ends are connected with result output control module (III), 32 positional operand 2 input ends are connected with 32 positional operand 2 output terminals of operand working storage (6), command code input end is connected with the command code output terminal of shift register (5), arithmetical unit reset signal input end be connected with the output terminal of door III (10), the pulse that operand sign bit is adjusted input end and pulse generation and controller (1) 2. output terminal is connected, low 32 output terminals are connected with an input end of one-out-three selector switch I (14), high 32 output terminals are connected with an input end of one-out-three selector switch II (15), and operation mistake output terminal is connected with the operation mistake input end of status register and control module (16) thereof,
The gating control end of described one-out-three selector switch I (14) is connected with the command code output terminal of shift register (5); Output terminal is connected with the low 32 bit arithmetic result input ends of status register and control module (16) thereof, the low 32 bit arithmetic result input ends of alternative selector switch (8);
The gating control end of described one-out-three selector switch II (15) is connected with the command code output terminal of shift register (5); Output terminal is connected with high 32 bit arithmetic result input ends, the result output control module (III) of status register and control module (16) thereof;
The pulse that the state of described status register and control module thereof (16) writes input end and pulse generation and controller (1) 4. output terminal is connected, operand 1 sign bit input end is connected with the D31 line of high 32 positional operands 1 of result output control module (III) output, operand 2 sign bit input ends are connected with 32 positional operand 2 output terminal D31 lines of operand working storage (6), arithmetical unit the RESET input be connected with the output terminal of door III (10); Mark output end is connected with result output control module (III), and the abnormal output terminal of operation result is to system output operation result abnormal signal.
4. multioperand four fundamental rules as claimed in claim 1 are mixed fixed point arithmetic arithmetic and control unit, it is characterized in that: described result output control module (III) comprises high 32 bit arithmetic result working storages (17), flag register (18), counter-controller (19), one-out-three selector switch III (20), with door IV (21), 32 triple gate groups (22); The high 32 bit arithmetic result input ends of described high 32 bit arithmetic result working storages (17) are connected with the output terminal of one-out-three selector switch II (15), the pulse that result writes input end and pulse generation and controller (1) 4. output terminal is connected, and the pulse of output module reset signal input end and pulse generation and controller (1) 1. output terminal is connected; Output terminal is connected with high 32 positional operand 1 input ends of totalizer (11), multiplier (12) and divider (13), the high 32 bit arithmetic result input ends of one-out-three selector switch III (20);
The mark input end of described flag register (18) is connected with the mark output end of status register and control module (16) thereof, the pulse that result writes input end and pulse generation and controller (1) 4. output terminal is connected, and the pulse of output module reset signal input end and pulse generation and controller (1) 1. output terminal is connected; Operation token output terminal is connected with the operation token input end of one-out-three selector switch III (20);
The count pulse input end of described counter-controller (19) is connected with system RD signal wire, and enable signal input end is connected with system CS line, and the pulse of output module reset signal input end and pulse generation and controller (1) 1. output terminal is connected; RD1, RD2, RD3 signal output part respectively with three control input ends of one-out-three selector switch III (20), with door IV (21) three input ends be connected;
The low 32 bit arithmetic result input ends of described one-out-three selector switch III (20) are connected with low 32 bit arithmetic result output terminals with low 32 positional operands 1 of operation result working storage (9); Output terminal is connected with the input end of 32 triple gate groups (22);
Described with door IV (21) an output terminal be connected with the control end of 32 triple gate groups (22);
32 bit data output terminals of described 32 triple gate groups (22) are connected with system DB.
5. multioperand four fundamental rules as claimed in claim 1 are mixed fixed point arithmetic arithmetic and control unit, it is characterized in that: described command register and operand keep in the pulse generation of control module (I) and controller (1) send the pulse of synchronizeing with system WR signal 1., pulse 2., pulse 3., 4. signal of pulse;
In pulse 1. under the effect of negative edge, the D31 of the algorithm transmitting from system data bus DB writes-1 counter (4) to an operand numerical value of D28 as counting initial value, D27 writes shift register (5) to the command code of D0, exports the algorithm of the 1st operand and the 2nd operand; Reset operation is counted working storage (6), operand 1 and operation result working storage (9), high 32 bit arithmetic result working storages (17);
In pulse 2. under the effect of negative edge, the 1st operand write operation number 1 and the operation result working storage (9) of algorithm;
In pulse, 3. under the effect of negative edge ,-1 counter (4) subtracts 1 operation, and the command code value in shift register (5) moves to right two, and working storage (6) is counted in the 2nd operand write operation of algorithm;
In pulse 4. under the effect of negative edge, working storage (6) is counted in the 3rd operand write operation of algorithm,-1 counter (4) subtracts 1 operation, command code value in shift register (5) moves to right two, export the algorithm of the 3rd operand and operation result, low 32 bit arithmetic result write operation numbers 1 and operation result working storage (9), high 32 bit arithmetic results write high 32 bit arithmetic result working storages (17), operation result Status Flag write state register and control module (16) thereof;-1 counter (4) overflow output terminal for " 1 ", shown in pulse generation and controller (1) circulation output pulse 4.;-1 counter (4) overflow output terminal by " 1 " → " 0 ", 4. the pulse that pulse generation and controller (1) send a clock period, is overflowed output terminal and is remained " 0 " state, until presetting pulse is inputted from " 1 " → " 0 ".
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103645878A (en) * | 2013-12-13 | 2014-03-19 | 广西科技大学 | Four mixed fixed point arithmetic operation control unit for multiple operands |
| CN103677740A (en) * | 2013-12-13 | 2014-03-26 | 广西科技大学 | Floating number adding/subtracting/multiplying/dividing operation execution controller |
| CN116863878A (en) * | 2023-09-05 | 2023-10-10 | 中科(深圳)无线半导体有限公司 | Double-line transmission method of mini LED system and chip structure for implementing double-line transmission method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103645878A (en) * | 2013-12-13 | 2014-03-19 | 广西科技大学 | Four mixed fixed point arithmetic operation control unit for multiple operands |
| CN103677740A (en) * | 2013-12-13 | 2014-03-26 | 广西科技大学 | Floating number adding/subtracting/multiplying/dividing operation execution controller |
| CN103677740B (en) * | 2013-12-13 | 2016-09-14 | 广西科技大学 | Floating number plus/minus, multiplication and division computing perform controller |
| CN116863878A (en) * | 2023-09-05 | 2023-10-10 | 中科(深圳)无线半导体有限公司 | Double-line transmission method of mini LED system and chip structure for implementing double-line transmission method |
| CN116863878B (en) * | 2023-09-05 | 2023-12-08 | 中科(深圳)无线半导体有限公司 | Double-line transmission method of mini LED system and chip structure for implementing double-line transmission method |
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