CN105786528B - Design method of SM3 algorithm IP core based on Avalon interface - Google Patents
Design method of SM3 algorithm IP core based on Avalon interface Download PDFInfo
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Abstract
The invention provides a method for designing an SM3 algorithm IP core based on an Avalon interface, and belongs to the technical field of information security. All signals of an encapsulation interface of the IP core are synchronous in clock, are sampled at a rising edge and are effective in high level; when the IP core works, firstly writing the total length of the message block into the length register, then writing the Data of a first message block to be operated into the Data register of the IP core, after the operation of the first message block Data is finished, setting the 3 rd bit of the control register to be 1, then writing the second message block Data to be operated into the IP core, setting the 3 rd bit of the control register to be 0 until all the operation of the message block Data is finished, writing the final hash operation result into the operation result register, and reading the hash operation result through a Data _ out [255..0] interface. The invention has flexible and convenient design and can meet the application requirements of the information security field on data encryption and decryption.
Description
Technical field
The present invention relates to field of information security technology more particularly to a kind of SM3 Algorithm IPs based on Avalon interface
Design method.
Background technique
Hash algorithm is also known as Hash function, hash function, it is can be mapped as the long input message of arbitrary finite
The output valve of regular length and calculate easy Certain function summary.Hash function is that a kind of important basis is calculated in contemporary cryptology
Method provides the support function that data integrity is authenticated and authenticated to message source during constructing information safety system
Energy.Hash function is generally using the design method of grouping iteration, and such as existing typical hash algorithm is all made of MD type in the world
It is grouped iteration structure, wherein using SHA-1 algorithm and SHA-256/384/512 algorithm as representative.Such algorithm has compression letter
Number nonlinearity is high, the advantages that strong is filled and be grouped to message, but there is also threaten safety.For this purpose, researcher causes
Power in the design and analysis and construction of parallel schema hash algorithm, and by national Password Management office on December 22nd, 2010 most
The SM3 cryptographic Hash algorithm suitable for commercial cipher application has been issued eventually.The safety and reliability of SM3 algorithm is high, extensively
Applied to information security field.
Avalon switching bus is a kind of interconnection that on-chip processor and various peripheral hardwares are connected in programmable system on chip
Mechanism.It defines the signal type communicated between main and subordinate node and sequential relationship, allows user easily certainly
Oneself is connected in Nios II system selected or design peripheral module by Avalon bus.But SM3 is calculated in current trust computing
Fado realizes that speed is slower, and safety is poor by software or credible chip.
Summary of the invention
In order to solve the above technical problems, setting the invention proposes a kind of SM3 Algorithm IP based on Avalon interface
Meter method.The present invention realizes SM3 hash cryptographic algorithm, meets Avalon interface specification.The IP kernel uses hardware description language
VHDL is designed, and the IP kernel can be connected in Nios II system by Avalon bus.
The technical scheme is that
All signals of the package interface of the IP kernel are that clock is synchronous, are sampled in rising edge, high level is effective.Each letter
Number function it is as follows:
Clk: input signal, the clock of Avalon bus, the clock signal as IP kernel；
Reset: input signal is the reset signal of IP kernel；
Data_in [511..0]: input signal, the input of 512 bit data；
Address [4..0]: input signal, address bus, for selecting the register of IP kernel after decoding.
Data_out [255..0]: output signal, the output of 256 bit operation results；
Done: output pin, the complement mark that message blocks operation generates when completing, high level are effective.
The IP kernel includes 4 registers, and word length is 32 bit, and the function of each register is as follows:
1), data register: offset address 0x00-0x0F, for storing one piece of message data of SM3 algorithm, to this
Register only carries out write operation.
2), length register: offset address 0x10, the total length of the message blocks for storing SM3 algorithm, to the deposit
Device can be written and read.
3), operation result register: offset address 0x11-0x18, for storing the message hash operation knot of SM3 algorithm
Fruit only carries out read operation to the register.
4) register: offset address 0x19, is controlled, control register can be written and read, to control IP
The function of core simultaneously inquires state.0 ~ 3 for controlling register is effective, in which: the 0th is IRQ_ENA, and setting 1 expression all ought disappear
Interrupt signal is generated after the completion of breath block operation, does not generate interrupt signal after the completion of clear 0 expression operation, IP kernel works in inquiry mould
Formula；1st is DATA_VALID, and it is effective to set 1 expression message blocks data, and clear 0 indicates that message blocks are invalid；2nd is enabling signal,
Start operation for starting IP kernel；3rd is that signal is completed in every piece of message blocks operation, sets 1 expression, one piece of message blocks operation and completes,
Clear 0 indicates that the non-operation of message blocks is completed.
IP kernel work when, first to length register write-in message blocks total length, backward IP kernel data register
The data of message blocks of the write-in first to operation, after the completion of first message blocks data operation, setting control register
3rd is 1, backward IP kernel second message blocks data to operation is written, and control register is set the 3rd be 0, directly
It is completed to all message blocks data operations, final hash operation result is written in operation result register, passes through
Data_out [255..0] interface is read.
The IP kernel uses the design method of finite state machine to the treatment process of data；The state of state machine shifts
Length condition WAIT_LEN is waited, data mode WAIT_DATA is waited, initial wheel state INITIAL_ROUND, repeats wheel state
DO_ROUND, final wheel state FINAL_ROUND and completion status DONE, each message blocks hash operation need more wheel operations；
Wherein data_stable is data stabilization signal, by controlling register access；Variable i is wheel counter, and NO_ROUNDS is
Constant indicates the total wheel number of processing data block process, is set by length register.
The beneficial effects of the present invention are:
The present invention is designed using Hardware Description Language VHDL, provides SM3 symmetric cryptographic algorithm, meets Avalon bus
Interface specification can be connected in the FPGA for being transplanted to different model, so that flexible design side with Nios II embeded processor
Just, it can satisfy information security field to the application demand of data encrypting and deciphering.
Detailed description of the invention
Fig. 1 is the SM3 Algorithm IP interface schema based on Avalon interface；
Fig. 2 is the state machine transfer figure of IP kernel data processing.
Specific embodiment
More detailed elaboration is carried out to the contents of the present invention below:
The package interface of the IP kernel is as shown in Fig. 1, and all signals are that clock is synchronous, is sampled in rising edge, high electricity
It is flat effective.The function of each signal is as follows:
Clk: input signal, the clock of Avalon bus, the clock signal as IP kernel；
Reset: input signal is the reset signal of IP kernel；
Data_in [511..0]: input signal, the input of 512 bit data；
Address [4..0]: input signal, address bus, for selecting the register of IP kernel after decoding.
Data_out [255..0]: output signal, the output of 256 bit operation results；
Done: output pin, the complement mark that message blocks operation generates when completing, high level are effective.
The IP kernel includes 4 registers, and word length is 32 bit, and the function of each register is as follows:
1), data register: offset address 0x00-0x0F, for storing one piece of message data of SM3 algorithm
(512bit) only carries out write operation to the register.
2), length register: offset address 0x10, the total length of the message blocks for storing SM3 algorithm, to the deposit
Device can be written and read.
3), operation result register: offset address 0x11-0x18, for storing the message hash operation knot of SM3 algorithm
Fruit only carries out read operation to the register.
4) register: offset address 0x19, is controlled, control register can be written and read, to control IP
The function of core simultaneously inquires state.0 ~ 3 for controlling register is effective, in which: the 0th is IRQ_ENA, and setting 1 expression all ought disappear
Interrupt signal is generated after the completion of breath block operation, does not generate interrupt signal after the completion of clear 0 expression operation, IP kernel works in inquiry mould
Formula；1st is DATA_VALID, and it is effective to set 1 expression message blocks data, and clear 0 indicates that message blocks are invalid；2nd is enabling signal,
Start operation for starting IP kernel；3rd is that signal is completed in every piece of message blocks operation, sets 1 expression, one piece of message blocks operation and completes,
Clear 0 indicates that the non-operation of message blocks is completed.
IP kernel work when, first to length register write-in message blocks total length, backward IP kernel data register
The data of message blocks (512bit) of the write-in first to operation, after the completion of first message blocks data operation, setting control
The 3rd of register is 1, backward IP kernel second message blocks data to operation is written, and be arranged and control the 3rd of register
Position is 0, and until all message blocks data operations are completed, final hash operation result is written to operation result register
In, it is read by Data_out [255..0] interface.
The IP kernel uses the design method of finite state machine to the treatment process of data, and the state transition diagram of state machine is such as
Shown in attached drawing 2, including waits length condition WAIT_LEN, waits data mode WAIT_DATA, initial wheel state INITIAL_
ROUND, wheel state DO_ROUND, final wheel state FINAL_ROUND and completion status DONE, each message blocks hash fortune are repeated
It calculates and needs more wheel operations.Wherein data_stable is data stabilization signal, by controlling register access；Variable i is that wheel counts
Device, NO_ROUNDS are constants, indicate the total wheel number of processing data block process, are set by length register, for example, setting is to be shipped
When the data block of calculation is total up to 16 pieces, NO_ROUNDS=16.
The specific work process of state machine are as follows:
(1), after the enabling signal of control register is set to IP kernel, starting state machine, into waiting length condition WAIT_
LEN。
(2), in WAIT_LEN state, the message blocks total length to operation, Zhi Houzhuan is written to the length register of IP kernel
State machine, which enters, waits data mode WAIT_DATA.
(3), in WAIT_DATA state, first data block to operation is written to the data register of IP kernel, works as data
After stabilization, data_stable=' 1 ', state machine enter initial wheel state INITIAL_ROUND at this time.
(4), in INITIAL_ROUND state, state machine carries out the arithmetic operation of first data block, and initial wheel has operated
Cheng Hou, the 3rd block operation complement mark position of setting control register are " 1 ", and entering for register repeats wheel state DO_
ROUND。
(5), in DO_ROUND state, state machine carries out circulate operation, and the 3rd block operation of control register clearly first is complete
It is " 0 " at flag bit, repeats the message blocks operation of corresponding wheel later, finally enters final wheel state FINAL_ROUND.
(6), in FINAL_ROUND state, state machine completes last wheel operation, enters completion status DONE later.
(7), in DONE state, state machine has been completed the operation of all data blocks, and final hash result is written
Operation result register is finally exported from Data_out [255..0] interface.
Claims (3)
1. a kind of design method of the SM3 Algorithm IP based on Avalon interface, which is characterized in that
All signals of the package interface of IP kernel are that clock is synchronous, are sampled in rising edge, high level is effective；The function of each signal
It can be as follows:
Clk: input signal, the clock of Avalon bus, the clock signal as IP kernel；
Reset: input signal is the reset signal of IP kernel；
Data_in [511..0]: input signal, the input of 512 bit data；
Address [4..0]: input signal, address bus, for selecting the register of IP kernel after decoding；
Data_out [255..0]: output signal, the output of 256 bit operation results；
Done: output pin, the complement mark that message blocks operation generates when completing, high level are effective；
The IP kernel includes 4 registers, and word length is 32 bit, and the function of each register is as follows:
1), data register: offset address 0x00-0x0F, for storing one piece of message data of SM3 algorithm, to the deposit
Device only carries out write operation；
2), length register: offset address 0x10, the total length of the message blocks for storing SM3 algorithm can to the register
It is written and read；
3), operation result register: offset address 0x11-0x18, for storing the message hash operation result of SM3 algorithm,
Read operation is only carried out to the register；
4) register: offset address 0x19, is controlled, control register can be written and read, to control IP kernel
Function simultaneously inquires state；
IP kernel work when, first to length register write-in message blocks total length, backward IP kernel data register be written
The data of first message blocks to operation, after the completion of first message blocks data operation, the 3rd of setting control register
Be 1, backward IP kernel second message blocks data to operation is written, and control register is set the 3rd be 0, Zhi Daosuo
Some message blocks data operations are completed, and final hash operation result is written in operation result register, pass through Data_
Out [255..0] interface is read.
2. the method according to claim 1, wherein 0 ~ 3 of control register is effective, in which: the 0th is
IRQ_ENA sets 1 expression and generates interrupt signal after the completion of all message blocks operations, do not generate interruption after the completion of clear 0 expression operation
Signal, IP kernel work in query pattern；1st is DATA_VALID, and it is effective to set 1 expression message blocks data, and clear 0 indicates message blocks
In vain；2nd is enabling signal, starts operation for starting IP kernel；3rd is that signal is completed in every piece of message blocks operation, sets 1 table
Show that one piece of message blocks operation is completed, clear 0 indicates that the non-operation of message blocks is completed.
3. according to the method described in claim 2, it is characterized in that, the IP kernel uses finite state to the treatment process of data
The design method of machine；State machine state transfer include wait length condition WAIT_LEN, wait data mode WAIT_DATA,
Initial wheel state INITIAL_ROUND, wheel state DO_ROUND, final wheel state FINAL_ROUND and completion status are repeated
DONE, each message blocks hash operation need more wheel operations；Wherein data_stable is data stabilization signal, is posted by control
Storage access；Variable i is wheel counter, and NO_ROUNDS is constant, indicates the total wheel number of processing data block process, is posted by length
Storage setting.
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| CN104182696A (en) * | 2014-08-15 | 2014-12-03 | 浪潮电子信息产业股份有限公司 | Design method based on Avalon interface for IP core of AES algorithm |
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| CN104182696A (en) * | 2014-08-15 | 2014-12-03 | 浪潮电子信息产业股份有限公司 | Design method based on Avalon interface for IP core of AES algorithm |
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| SM3杂凑算法的流水线结构硬件实现;蔡冰清 等;《微电子学与计算机》;20150131;第32卷(第1期);第15-18页 * |
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