CN103049710B - Field-programmable gate array (FPGA) chip for SM2 digital signature verification algorithm - Google Patents

Abstract

The invention discloses an FPGA chip used for SM2 digital signature verification algorithm. The FPGA chip includes: a system bus interface, which is used to communicate with the external system of the FPGA chip, obtain the parameters and data required for SM2 digital signature verification from the external system, write them into the SM2 controller, and receive control messages sent by the external system, The working state query message and the operation result query message are sent to the SM2 controller; the SM2 controller is used to trigger the SM2 operation unit according to the control message, and after receiving the working state query message and the operation result query message, through the system bus interface Send the working status and verification results of the SM2 computing unit to the external system; the SM2 computing unit is used to read the parameters and data required for this SM2 digital signature verification from the SM2 controller under the trigger of the SM2 controller, and perform the verification based on the SM2 controller. The SM2 digital signature verification algorithm completes the verification calculation and sends the verification result to the SM2 controller.

Description

FPGA chip for SM2 digital signature verification algorithm

technical field

The invention relates to the technical field of computers, in particular to an FPGA chip used for SM2 digital signature verification algorithm.

Background technique

At the end of 2010, the State Encryption Administration put forward the relevant cryptography algorithm standards in my country, including: SM2 standard, SM3 standard, and SM7 standard. Among them, the SM2 standard is: based on the mathematical problem basis of elliptic curve discrete logarithm, it is a domestic standard evolved on the basis of international related ECC (elliptic curve cryptography) related standard algorithms.

At present, the asymmetric cryptographic algorithm widely used at home and abroad is mainly the RSA algorithm. However, from the perspective of theoretical analysis and application requirements, the security strength of the ECC algorithm (including the SM2 standard algorithm) is higher than that of the RSA algorithm, and the key length is shorter, so the application prospect is better. However, based on the SM2 algorithm, there are not many products in the development of terminal chips.

On the other hand, the State Cryptography Administration requires all domestic systems and terminals using asymmetric cryptographic algorithms to use domestic standards, including SM2 algorithm standards, before 2015. Therefore, systematic research can be carried out in SM2 product development and system solutions.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the present invention provides an FPGA chip for SM2 digital signature verification algorithm.

The present invention provides a kind of FPGA chip that is used for SM2 digital signature verification algorithm, comprises: system bus interface, is used for communicating with the external system of FPGA chip, obtains the required parameter and data of SM2 digital signature verification from external system, and writes Enter the SM2 controller to receive control messages, working status query messages, and operation result query messages sent by the external system, and send them to the SM2 controller; the SM2 controller is connected to the system bus interface and the SM2 computing unit to Trigger the SM2 computing unit, and after receiving the working status query message and the computing result query message, send the working status and verification results of the SM2 computing unit to the external system through the system bus interface; the SM2 computing unit is used for triggering by the SM2 controller , read the parameters and data required for this SM2 digital signature verification from the SM2 controller, perform verification calculation according to the SM2 digital signature verification algorithm, and send the verification result to the SM2 controller.

Preferably, the system bus interface includes: a system bus interface conforming to a general industrial bus standard, or a system bus interface conforming to a user-defined bus interface protocol.

Preferably, the SM2 controller specifically includes: a control register, which is used to trigger the start of the SM2 arithmetic unit through the SM2 start signal according to the control message when receiving a control message sent by the external system through the system bus interface, and trigger the start of the SM2 operation unit through the SM2 reset signal. Reset the SM2 operation unit; the data register is used to receive the parameters and data required for this SM2 digital signature verification sent by the external system through the system bus interface, and store them. After the control register resets the SM2 operation unit, clear the current SM2 digital signature The parameters and data required for signature verification; the status register is used to query the working status of the SM2 arithmetic unit when receiving the working status query message, and send the working status to the external system through the system bus interface; actively notify the external system The SM2 computing unit has completed this verification of the SM2 digital signature; upon receiving the computation result query message, it sends the verification result of this SM2 digital signature verification to the external system through the system bus interface.

Preferably, the SM2 computing unit specifically includes: a first state machine module, used to control the SM2 digital signature verification operation process, and communicate with the SM2 controller; a first modular addition operation module, used to complete The calculation of t=(r'+s') modn in the SM2 digital signature verification algorithm, and the calculation of R=(e'+x ₁ ') modn, where (r'+s') is the signature codeword, and the calculation Digest value of the message H _v () is the summary calculation function, "□" indicates the splicing of two character strings before and after, n is the order of the elliptic curve, x ₁ ' is one of the coordinate elements of the elliptic curve point (x', y'); the first doubling point operation module is used to With the support of field addition and subtraction operations, prime number field multiplication operations, and prime number field division operations, [s′]G and [t′]PA in the SM2 digital signature verification algorithm are calculated in the affine coordinate system, where _G is the base point of the elliptic curve, G=(x _G ,y _G )(G≠O), x _G and y _G are two elements in F _p , and the two elements a and b of the elliptic curve E(F _q ) equation _{∈F q} , PA is the user public key, and also a point on the elliptic curve, [s′] _G refers to the s′ times point of _G , [t′]PA refers to the t′ times point of PA; One-point addition operation module, used to complete the [s′]G in the SM2 digital signature verification algorithm in the affine coordinate system with the support of the underlying prime number field addition and subtraction operations, prime number field multiplication operations, and prime number field division operations Point addition operation of two points and [t′]PA, that is, (x′,y′) ₌ [s′] _G +[t′]PA, where (x′,y′) is point.

Preferably, the first state machine module is specifically used to: read the parameters and data required for this SM2 digital signature verification in the SM2 controller; receive the SM2 start signal sent by the SM2 controller, and start the SM2 computing unit; according to the SM2 digital signature The operation process of the verification algorithm calls the first multiplication point operation module, the first point addition operation module, and the first modulo addition operation module, and performs verification calculations according to the parameters and data required for this SM2 digital signature verification; After the signature verification is completed, obtain the verification result, and return the verification result and completion flag to the SM2 controller; receive the SM2 reset signal sent by the SM2 controller, and reset the SM2 arithmetic unit.

Preferably, the first state machine module is specifically used to: call the first modular addition operation module to calculate t=(r'+s') modn; call the first multiplication point operation module to calculate [s']G and [t']P _A ; call the first point addition operation module to calculate (x', y')=[s'] _G +[t']PA; call the first modular addition operation module to calculate R=(e'+x ₁ ') modn, Check whether R=r' is true, if true, the verification is passed, otherwise the verification is not passed.

Preferably, the SM2 computing unit specifically includes: a coordinate transformation module, which is used to convert point coordinate data on the elliptic curve from an affine coordinate system to a Jacobian coordinate system; a second state machine module, which is used to perform SM2 digital signature verification operations Process control, and communicate with the SM2 controller; The second modulus addition operation module is used to complete the calculation of t=(r'+s') modn in the SM2 digital signature verification algorithm under the Jacobian coordinate system, and R= Calculation of (e′+x ₁ ′)modn, where (r′+s′) is the signature codeword, and calculates the digest value of the message H _v () is the summary calculation function, "□" indicates the splicing of two character strings before and after, n is the order of the elliptic curve, x ₁ ' is one of the coordinate elements of the elliptic curve point (x', y'); the second doubling point operation module is used to With the support of field addition and subtraction operations, prime number field multiplication operations, and prime number field division operations, [s′]G and [t′]PA in the SM2 digital signature verification algorithm are calculated in the Jacobian coordinate system, where _G is the base point of the elliptic curve, G=(x _G ,y _G )(G≠O), x _G and y _G are two elements in F _p , and the two elements a and b of the elliptic curve E(F _q ) equation _{∈F q} , PA is the user public key, and also a point on the elliptic curve, [s′] _G refers to the s′ times point of _G , [t′]PA refers to the t′ times point of PA; The two-point addition operation module is used to complete [s′]G in the SM2 digital signature verification algorithm in the Jacobian coordinate system with the support of addition and subtraction operations in the underlying prime number field, multiplication operations in the prime number field, and division operations in the prime number field Point addition operation of two points and [t′]PA, that is, (x′,y′) ₌ [s′] _G +[t′]PA, where (x′,y′) is point.

Preferably, the prime field multiplication is replaced by a Montgomery multiplication.

Preferably, the multiplier required by the Montgomery multiplication operation is replaced by a digital signal processor DSP resource in the FPGA chip.

Preferably, the second state machine module is specifically used to: read the parameters and data required for this SM2 digital signature verification in the SM2 controller; receive the SM2 start signal sent by the SM2 controller, start the SM2 computing unit; call the second module The addition operation module calculates t=(r'+s') modn; Call the second doubling point operation module to calculate [s'] _G and [t']PA; Call the second point addition operation module to calculate (x', y' )=[s′] _G +[t′]PA; call the second modulo addition operation module to calculate R=(e′+x ₁ ′)modn, check whether R=r′ holds true, if true, pass the verification, otherwise verify Failed; after the SM2 digital signature verification is completed, obtain the verification result, and return the verification result and completion flag to the SM2 controller; receive the SM2 reset signal sent by the SM2 controller, and reset the SM2 arithmetic unit.

The beneficial effects of the present invention are as follows:

With the help of the technical solutions of the embodiments of the present invention, FPGA chip resources are fully utilized, and the computing speed of the SM2 algorithm can be effectively improved; the technical solutions of the embodiments of the present invention can be applied to various security certification fields, and at the same time, according to specific application scenarios and technologies According to the requirements, a flexible configuration method is adopted to achieve a reasonable allocation of system resources and computing efficiency.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the specific embodiments of the present invention are enumerated below.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiment. The drawings are only for the purpose of illustrating a preferred embodiment and are not to be considered as limiting the invention. Also throughout the drawings, the same reference numerals are used to designate the same parts. In the attached picture:

Fig. 1 is the SM2 digital signature verification algorithm flowchart of the embodiment of the present invention;

Fig. 2 is the structural representation of the FPGA chip that is used for SM2 digital signature verification algorithm of the embodiment of the present invention;

Fig. 3 is the schematic diagram of SM2 signature verification FPGA chip internal structure of the embodiment of the present invention;

Fig. 4 is a schematic diagram of the realization of the SM2 signature verification operation unit under the affine coordinate system of the embodiment of the present invention;

Fig. 5 is a schematic diagram of the implementation of the SM2 signature verification operation unit in the Jacobian coordinate system according to the embodiment of the present invention.

detailed description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

The invention provides an FPGA chip used for the SM2 digital signature verification algorithm, and realizes the verification operation of the digital signature in the SM2 national encryption standard based on the FPGA chip. The application scenarios or application requirements are various security terminal systems. The embodiment of the present invention is based on the digital signature verification algorithm in the SM2 standard of the State Cryptography Administration, and realizes the calculation of the prime number field algorithm on the FPGA chip. In addition, through the data conversion between the affine coordinate system and the Jacobian coordinate system, the SM2 algorithm can be optimized and designed, thereby improving the computing efficiency of the FPGA chip. At the same time, since the FPGA chip has programmable and configurable features, the chip bus interface can be developed and designed according to specific system requirements, reducing costs and improving efficiency.

As mentioned above, the FPGA implementation of the SM2 signature algorithm is equivalent to the existing dedicated security chip in terms of computing functions. However, due to the configurable, programmable, and upgradeable characteristics of the FPGA chip, the FPGA implementation of the SM2 digital signature algorithm can be flexibly selected according to specific application scenarios and application requirements for algorithm calculation efficiency and system implementation cost. That is, in the application environment with low real-time requirements of the algorithm, the FPGA chip with relatively low internal resources can be selected to implement the algorithm based on the affine coordinate system; on the other hand, for the application environment with high real-time requirements, you can Choose an FPGA chip with relatively rich internal resources, and use technical means such as algorithm optimization or increase the chip clock to further improve the computing speed and system efficiency. At the same time, according to the specific system bus type, the external system bus of the chip can be flexibly configured to improve the system adaptability of the chip, which is another advantage of FPGA implementation compared with dedicated security chips. The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

Before the technical solution of the embodiment of the present invention is described in detail, the SM2 national standard digital signature verification algorithm is firstly described in detail.

The national standard "SM2 Elliptic Curve Public Key Cryptography Algorithm" is divided into four parts, including: General Provisions, Digital Signature Algorithm, Key Exchange Protocol, and Public Key Encryption Algorithm. The digital signature algorithm also includes: elliptic curve system parameters, user key pair, auxiliary functions, other user information, digital signature generation algorithm and process, digital signature verification algorithm and process, etc.

The embodiment of the present invention mainly completes the FPGA implementation and performance efficiency optimization of the digital signature verification algorithm. The following mainly describes the basic situation of the SM2 digital signature verification algorithm, and then explains the FPGA implementation and optimization later.

SM2 digital signature verification algorithm, as follows:

enter:

1. Elliptic curve parameters: including the scale q of the finite field F _p , the two elements a, b∈F _q , and the base point on E(F _q ) defining the elliptic curve E(F _q ) equation G=(x _G ,y _G )(G≠O), where x _G and y _G are two elements in F _p , the order n of G on the base point E(F _q ) of the elliptic curve, and other optional items (such as the cofactor h of n, etc. );

2. Z _A : the user's identifiable identifier, some elliptic curve system parameters and the hash value of user A's public key;

3. PA _: user's public key;

4. M': message to be verified;

5. (r', s'): the signature code word received by the system.

Output: verification result: verification passed or verification failed.

Step: Fig. 1 is the SM2 digital signature verification algorithm flow chart of the embodiment of the present invention, as shown in Fig. 1, in order to check the received message M' and its digital signature (r', s'), the user as verifier needs Carry out the following operation steps:

Step 1, check whether r'∈[1,n-1] is true, if not, the verification fails, where n is the order of the elliptic curve;

Step 2, check whether s'∈[1,n-1] is true, if not, the verification fails, where n is the order of the elliptic curve;

Step 3, set The "□" operator represents the splicing of the two strings before and after;

Step 4, calculate That is to calculate the digest value of the message, where H _v () is a digest calculation function;

Step 5, convert the signature codeword data type into an integer, calculate t=(r'+s') modn, if t=0, then the verification fails;

Step 6, calculate the elliptic curve point (x', y')=[s'] _G +[t']PA, where (x', y') is the point on the elliptic curve, [s']G and [t ′]PA is point doubling operation [s′] _G +[t′] _PA is point addition operation;

Step 7, calculate R=(e′+x ₁ ′) modn, check whether R=r′ holds true, if true, the verification is passed; otherwise, the verification fails, where x ₁ ′ is the elliptic curve point calculated in the above step 6 ( x', y') coordinate element.

The technical solutions of the embodiments of the present invention will be described in detail below.

According to an embodiment of the present invention, a kind of FPGA chip that is used for SM2 digital signature verification algorithm is provided, and Fig. 2 is the structural representation of the FPGA chip that is used for SM2 digital signature verification algorithm of the embodiment of the present invention, as shown in Fig. 2, According to the embodiment of the present invention, the FPGA chip for SM2 digital signature verification algorithm includes: system bus interface 20, SM2 controller 22, and SM2 computing unit 24, and each module of the embodiment of the present invention will be described in detail below.

The system bus interface 20 is used to communicate with the external system of the FPGA chip, obtain the parameters and data required for SM2 digital signature verification from the external system, and write them into the SM2 controller 22, and receive control messages and work status inquiries sent by the external system Message, and operation result query message, and send to SM2 controller 22;

Wherein, the system bus interface 20 includes: a system bus interface 20 conforming to a general industrial bus standard, or a system bus interface 20 conforming to a user-defined bus interface protocol.

The SM2 controller 22 is connected with the system bus interface 20 and the SM2 computing unit 24, and is used to trigger the SM2 computing unit 24 according to the control message. Send the working status and verification results of the SM2 arithmetic unit 24;

The SM2 controller 22 specifically includes:

The control register is used to trigger the start of the SM2 computing unit 24 through the SM2 start signal, and trigger the SM2 computing unit 24 to reset through the SM2 reset signal according to the control message when receiving the control message sent by the external system through the system bus interface 20;

The data register is used to receive the parameters and data required for this SM2 digital signature verification sent by the external system through the system bus interface 20, and store them. After the control register resets the SM2 arithmetic unit 24, the SM2 digital signature verification place is cleared. required parameters and data;

The state register is used to inquire about the working status of the SM2 computing unit 24 when receiving the working status query message, and sends the working status to the external system through the system bus interface 20; actively inform the external system that the SM2 computing unit 24 has completed this Secondary SM2 digital signature verification; in the case of receiving the operation result query message, send the verification result of this SM2 digital signature verification to the external system through the system bus interface 20 .

The SM2 computing unit 24 is used to read the parameters and data required for this SM2 digital signature verification from the SM2 controller 22 under the trigger of the SM2 controller 22, and perform verification calculation according to the SM2 digital signature verification algorithm. The results are sent to the SM2 controller 22 . The structure of the SM2 arithmetic unit 24 will be described below with two examples.

Example 1

The SM2 computing unit 24 specifically includes:

The first state machine module is used to perform SM2 digital signature verification operation flow control, and communicate with the SM2 controller 22;

The first state machine module is specifically used to: read the parameters and data required for this SM2 digital signature verification in the SM2 controller 22; receive the SM2 start signal sent by the SM2 controller 22, start the SM2 computing unit 24; according to the SM2 digital signature The operation process of the verification algorithm calls the first multiplication point operation module, the first point addition operation module, and the first modulo addition operation module, and performs verification calculations according to the parameters and data required for this SM2 digital signature verification; After the signature verification is completed, the verification result is obtained, and the verification result and completion flag are returned to the SM2 controller 22; the SM2 reset signal sent by the SM2 controller 22 is received, and the SM2 computing unit 24 is reset.

Among them, according to the operation process of the SM2 digital signature verification algorithm, the first multiplication point operation module, the first point addition operation module, and the first model addition operation module are called, and the verification calculation is performed according to the parameters and data required for this SM2 digital signature verification. Specifically include the following processing:

Call the first modular addition operation module to calculate t=(r'+s') modn; Call the first doubling point operation module to calculate [s'] _G and [t']PA; Call the first point addition operation module to calculate (x ',y')=[s'] _G +[t']PA; call the first modulo addition operation module to calculate R=(e'+x ₁ ')modn, check whether R=r' is true, and verify if it is true pass, otherwise the verification fails.

The first modular addition operation module is used to complete the calculation of t=(r'+s') modn in the SM2 digital signature verification algorithm under the affine coordinate system, and the calculation of R=(e'+x ₁ ') modn , where (r'+s') is the signature codeword, and the digest value of the message is calculated H _v () is the summary calculation function, "□" indicates the concatenation of the two character strings before and after, n is the order of the elliptic curve, and x ₁ ' is one of the coordinate elements of the elliptic curve point (x', y');

The first multiplication point calculation module is used to calculate [s′] in the SM2 digital signature verification algorithm in the affine coordinate system with the support of the addition and subtraction operation of the underlying prime number field, the multiplication operation of the prime number field, and the division operation of the prime number field G and [t′]PA, where G is the base point of the elliptic curve, G=(x _G ,y _G )( _G ≠O), x _G and y _G are two elements in F _p , the elliptic curve E The two elements a, b∈F _q , P _A of the (F _q ) equation are the user public key and a point on the elliptic curve, [s′]G refers to the s′ times point of G, [t′]P _A refers to the t′ times point of P _A ;

The first point addition operation module is used to complete [s′] in the SM2 digital signature verification algorithm in the affine coordinate system with the support of addition and subtraction operations in the underlying prime number field, multiplication operations in the prime number field, and division operations in the prime number field Point addition operation of two points _G and [t′]PA, that is, (x′,y′)=[s′] _G +[t′]PA, where (x′,y′) is an elliptic curve on point.

Example 2:

The SM2 computing unit 24 specifically includes:

Coordinate conversion module, used for converting the point coordinate data on the elliptic curve from the affine coordinate system to the Jacobian coordinate system;

The second state machine module is used for performing SM2 digital signature verification operation process control, and communicates with the SM2 controller 22;

The second state machine module is specifically used to: read the parameters and data required for this SM2 digital signature verification in the SM2 controller 22; receive the SM2 start signal sent by the SM2 controller 22, start the SM2 computing unit 24; call the second module The addition operation module calculates t=(r'+s') modn; Call the second doubling point operation module to calculate [s'] _G and [t']PA; Call the second point addition operation module to calculate (x', y' )=[s′] _G +[t′]PA; call the second modulo addition operation module to calculate R=(e′+x ₁ ′)modn, check whether R=r′ holds true, if true, pass the verification, otherwise verify Not through; after this SM2 digital signature verification is completed, obtain the verification result, and return the verification result and completion flag to the SM2 controller 22; receive the SM2 reset signal sent by the SM2 controller 22, and reset the SM2 computing unit 24.

The second modular addition operation module is used to complete the calculation of t=(r'+s') modn in the SM2 digital signature verification algorithm under the Jacobian coordinate system, and the calculation of R=(e'+x ₁ ') modn , where (r'+s') is the signature codeword, and the digest value of the message is calculated H _v () is the summary calculation function, "□" indicates the concatenation of the two character strings before and after, n is the order of the elliptic curve, and x ₁ ' is one of the coordinate elements of the elliptic curve point (x', y');

The second doubling point calculation module is used to calculate [s′] in the SM2 digital signature verification algorithm in the Jacobian coordinate system with the support of addition and subtraction operations in the underlying prime number field, multiplication operations in the prime number field, and division operations in the prime number field G and [t′]PA, where G is the base point of the elliptic curve, G=(x _G ,y _G )( _G ≠O), x _G and y _G are two elements in F _p , the elliptic curve E The two elements a, b∈F _q , P _A of the (F _q ) equation are the user public key and a point on the elliptic curve, [s′]G refers to the s′ times point of G, [t′]P _A refers to the t′ times point of P _A ;

The second point addition operation module is used to complete [s′] in the SM2 digital signature verification algorithm in the Jacobian coordinate system with the support of addition and subtraction operations in the underlying prime number field, multiplication operations in the prime number field, and division operations in the prime number field Point addition operation of two points _G and [t′]PA, that is, (x′,y′)=[s′] _G +[t′]PA, where (x′,y′) is an elliptic curve on point.

It should be noted that, in the above-mentioned example 1 and example 2, the multiplication operation of the prime field can be replaced by the multiplication operation of Montgomery. In addition, the multiplier required by the Montgomery multiplication operation can also be replaced by the digital signal processor DSP resource in the FPGA chip.

The technical solutions of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Fig. 3 is the schematic diagram of the internal structure of the SM2 signature verification FPGA chip of the embodiment of the present invention, as shown in Fig. 3, completes SM2 digital signature verification based on the FPGA chip, the overall implementation of the chip includes three parts: system bus interface 20, SM2 controller 22 , and the SM2 arithmetic unit 24.

The system bus interface 20, the SM2 controller 22, and the SM2 computing unit 24 will be described respectively below.

1. System bus interface 20

The implementation of the system bus interface 20 is relatively flexible. It can be a general industrial bus standard or a user-defined bus interface protocol, which needs to be designed and developed according to specific system requirements. The function of the system bus interface 20 is mainly to communicate between the FPGA-based SM2 signature verification chip and the external system of the chip, including writing of parameters and data required for signature verification, control of the SM2 chip, and query of chip status and calculation results.

2. SM2 controller 22

The implementation of the SM2 controller 22 is mainly a register set. In terms of functions, it mainly includes: control registers, data registers, and status registers. The register set of the SM2 controller 22 can be regarded as an intermediate bridge or intermediate link between the bus interface and the SM2 arithmetic unit 24 , and the SM2 arithmetic unit 24 can be controlled or accessed by an external system through the SM2 controller 22 .

control register

The control register has two signal bits, which are functionally divided into: SM2 start signal and SM2 reset signal. The SM2 start signal is mainly used for the calculation start function of the SM2 chip. This control function is completed by a trigger signal, which can be level triggered or edge triggered, and it can be measured according to the design requirements; the external system communicates to the SM2 controller 22 through the bus interface. A write to the control register triggers this signal. The SM2 reset signal is mainly used for the reset of the SM2 arithmetic unit 24. This reset signal is active at low level. The external system writes the trigger signal to the control register of the SM2 controller 22 through the bus interface. This signal is generally completed in the SM2 arithmetic unit 24. For an SM2 signature verification operation, the external system takes the verification result and sets the bit. By setting the bit, the SM2 computing unit 24 can be reset to prepare for a new SM2 signature verification calculation.

data register

The data register is mainly used to store the data required by the calculation of the SM2 arithmetic unit 24, and these data include: the required elliptic curve parameters (scale q, two elements a and b of the elliptic curve equation, base point G (main is the coordinate element of the base point), the order n of the base point _G , and other optional items, etc.), the user public key PA for verification calculation, and the digest of the message to be verified Signature codes (r', s') words etc. used for verification calculation (note that the chip design of the present invention mainly completes steps 5 to 7 of the SM2 digital signature verification algorithm. The external system of the chip is completed, and the following steps with large amount of calculation are completed inside the chip, which can save the area and cost of the chip); among them, the parameters of the elliptic curve can refer to the reference parameters given in the SM2 standard, or can be calculated by the user through the previous verification The resulting elliptic curve parameters. The data register is used as a data cache, and the data is ready before the SM2 computing unit 24 is triggered to start computing, so before the SM2 computing unit 24 starts, an external system is required to write the above-mentioned data through the external bus interface; after the SM2 computing unit 24 starts computing , the SM2 computing unit 24 reads the above data; after the data is read, the data register can wait for the completion of the SM2 signature verification calculation, and clear the SM2 computing unit 24 after resetting, and wait for a new SM2 computing before the new Data is written.

status register

The status register can be used to query the working status of the arithmetic unit 24 of the chip SM2, including: idle, computing, and computing completed. In addition, the status register may include an operation completion flag bit, which is used to give an interrupt flag of the external system, through which the external system SM2 can be proactively notified that the computation is completed. At the same time, the status register also has a flag bit, called the result flag bit, which is used to indicate the verification result, including two types: verification success and verification failure. The external system can read the flag bit to obtain the operation result.

3. SM2 computing unit 24

The embodiment of the present invention is mainly designed and implemented based on the internal structure of the above-mentioned SM2 signature verification FPGA chip, and the main work is concentrated on the SM2 computing unit 24 . First, design, implement, and verify in the affine coordinate system; then, in the Jacobian coordinate system, optimize the relevant algorithm and calculation structure of the SM2 operation unit 24, thereby improving the calculation speed of SM2 signature verification. This invention is based on FPGA for chip design, the basic structure is still three main parts as shown in Figure 3, the difference lies in the implementation of SM2 arithmetic unit 24 is different. It should be noted that the implementation of the SM2 operation unit 24 in FIG. 3 is based on an affine coordinate system. Two types of realization of the SM2 operation unit 24: in the affine coordinate system, the verification operation unit of the SM2 signature is realized as a basic implementation; in the Jacobian coordinate system, the verification operation unit of the SM2 signature is realized, which is an optimization that can improve the operation speed Implementation scheme, but it will take up more FPGA chip resources. For details, refer to the description below.

Realization of SM2 Signature Verification Operation Unit in Affine Coordinate System

Fig. 4 is a schematic diagram of the implementation of the SM2 signature verification operation unit under the affine coordinate system of the embodiment of the present invention. As shown in Fig. 4, the SM2 operation unit 24 communicates with the SM2 controller 22, and the signal types include: control signal writing, data writing input, status and result readout, and its signal functions correspond to the functions of the control register, data register and status register in the SM2 controller 22 respectively.

It should be pointed out that the SM2 operation unit 24 mainly completes the operation process of step 5 to step 7 of the SM2 digital signature verification algorithm. Because the calculation of the signature steps is small, it can be completed outside the chip.

As shown in Fig. 4, the internal structure of SM2 operation unit 24 includes: a state machine module, a doubling point operation module, and a point addition operation module (the point addition refers to the point addition operation of points on the elliptic curve, which requires the underlying prime number domain operation support, Including prime number field multiplication, prime number field division, and prime number field addition and subtraction), modulo addition operation module.

1. State machine module

According to the design characteristics of the FPGA chip state machine, the main functions of the state machine in the SM2 operation unit 24 are: SM2 operation flow control, and the communication function with the SM2 controller 22 . The state control transfer process of the state machine is: read the data of the data register in the SM2 controller 22 --> respond to the start signal of the control register in the SM2 controller 22 --> perform SM2 calculation --> SM2 calculation is completed, and the calculation result is obtained , the result and the completion flag are returned to the status register of the SM2 control register—>wait for the reset signal of the SM2 controller 22.

The functions of the state machine are as follows:

(1) SM2 data reading mainly reads the data of the data register in the SM2 controller 22, which is the first work to be completed by the state machine before a complete SM2 operation.

(2) SM2 control signal response: mainly responds to the start signal and reset signal given by the SM2 controller 22 . In response to the start signal, the SM2 calculation is started; in response to the reset signal, the SM2 computing unit 24 is reset to prepare for a new calculation.

(3) Control the SM2 calculation process, according to the calculation requirements of steps 5 to 7 of the SM2 digital signature verification algorithm, schedule each calculation module once in order, specifically:

Modular addition operation mainly completes t=(r'+s') modn calculation;

Doubling point operation successively once, [s′] _G and [t′]PA;

Point addition operation, [s′] _G +[t′]PA;

Modulo addition operation, R=(e'+x ₁ ')modn.

(4) Give and verify the SM2 signature verification result, and return the status and verification result to the status register of the SM2 controller 22 .

2. Point addition operation module

This module mainly completes the point addition operation of the two points [s′]G and [t′]PA in step 6 of the SM2 digital signature verification algorithm, that is, (x′,y′) ₌ [s′]G+[t′] P _A .

The dot addition operation rules are listed below, as follows:

(1) Assuming two points P ₁ =(x ₁ ,y ₁ ) and P ₂ =(x ₂ ,y ₂ ), calculate P ₃ =(x ₃ ,y ₃ )=P ₁ +P ₂ ;

(2) then $x_3={\left(\frac{{\mathrm{the\; y}}_2-{\mathrm{the\; y}}_1}{x_2-x_1}\right)}^2-x_1-x_2$ and ${\mathrm{the\; y}}_3=\left(\frac{{\mathrm{the\; y}}_2-{\mathrm{the\; y}}_1}{x_2-x_1}\right)(x_1-x_3)-{\mathrm{the\; y}}_1.$

According to the above operation rules, it can be seen that the elliptic curve point addition operation requires the support of addition and subtraction operations in the underlying prime number field, multiplication operations in the prime number field, and division operations in the prime number field.

3. Multiplier calculation module

The doubling point calculation module is mainly responsible for completing the two calculations of [s′] _G and [t′]PA in step 6 of the SM2 digital signature verification algorithm.

In the embodiment of the present invention, [s′] _G is the point multiplication operation completed first, and [t′]PA is the point multiplication operation to be completed later. _G is the base point of the elliptic curve, and PA is the user's public key, which is also a point on the elliptic curve. [s'] _G refers to the s'time point of _G , and [t']PA refers to the t'time point of PA. According to the relevant theoretical knowledge of the elliptic curve, the point on the elliptic curve is still on the elliptic curve, that is, the point is also a point of the elliptic curve, so [s′]G and [t′ ]P _A are two points on the elliptic curve. The result of the point addition of these two points is also a point on the elliptic curve.

From the perspective of the calculation process, the essence of doubling operation can be regarded as multiple point addition operations, so the doubling operation still needs to call the underlying prime number field addition and subtraction operations, prime number field multiplication operations, and prime number field division operation modules.

4. Modular addition operation module

The modulo addition operation is relatively simple, that is, after the data is summed, the modulo operation is performed. Mainly responsible for completing the calculation of t=(r'+s') modn in step 5 of the SM2 digital signature verification algorithm, and the calculation of R=(e'+x ₁ ') modn in step 7.

In the above-mentioned affine coordinate system, the SM2 signature verification operation unit implemented based on the FPGA chip generally requires more than 500 addition calculations to complete an SM2 signature operation, and the corresponding division calculation requires more than 20,000 times. For example, according to the calculation rule of SM2 point addition operation, one division calculation and three multiplication calculations are required, but the calculation amount of division on the prime number field is about 50 times that of multiplication, so it can be clearly stated that the biggest calculation bottleneck is a large number of division operations .

Here, in order to reduce the amount of division in the affine coordinate system, the Jacobian coordinate system can be introduced. The coordinates in the Jacobian coordinate system can be expressed as, which corresponds to the affine coordinates, so the coordinate vector in the Jacobian coordinate system can be regarded as an intermediate variable, and the mutual conversion between the affine coordinate system and the Jacobian coordinate system can be completed by using it.

Through the mutual conversion between the affine coordinate system and the Jacobian coordinate system, the SM2 signature verification calculation is realized in the Jacobian coordinate system, which can effectively avoid a large number of division calculations and significantly reduce the amount of calculation. And in the process of completing one SM2 operation, only one conversion between the affine coordinate system and the Jacobian coordinate system is required. Even one SM2 signature operation only needs two or three division operations, which can greatly optimize the operation unit and operation speed. In essence, through the transformation of the affine coordinate system and the Jacobian coordinate system, the number of calls to the division calculation amount is effectively eliminated, which is mainly reflected in the effective reduction of the number of calls to the prime field division during the doubling point and point addition calculation process.

As we know before, the division operation can be effectively reduced through the mutual conversion between the affine coordinate system and the Jacobian coordinate system. Therefore, after the optimization of the division operation is implemented, the main computational bottleneck lies in the multiplication operation.

The multiplication operation on the prime number field is a modular multiplication operation, that is, c=a×bmodp. Traditional multiplication either requires division to take the remainder, or a low-rate subtraction. The invention adopts Montgomery multiplication (Montgomery multiplication) to effectively optimize the multiplication calculation of the prime number field, and realizes by converting complex operations into simple low-precision multiplication operations. Montgomery multiplication works as follows:

Algorithm: Montgomery Multiplication (Montgomery multiplication calculation)

enter:

1. Field F _p , modulo p, let p=n ₁ 2 ^D +n ₀ , ${\mathrm{no}}_0^{\′}=-{\mathrm{no}}_0^{-1}\mathrm{mod}{2}^{\mathrm{D.}};$

2. Integer a,b∈[0,p-1], a=a ₁ □2 ^D +a ₀ , b=b ₁ □2 ^D +b ₀ ;

3. Integer $T=\underset{i=0}{\overset{2}{\mathrm{\Σ}}}{2}^{\mathrm{iD}}{t}_i,$ integer m.

Output: c＝a b×R ^-1 modp

step:

Step 1, T = a ₀ b ₀

Step 2, m=(t ₀ n' ₀ ) mod2 ^D ;

Step 3, T=(T+mn ₀ )>>D;

Step 4, T=T+a ₀ b ₁ +a ₁ b ₀ +mn ₁ ;

Step 5, m=(t ₀ n' ₀ ) mod2 ^D ;

Step 6, T=(T+mn ₀ )>>D;

Step 7, c=(T+a ₁ b ₁ +mn ₁ ) modp.

From the implementation steps in the description of the above algorithm, it can be seen that the original modular multiplication operation completed on the prime number field can be converted into several simple low-precision multiplication operations. Therefore, the operation cycle of the original prime number field multiplication operation can be effectively reduced, and the operation speed of the SM2 digital signature verification operation can be improved. However, based on the above-mentioned Montgomery multiplication operation, the present invention is realized through FPGA programming, which needs to occupy more FPGA logic resources. Therefore, in the Jacobian coordinate system, to realize the SM2 digital signature verification operation, the FPGA chip area is larger than that in the affine coordinate system. The implementation of the SM2 digital signature verification operation unit under the Jacobian coordinate system will be described below.

Realization of SM2 Signature Verification Operation Unit in Jacobian Coordinate System

Fig. 5 is a schematic diagram of the implementation of the SM2 signature verification operation unit in the Jacobian coordinate system of the embodiment of the present invention, as shown in Fig. 5, compared with Fig. 4, the main differences are:

1. The coordinate conversion module is added, which is used to convert the point coordinate data on the elliptic curve from the affine coordinate system to the Jacobian coordinate system. It is mainly the point data of the data register in the SM2 controller, and the conversion is completed by the coordinate conversion module first After that, it is written into the SM2 arithmetic unit for doubling point calculation and point addition calculation;

2. The doubling point calculation and point addition calculation in Figure 5 are all completed in the Jacobian coordinate system, and the number of calls to the underlying arithmetic unit is significantly reduced, especially the calls to the division and multiplication operations of the prime number field;

3. In Figure 5, using the Montgomery multiplication module to replace the original prime field multiplication operation can effectively improve the system operation speed.

The functions and module realization of each part shown in FIG. 5 are basically the same as those shown in FIG. 4 , and will not be repeated here.

It should be noted that some types of FPGA chips contain DSP resources inside. These DSP resources are optimized multiplication and accumulation modules. Under the condition that the number of DSPs is allowed, it is better to use DSP to realize simple low-precision multiplication operations than FPGA chips. internal general multiplier.

Therefore, by using the rich DSP resources inside the FPGA chip, further hardware optimization can be done for the low-precision multiplication calculation in the Montgomery multiplication operation. That is to use the internal DSP resources of the FPGA chip to replace the required multiplier for the original Montgomery operation. Then the calculation efficiency of Montgomery multiplication can be nearly doubled, which is also an optimization method under the condition of specific application requirements and system cost.

Table 1 shows the comparison of M2 algorithm FPGA implementation and its optimized resource efficiency. As shown in Table 1, the listed FPGA implementation methods are mainly: under the affine coordinate system and the Jacobian coordinate system, the average SM2 signature verification calculation is completed once. compare results. These include: affine coordinate system implementation, Jacobian coordinate system implementation (using 1 times DSP resources instead of ordinary multipliers), Jacobi coordinate system implementation and optimization scheme 1 (using 1 times DSP resources instead of ordinary multipliers, and comprehensive tool Adder optimization), Jacobian coordinate system implementation and optimization scheme 2 (using 2 times DSP resources instead of ordinary multipliers).

Table 1

To sum up, with the help of the technical solution of the embodiment of the present invention, the method of mutual conversion between the affine coordinate system and the Jacobian coordinate system is adopted, and the FPGA chip resources are fully utilized, which can effectively improve the operation speed of the SM2 algorithm. The implementation method and optimization method of the present invention can be applied to various security authentication fields, and at the same time, according to specific application scenarios and technical requirements, a flexible configuration method is adopted to realize reasonable allocation of system resources and computing efficiency.

The algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other device. Various generic systems can also be used with the teachings based on this. The structure required to construct such a system is apparent from the above description. Furthermore, the present invention is not specific to any particular programming language. It should be understood that various programming languages can be used to implement the content of the present invention described herein, and the above description of specific languages is for disclosing the best mode of the present invention.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, in order to streamline this disclosure and to facilitate an understanding of one or more of the various inventive aspects, various features of the invention are sometimes grouped together in a single embodiment, figure, or its description. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.

Those skilled in the art can understand that the modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment. Modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore may be divided into a plurality of sub-modules or sub-units or sub-assemblies. All features disclosed in this specification (including accompanying claims, abstract and drawings), as well as any method or method so disclosed, may be used in any combination, except that at least some of such features and/or processes or units are mutually exclusive. All processes or units of equipment are combined. Each feature disclosed in this specification (including accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will understand that although some embodiments described herein include some features included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of the invention. and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.

The various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art should understand that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the components in the FPGA chip used for the SM2 digital signature verification algorithm according to the embodiment of the present invention Or full functionality. The present invention can also be implemented as an apparatus or an apparatus program (for example, a computer program and a computer program product) for performing a part or all of the methods described herein. Such a program for realizing the present invention may be stored on a computer-readable medium, or may be in the form of one or more signals. Such a signal may be downloaded from an Internet site, or provided on a carrier signal, or provided in any other form.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

Claims (9)

1. a kind of fpga chip for SM2 digital signature verification algorithm is it is characterised in that include：

System bus interface, for being communicated with the external system of described fpga chip, obtains SM2 number from described external system Parameter data needed for word signature verification, and write described SM2 controller, the control receiving described external system transmission disappears Breath, working condition query messages and operation result query messages, and it is sent to described SM2 controller；

SM2 controller, is connected with described system bus interface and described SM2 arithmetic element, for being touched according to described control message Send out SM2 arithmetic element described, after receiving described working condition query messages and described operation result query messages, by institute State working condition and the result that system bus interface sends described SM2 arithmetic element to described external system；

SM2 arithmetic element, under the triggering of described SM2 controller, reading this SM2 numeral from described SM2 controller Parameter data needed for signature verification, carries out carrying out checking calculating according to described SM2 digital signature verification algorithm, will checking knot Fruit is sent to described SM2 controller；

Described SM2 arithmetic element specifically includes：

Coordinate transferring, for being carried out turning to Jacobi Coordinate system from affine coordinate system to the point coordinate data on elliptic curve Change；

Second state machine module, is used for carrying out SM2 digital signature authentication computing Row control, and is carried out with described SM2 controller Communication；

Second mould adds computing module, for complete under Jacobi Coordinate system the t=in SM2 digital signature verification algorithm (r '+ S ') modn calculating, and R=(e '+x₁') calculating of modn, wherein, (r '+s ') is signature code word, calculates the summary of message ValueH_v() is digest calculations function,Represent the splicing of former and later two character strings, n is The rank of elliptic curve, x₁' it is one of elliptic curve point (x ', y ') coordinate element；

Second point doubling module, in bottom prime field signed magnitude arithmetic(al), prime field multiplying and prime field division Under the support of computing, calculate [s '] G and [t '] P in SM2 digital signature verification algorithm under Jacobi Coordinate system_A, wherein, G It is the basic point of elliptic curve, G=(x_G,y_G) (G ≠ O), x_GAnd y_GIt is F_pIn two elements, elliptic curve E (F_q) equation two Individual element a, b ∈ F_q、P_AIt is client public key, is also a point on elliptic curve, [s '] G refers to s ' times of point of G, [t '] P_AIt is Refer to P_AT ' times of point；

Second point adds computing module, in bottom prime field signed magnitude arithmetic(al), prime field multiplying and prime field division Under the support of computing, complete [s '] G in SM2 digital signature verification algorithm and [t '] P under Jacobi Coordinate system_ATwo points Point add operation, i.e. (x ', y ')=[s '] G+ [t '] P_A, wherein, (x ', y ') is the point on elliptic curve.

2. fpga chip as claimed in claim 1 is it is characterised in that described system bus interface includes：Meet universal industrial The system bus interface of bus standard；Or meet the system bus interface of User Defined bus inferface protocol.

3. fpga chip as claimed in claim 1 is it is characterised in that described SM2 controller specifically includes：

Control register, for receiving, by described system bus interface, the described control message that described external system sends In the case of, according to described control message, started by the described SM2 arithmetic element of SM2 enabling signal triggering, resetted by SM2 The described SM2 arithmetic element of signal triggering resets；

Data register, for receiving, by described system bus interface, this SM2 digital signature that described external system sends The required parameter data of checking, and stored, after described control register resets described SM2 arithmetic element, empty this Parameter data needed for secondary SM2 digital signature authentication；

Status register, for, in the case of receiving described working condition query messages, inquiring about described SM2 arithmetic element Working condition, and described working condition is sent to by described external system by described system bus interface；Described in proactive notification SM2 arithmetic element described in external system has completed this SM2 digital signature authentication；Receiving described operation result query messages In the case of, send the result of this SM2 digital signature authentication to described external system by described system bus interface.

4. fpga chip as claimed in claim 1 it is characterised in that or, described SM2 arithmetic element specifically includes：

First state machine module, is used for carrying out SM2 digital signature authentication computing Row control, and is carried out with described SM2 controller Communication；

First mould adds computing module, for completing the t=(r '+s ') in SM2 digital signature verification algorithm under affine coordinate system The calculating of modn, and R=(e '+x₁') calculating of modn, wherein, (r '+s ') is signature code word, calculates the digest value of messageH_v() is digest calculations function," | | " represents the splicing of former and later two character strings, and n is ellipse The rank of circular curve, x₁' it is one of elliptic curve point (x ', y ') coordinate element；

First point doubling module, in bottom prime field signed magnitude arithmetic(al), prime field multiplying and prime field division Under the support of computing, calculate [s '] G and [t '] P in SM2 digital signature verification algorithm under affine coordinate system_A, wherein, G is The basic point of elliptic curve, G=(x_G,y_G) (G ≠ O), x_GAnd y_GIt is F_pIn two elements, elliptic curve E (F_q) two of equation Element a, b ∈ F_q、P_AIt is client public key, is also a point on elliptic curve, [s '] G refers to s ' times of point of G, [t '] P_ARefer to P_AT ' times of point；

First point add operation module, in bottom prime field signed magnitude arithmetic(al), prime field multiplying and prime field division Under the support of computing, complete [s '] G in SM2 digital signature verification algorithm and [t '] P under affine coordinate system_AThe point of two points Plus computing, i.e. (x ', y ')=[s '] G+ [t '] P_A, wherein, (x ', y ') is the point on elliptic curve.

5. fpga chip as claimed in claim 4 it is characterised in that described first state machine module specifically for：

Read this parameter data needed for SM2 digital signature authentication in described SM2 controller；

Receive the described SM2 enabling signal that described SM2 controller sends, start described SM2 arithmetic element；

According to the computing process invocation of SM2 digital signature verification algorithm the first point doubling module, described first point add fortune Calculate module, described first mould adds computing module, and the parameter data according to needed for this SM2 digital signature authentication is verified Calculate；

After the completion of this SM2 digital signature authentication, obtain the result, described the result and complement mark are returned to institute State SM2 controller；

Receive the described SM2 reset signal that described SM2 controller sends, reset described SM2 arithmetic element.

6. fpga chip as claimed in claim 5 it is characterised in that described first state machine module specifically for：

Call described first mould to add computing module and calculate t=(r '+s ') modn；

Described first point doubling module is called to calculate [s '] G and [t '] P_A；

Described first point add operation module is called to calculate (x ', y ')=[s '] G+ [t '] P_A；

Call described first mould to add computing module and calculate R=(e '+x₁') modn, whether checking R=r ' sets up, if setting up, verifies Pass through, otherwise verify and do not pass through.

7. the fpga chip as described in claim 1 or 4 is it is characterised in that replace with illiteracy brother by described prime field multiplying Horse profit Montgomery multiplying.

8. fpga chip as claimed in claim 7 is it is characterised in that pass through the digital signal processor in described fpga chip DSP resource replaces the multiplier needed for described Montgomery multiplying.

9. fpga chip as claimed in claim 1 it is characterised in that described second state machine module specifically for：

Read this parameter data needed for SM2 digital signature authentication in described SM2 controller；

Receive the described SM2 enabling signal that described SM2 controller sends, start described SM2 arithmetic element；

Call described second mould to add computing module and calculate t=(r '+s ') modn；

Described second point doubling module is called to calculate [s '] G and [t '] P_A；

Call described second point to add computing module and calculate (x ', y ')=[s '] G+ [t '] P_A；

Call described second mould to add computing module and calculate R=(e '+x₁') modn, whether checking R=r ' sets up, if setting up, verifies Pass through, otherwise verify and do not pass through；

After the completion of this SM2 digital signature authentication, obtain the result, described the result and complement mark are returned to institute State SM2 controller；

Receive the described SM2 reset signal that described SM2 controller sends, reset described SM2 arithmetic element.