CN105786528A - Design method of SM3 algorithm IP core based on Avalon interface - Google Patents
Design method of SM3 algorithm IP core based on Avalon interface Download PDFInfo
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Abstract
The invention provides a method for designing an SM3 algorithm IP core based on an Avalon interface, and belongs to the technical field of information security. All signals of an encapsulation interface of the IP core are synchronous in clock, are sampled at a rising edge and are effective in high level; when the IP core works, firstly writing the total length of the message block into the length register, then writing the Data of a first message block to be operated into the Data register of the IP core, after the operation of the first message block Data is finished, setting the 3 rd bit of the control register to be 1, then writing the second message block Data to be operated into the IP core, setting the 3 rd bit of the control register to be 0 until all the operation of the message block Data is finished, writing the final hash operation result into the operation result register, and reading the hash operation result through a Data _ out [255..0] interface. The invention has flexible and convenient design and can meet the application requirements of the information security field on data encryption and decryption.
Description
Technical field
The present invention relates to field of information security technology, particularly relate to the method for designing of a kind of SM3 Algorithm IP based on Avalon interface.
Background technology
Hash algorithm is also called Hash function, hash function, and it is able to the input message of arbitrary finite length is mapped as the output valve of regular length and calculates easy Certain function summary.Hash function is the basic algorithm that in contemporary cryptology, a class is important, in the process building information safety system, it is provided that data integrity certification and the support function that message source is authenticated.Hash function is generally adopted the method for designing of packet iteration, as existing typical case's hash algorithm all adopts MD type packet iteration structure in the world, wherein with SHA-1 algorithm and SHA-256/384/512 algorithm for representative.Such algorithm has compression function nonlinearity height, the advantages such as strong are filled and be grouped to message, but there is also the shortcoming threatening safety.For this, research worker is devoted to design and analysis and the structure of parallel schema hash algorithm, and within 22nd, has finally been issued the SM3 cryptographic Hash algorithm being applicable to commercial cipher application by Password Management office of country in December in 2010.The safety and reliability of SM3 algorithm is high, is widely used to information security field.
Avalon switching bus is a kind of interconnection mechanism connecting on-chip processor and various peripheral hardware in programmable system on chip.It define signal type and the sequential relationship of communication between main and subordinate node so that user can be connected in NiosII system by Avalon bus by oneself is selected or design peripheral module easily.But in trust computing, SM3 algorithm is many at present is realized by software or credible chip, and speed is relatively slow, poor stability.
Summary of the invention
In order to solve above technical problem, the present invention proposes the method for designing of a kind of SM3 Algorithm IP based on Avalon interface.The present invention realizes SM3 hash cryptographic algorithm, meets Avalon interface specification.This IP kernel adopts Hardware Description Language VHDL to design, it is possible to by Avalon bus, this IP kernel is connected in NiosII system.
The technical scheme is that
All signals of the package interface of this IP kernel are that clock synchronizes, and are sampled at rising edge, and high level is effective.The function of each signal is as follows:
Clk: input signal, the clock of Avalon bus, as the clock signal of IP kernel；
Reset: input signal, is the reset signal of IP kernel；
Data_in [511..0]: input signal, 512bit data input；
Address [4..0]: input signal, address bus, for selecting the depositor of IP kernel after decoding.
Data_out [255..0]: output signal, 256bit operation result exports；
Done: output pin, the complement mark produced when message blocks computing completes, high level is effective.
This IP kernel includes 4 depositors, and word length is 32bit, and the function of each depositor is as follows:
1), data register: offset address is 0x00-0x0F, for depositing one piece of message data of SM3 algorithm, this depositor carries out write operation only.
2), length register: offset address is 0x10, for depositing the total length of the message blocks of SM3 algorithm, this depositor can be written and read operation.
3), operation result depositor: offset address is 0x11-0x18, for depositing the message hash operation result of SM3 algorithm, this depositor carries out read operation only.
4), depositor is controlled: offset address is 0x19, it is possible to be written and read operation to controlling depositor, thus controlling function the query State of IP kernel.Controlling 0 ~ 3 of depositor effectively, wherein: the 0th is IRQ_ENA, put 1 expression and produce interrupt signal after all message blocks computings complete, clear 0 represents that computing does not produce interrupt signal after completing, and IP kernel works in query pattern；1st is DATA_VALID, puts 1 expression message blocks data effectively, and clear 0 represents that message blocks is invalid；2nd is enabling signal, is used for starting IP kernel and starts computing；3rd is that every piece of message blocks computing completes signal, puts one piece of message blocks computing of 1 expression and completes, and clear 0 represents that the non-computing of message blocks completes.
During IP kernel work, first the total length of message blocks is write to length register, backward IP kernel data register write first message blocks treating computing data, after first message blocks data operation completes, arranging the 3rd that controls depositor is 1, backward IP kernel write second message blocks data treating computing, and arrange that to control the 3rd of depositor be 0, until all of message blocks data operation completes, final hash operation result is written in operation result depositor, is read by Data_out [255..0] interface.
The processing procedure of data be have employed the method for designing of finite state machine by this IP kernel；The state transfer of state machine includes waiting length condition WAIT_LEN, wait data mode WAIT_DATA, initial wheel state INITIAL_ROUND, repeating wheel state DO_ROUND, final wheel state FINAL_ROUND and completion status DONE, and operation taken turns by each message blocks hash computing needs more；Wherein data_stable is data stabilization signal, by controlling register access；Variable i is wheel enumerator, and NO_ROUNDS is constant, and expression processes the wheel number that data block process is total, length register set.
The invention has the beneficial effects as follows:
The present invention adopts Hardware Description Language VHDL to design, SM3 symmetric cryptographic algorithm is provided, meet Avalon bus interface specifications, can be connected in the FPGA being transplanted to different model with NiosII flush bonding processor, make flexible design convenient, it is possible to meet the information security field application demand to data encrypting and deciphering.
Accompanying drawing explanation
Fig. 1 is based on the SM3 Algorithm IP interface schema of Avalon interface；
Fig. 2 is the state machine transfer figure that IP kernel data process.
Detailed description of the invention
Below present disclosure is carried out more detailed elaboration:
As shown in Figure 1, all signals are that clock synchronizes to the package interface of this IP kernel, are sampled at rising edge, and high level is effective.The function of each signal is as follows:
Clk: input signal, the clock of Avalon bus, as the clock signal of IP kernel；
Reset: input signal, is the reset signal of IP kernel；
Data_in [511..0]: input signal, 512bit data input；
Address [4..0]: input signal, address bus, for selecting the depositor of IP kernel after decoding.
Data_out [255..0]: output signal, 256bit operation result exports；
Done: output pin, the complement mark produced when message blocks computing completes, high level is effective.
This IP kernel includes 4 depositors, and word length is 32bit, and the function of each depositor is as follows:
1), data register: offset address is 0x00-0x0F, for depositing one piece of message data (512bit) of SM3 algorithm, this depositor carries out write operation only.
2), length register: offset address is 0x10, for depositing the total length of the message blocks of SM3 algorithm, this depositor can be written and read operation.
3), operation result depositor: offset address is 0x11-0x18, for depositing the message hash operation result of SM3 algorithm, this depositor carries out read operation only.
4), depositor is controlled: offset address is 0x19, it is possible to be written and read operation to controlling depositor, thus controlling function the query State of IP kernel.Controlling 0 ~ 3 of depositor effectively, wherein: the 0th is IRQ_ENA, put 1 expression and produce interrupt signal after all message blocks computings complete, clear 0 represents that computing does not produce interrupt signal after completing, and IP kernel works in query pattern；1st is DATA_VALID, puts 1 expression message blocks data effectively, and clear 0 represents that message blocks is invalid；2nd is enabling signal, is used for starting IP kernel and starts computing；3rd is that every piece of message blocks computing completes signal, puts one piece of message blocks computing of 1 expression and completes, and clear 0 represents that the non-computing of message blocks completes.
During IP kernel work, first the total length of message blocks is write to length register, backward IP kernel data register write first message blocks (512bit) treating computing data, after first message blocks data operation completes, arranging the 3rd that controls depositor is 1, backward IP kernel write second message blocks data treating computing, and arrange that to control the 3rd of depositor be 0, until all of message blocks data operation completes, final hash operation result is written in operation result depositor, is read by Data_out [255..0] interface.
The processing procedure of data be have employed the method for designing of finite state machine by this IP kernel, the state transition diagram of state machine is as shown in Figure 2, including waiting length condition WAIT_LEN, wait data mode WAIT_DATA, initial wheel state INITIAL_ROUND, repeating wheel state DO_ROUND, final wheel state FINAL_ROUND and completion status DONE, operation taken turns by each message blocks hash computing needs more.Wherein data_stable is data stabilization signal, by controlling register access；Variable i is wheel enumerator, and NO_ROUNDS is constant, and expression processes the wheel number that data block process is total, length register set, for instance, set when the data block of computing is total up to 16 pieces, NO_ROUNDS=16.
The specific works process of state machine is:
(1) after, to IP kernel the enabling signal of control depositor is set, starting state machine, enter and wait length condition WAIT_LEN.
(2), in WAIT_LEN state, writing the message blocks total length treating computing to the length register of IP kernel, state machine enters and waits data mode WAIT_DATA afterwards.
(3), in WAIT_DATA state, first data block treating computing is write to the data register of IP kernel, when, after data stabilization, now data_stable=' 1 ', state machine enters initial wheel state INITIAL_ROUND.
(4), in INITIAL_ROUND state, state machine carries out the arithmetic operation of first data block, and after the operation of initial wheel completes, arranging the 3rd the block computing complement mark position controlling depositor is " 1 ", and the entrance of depositor repeats wheel state DO_ROUND.
(5), in DO_ROUND state, state machine is circulated operation, and the 3rd the block computing complement mark position controlling first clearly depositor is " 0 ", repeats the message blocks computing of corresponding wheel afterwards, finally enters final wheel state FINAL_ROUND.
(6), in FINAL_ROUND state, state machine completes last and takes turns computing, enters completion status DONE afterwards.
(7), in DONE state, state machine has been completed the computing of all data blocks, final hash result write operation result depositor, finally exports from Data_out [255..0] interface.
Claims (3)
1. the method for designing based on the SM3 Algorithm IP of Avalon interface, it is characterised in that
All signals of the package interface of IP kernel are that clock synchronizes, and are sampled at rising edge, and high level is effective；The function of each signal is as follows:
Clk: input signal, the clock of Avalon bus, as the clock signal of IP kernel；
Reset: input signal, is the reset signal of IP kernel；
Data_in [511..0]: input signal, 512bit data input；
Address [4..0]: input signal, address bus, for selecting the depositor of IP kernel after decoding；
Data_out [255..0]: output signal, 256bit operation result exports；
Done: output pin, the complement mark produced when message blocks computing completes, high level is effective；
This IP kernel includes 4 depositors, and word length is 32bit, and the function of each depositor is as follows:
1), data register: offset address is 0x00-0x0F, for depositing one piece of message data of SM3 algorithm, this depositor carries out write operation only；
2), length register: offset address is 0x10, for depositing the total length of the message blocks of SM3 algorithm, this depositor can be written and read operation；
3), operation result depositor: offset address is 0x11-0x18, for depositing the message hash operation result of SM3 algorithm, this depositor carries out read operation only；
4), depositor is controlled: offset address is 0x19, it is possible to be written and read operation to controlling depositor, thus controlling function the query State of IP kernel；
During IP kernel work, first the total length of message blocks is write to length register, backward IP kernel data register write first message blocks treating computing data, after first message blocks data operation completes, arranging the 3rd that controls depositor is 1, backward IP kernel write second message blocks data treating computing, and arrange that to control the 3rd of depositor be 0, until all of message blocks data operation completes, final hash operation result is written in operation result depositor, is read by Data_out [255..0] interface.
2. method according to claim 1, it is characterised in that control 0 ~ 3 of depositor effectively, wherein: the 0th is IRQ_ENA, putting 1 expression and produce interrupt signal after all message blocks computings complete, clear 0 represents that computing does not produce interrupt signal after completing, and IP kernel works in query pattern；1st is DATA_VALID, puts 1 expression message blocks data effectively, and clear 0 represents that message blocks is invalid；2nd is enabling signal, is used for starting IP kernel and starts computing；3rd is that every piece of message blocks computing completes signal, puts one piece of message blocks computing of 1 expression and completes, and clear 0 represents that the non-computing of message blocks completes.
3. method according to claim 2, it is characterised in that the processing procedure of data be have employed the method for designing of finite state machine by this IP kernel；The state transfer of state machine includes waiting length condition WAIT_LEN, wait data mode WAIT_DATA, initial wheel state INITIAL_ROUND, repeating wheel state DO_ROUND, final wheel state FINAL_ROUND and completion status DONE, and operation taken turns by each message blocks hash computing needs more；Wherein data_stable is data stabilization signal, by controlling register access；Variable i is wheel enumerator, and NO_ROUNDS is constant, and expression processes the wheel number that data block process is total, length register set.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106228088A (en) * | 2016-08-11 | 2016-12-14 | 浪潮电子信息产业股份有限公司 | SM4 algorithm IP core design method based on domestic BMC chip |
| WO2024103821A1 (en) * | 2022-11-15 | 2024-05-23 | 浪潮电子信息产业股份有限公司 | Data migration method and apparatus, device, and medium |
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| CN104182696A (en) * | 2014-08-15 | 2014-12-03 | 浪潮电子信息产业股份有限公司 | Design method based on Avalon interface for IP core of AES algorithm |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104182696A (en) * | 2014-08-15 | 2014-12-03 | 浪潮电子信息产业股份有限公司 | Design method based on Avalon interface for IP core of AES algorithm |
Non-Patent Citations (1)
| Title |
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| 蔡冰清 等: "SM3杂凑算法的流水线结构硬件实现", 《微电子学与计算机》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106228088A (en) * | 2016-08-11 | 2016-12-14 | 浪潮电子信息产业股份有限公司 | SM4 algorithm IP core design method based on domestic BMC chip |
| WO2024103821A1 (en) * | 2022-11-15 | 2024-05-23 | 浪潮电子信息产业股份有限公司 | Data migration method and apparatus, device, and medium |
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