CN112558864A - Underwater acoustic data storage device based on FPGA - Google Patents

Underwater acoustic data storage device based on FPGA Download PDF

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Publication number
CN112558864A
CN112558864A CN202011377247.7A CN202011377247A CN112558864A CN 112558864 A CN112558864 A CN 112558864A CN 202011377247 A CN202011377247 A CN 202011377247A CN 112558864 A CN112558864 A CN 112558864A
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China
Prior art keywords
fpga
chip
pin
module
clock
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Inventor
刘耸霄
杨凯强
徐彤彤
李树贤
杨飞
李鑫旺
牛耀
周生启
钟艺玲
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Haiying Enterprise Group Co Ltd
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Haiying Enterprise Group Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

Abstract

The invention provides an underwater acoustic data storage device based on an FPGA, which comprises: the system comprises an FPGA, an acquisition module, a clock module, a configuration circuit module, an SRAM static storage module, an SATA storage module and a power module, wherein the power module provides reliable power for the working modules; the acquisition module is used for acquiring underwater acoustic data, and transmitting the underwater acoustic data to the FPGA after analog-to-digital conversion; the clock module comprises an on-chip clock and an off-chip clock, and the off-chip clock is connected with the FPGA; the configuration circuit module is in communication connection with the FPGA, the FPGA generates and outputs a clock signal to the configuration circuit, and the configuration circuit decompresses the PROM data file output by the FPGA at the working clock frequency; the SRAM static storage module is in communication connection with the FPGA; the SATA storage module is connected with the FPGA to provide multi-path data read-write transmission, a high-performance and low-power-consumption FPGA processor is selected, a plurality of novel framework elements designed for obtaining the best performance, higher integration level and lower power consumption are integrated, the higher system performance level is achieved, and the SATA hard disk is adopted to realize the storage space with larger data volume.

Description

Underwater acoustic data storage device based on FPGA
Technical Field
The invention relates to the field of underwater sound signal detection and acquisition, in particular to an underwater sound data storage device based on an FPGA (field programmable gate array), which is used for acquiring, processing, storing and the like analog signals in the field of underwater sound.
Background
In recent years, along with the progress and development of society, people want to know the living celestial body more and more, compared with the familiar land, people know the sea less, the sea is an indispensable resource of people, and is more worthy of exploration and development, China is bearing important missions and tasks for building the sea and strengthening the country, the continuous exploration of unknown sea becomes an important subject for the development of China, the underwater information needs to be analyzed and processed in order to know the sea, as is well known, most of the underwater information is transmitted in the form of sound waves, the transmission method is effective, sound signals with the underwater information can be collected underwater, and converted into electric signals for processing and analyzing, so that the underwater information can be known, and an important link in the underwater signal processing is the collection and storage of data, this link has been widely used in the fields of sonar and radar.
The traditional underwater acoustic data acquisition and storage circuit mainly has the following defects: (1) the data storage space is small: the underwater collector generally works for a long time under water, the traditional storage method cannot store data collected by long-time work, and in order to improve the data storage space of the underwater collector, an SATA hard disk is selected as a storage medium, so that the high-speed and high-capacity requirements of application in an embedded system can be met, and meanwhile, the high-speed and high-capacity SATA hard disk has stronger error correction capability and improves the reliability of data transmission to a great extent; (2) weak signal processing capability: the traditional underwater sound data acquisition memory is limited by the sensor level of domestic vibration and the like, the analysis frequency range is not wide, certain difficulty is brought to diagnosis of some low-speed machines or bearings, the signal processing function of the data acquisition unit is not strong, only some simple diagnoses can be made on site, precise diagnosis needs to be performed on a computer offline, and the function of the on-site precise diagnosis is weak; (3) the data transmission channels are few: the traditional underwater sound data acquisition memory generally has fewer channels, such as a single channel with SP201 and SC247 types, and a double channel with EG3300 and YE5938 types, and the like, and the fewer channels result in slower data transmission, longer working time and lower acquisition efficiency.
Contents of the invention
The invention provides an underwater acoustic data storage device based on an FPGA (field programmable gate array), which improves the storage space of data volume and achieves higher system performance level, and in order to realize the purpose, the following technical scheme is adopted: the method comprises the following steps: the system comprises an FPGA, an acquisition module, a clock module, a configuration circuit module, an SRAM static storage module, an SATA storage module and a power module, wherein the power module provides reliable power for the working modules; the acquisition module is used for acquiring underwater acoustic data, and transmitting the underwater acoustic data to the FPGA after analog-to-digital conversion; the clock module comprises an on-chip clock and an off-chip clock, and the off-chip clock is connected with the FPGA; the configuration circuit module is in communication connection with the FPGA, the FPGA generates and outputs a clock signal to the configuration circuit, and the configuration circuit decompresses the PROM data file output by the FPGA at the working clock frequency; the SRAM static storage module is in communication connection with the FPGA; the SATA storage module is connected with the FPGA and provides multi-path data read-write transmission.
Preferably, the acquisition module adopts an AD7608 chip, the acquisition module is connected with a 5v single power supply for power supply, and a sampling amplifier and a digital filter are arranged in the acquisition module; XC5VFX30T is adopted by the FPGA, the FPGA is connected with 5v working voltage, and the FPGA generates a logic clock signal through an internal DCM and a PLL.
Preferably, the off-chip clock comprises: the SATA storage module clock circuit comprises a reference clock generating circuit and a SATA storage module clock circuit, wherein the reference clock generating circuit adopts an IDT5V9885 programmable clock generator, the IDT5V9885 comprises two input clocks CLKIN and XTALIN/REFIN, wherein CLKIN is grounded, the IDT5V9885 is programmed through a JTAG interface chip, the IDT5V9885 has 6 output paths, 4 output paths are connected with an FPGA, 1 output path outputs a differential driving clock signal to an Ethernet controller, and 1 output path of the 4 output paths connected with the FPGA provides a differential working clock signal; the clock circuit of the SATA storage module adopts an ICS844071 chip, and the ICS844071 chip outputs a differential clock signal to the STAT storage module.
Preferably, the configuration circuit module adopts an XCF32P chip as a hardware core to configure a master control chip, VCCINT of the XCF32P chip is connected to a 1.8v internal power supply and is connected to a 3.3v power supply voltage, a CLK pin is connected to an FPGA clock pulse signal output, and a D0 pin is connected to an FPGA.
Preferably, the SRAM static memory module adopts an IS61NLP204836B memory chip and IS connected with a 3.3v power supply voltage.
Preferably, the SATA storage module uses two MOLEX connectors, and performs data transmission with the solid state disk by using the SATA storage module.
Preferably, the power module comprises a low dropout linear voltage stabilizing circuit, a switch type voltage stabilizing circuit and an MGT power supply, wherein the switch type voltage stabilizing circuit inputs an external direct current power supply and converts the external direct current power supply into a direct current power supply by voltage reduction; the low-voltage-difference linear voltage stabilizing circuit is connected with 3.3V of input voltage and outputs 0.9V and 2.5V of voltage; the MGT power supply is connected with the output voltage of the switch type voltage stabilizing circuit, and the MGT power supply outputs 1.0v and 1.2v voltages and is used for supplying power to the I/O interface.
Preferably, the switch type voltage stabilizing circuit is provided with a plurality of groups, the switch type voltage stabilizing circuit adopts a PTH08T240 chip, a VIN pin of the PTH08T240 chip is connected with an external direct-current power supply, a VOUT pin of the PTH08T240 chip is connected with an SNSP pin, a resistor is connected between the SNSP pin and a TT pin, and direct-current voltage after voltage reduction is output between the SNSP pin and the SNSN pin; and the output voltage of the PTH08T240 chip is different due to the difference in resistance between the SNSP pin and the TT pin.
Preferably, the low dropout linear voltage regulator circuit is provided with a plurality of groups, the low dropout linear voltage regulator circuit adopts a TPS7A8400ARGRR chip and a TPS51206DSQR chip, a BIAS pin of the TPS7A8400ARGRR chip is connected with 3.3v of voltage, a FB pin and an OUT pin of the TPS7A8400ARGRR chip are connected with a capacitor, a resistor is connected between the OUT pin and a PG pin, the resistors are different, and the PG pin has different output voltages; the TPS51206DSQR chip inputs a 3.3v power supply voltage, a 1.8v VTTREF voltage and a 1.8v VTT LDO voltage and outputs a 0.9v buffer reference voltage and a 0.9v feedback voltage.
Preferably, the MGT power supply adopts a TPS7A8400ARGRR chip, 3.3v or 1.8v voltage is input to an IN pin of the TPS7A8400ARGRR chip, a capacitor is connected to an FB pin and an OUT pin, a resistor is connected between the OUT pin and a PG pin, the resistors are different, and the PG pin has different output voltages.
The invention has the beneficial effects that: (1) the storage space of the underwater acoustic processing circuit of the submerged buoy is increased, and the storage space with larger data volume can be realized by adopting the SATA hard disk; (2) the high-performance and low-power-consumption FPGA processor is selected and integrated with a plurality of novel architecture elements designed for obtaining the best performance, higher integration level and lower power consumption, thereby achieving higher system performance level.
Drawings
FIG. 1 is a block diagram of the hardware architecture for the present patent application;
FIG. 2 is a block diagram of the software architecture of the present patent application;
FIG. 3 is a partial pin diagram of XC5VFX30T according to the present application;
FIG. 4 is a circuit diagram of the AD7608 circuit of the present application;
FIG. 5 is a schematic diagram of a reference clock generation circuit according to the present application;
FIG. 6 is a schematic diagram of a SATA storage module clock circuit according to the present application;
FIG. 7 is a hardware schematic diagram of the present application with respect to configuring a circuit block;
FIG. 8 is a schematic diagram of an SRAM static memory module of the present patent application;
FIG. 9 is a schematic diagram of a SATA storage module according to the present patent application;
FIG. 10 is a schematic diagram of a switched mode voltage regulator circuit according to the present application;
FIG. 11 is a schematic diagram of a low dropout linear voltage regulator circuit according to the present application;
fig. 12 is a schematic diagram of the MGT power supply of the present patent application.
Schematic diagram.
Detailed Description
The invention will now be further described with reference to the accompanying drawings.
As shown in fig. 1, the present patent application includes: the system comprises an FPGA, an acquisition module, a clock module, a configuration circuit module, an SRAM static storage module, an SATA storage module and a power module, wherein the power module provides reliable power for the working modules; the acquisition module is used for acquiring underwater acoustic data, and transmitting the underwater acoustic data to the FPGA after analog-to-digital conversion; the clock module comprises an on-chip clock and an off-chip clock, and the off-chip clock is connected with the FPGA; the configuration circuit module is in communication connection with the FPGA, the FPGA generates and outputs a clock signal to the configuration circuit, and the configuration circuit decompresses the PROM data file output by the FPGA at the working clock frequency; the SRAM static storage module is in communication connection with the FPGA; the SATA storage module is connected with the FPGA and provides multi-path data read-write transmission.
As shown in fig. 4, the acquisition module adopts an AD7608 chip as an acquisition chip with 6-bit and 8-channel synchronous sampling analog-to-digital data, and a sampling amplifier, a digital filter, a 2.5V reference voltage source, and a high-speed serial-parallel interface are built in the device; AD7608 adopts 5V single power supply to supply power, and can process + -10V and + -5V true bipolar input signals, and the digital filter adopts pin drive, and can improve signal-to-noise ratio and reduce 3dB bandwidth, as can be seen from FIG. 4, 8 analog differential signals at the input end complete analog-to-digital conversion through an A/D converter, then complete digital signal filtering through a second-order low-pass filter, and then complete digital signal output through an eight-out-of-one digital selector, digital filtering, serial and parallel interface digital signal output module.
As shown in fig. 3, XC5VFX30T is adopted for the FPGA, which is connected to 5v operating voltage, and generates logic clock signals through internal DCM and PLL.
Preferably, the off-chip clock comprises: a reference clock generating circuit, a SATA storage module clock circuit, as shown in FIG. 5, said reference clock generating circuit employs a programmable clock generator IDT5V9885, which has three kinds of phase locked loops therein that can be programmed independently, each supporting the generation of different non-integer related signals and related clock frequencies by the same clock, said IDT5V9885 includes two input clocks CLKIN, XTALIN/REFIN, wherein CLKIN is grounded, said IDT5V9885 is programmed through JTAG interface chip, and can be programmed automatically when in normal operation, the chip allows the programming user to easily save and restore all configurations of the device through internal EEPROM interface, and the user does not need to program their configurations again; the IDT5V9885 is provided with 6 paths of output, three differential driving clock control signal transmission interfaces of 25MHz, 27MHz and 125MHz, wherein 4 paths of output are connected with the FPGA, 1 path of output is used for outputting differential driving clock signals to the Ethernet controller, and 1 path of output of the 4 paths of output connected with the FPGA provides differential working clock signals.
As shown in fig. 6, the clock circuit of the SATA storage module operates at 75/150MHz, the embedded clock is designed and generated by an ICS chip in the figure, and the chip is a clock signal generator specially used for a high-performance embedded device, the patent uses an ICS844071 chip, and the ICS844071 chip outputs a differential clock signal to the STAT storage module, so that the chip can effectively suppress jitter performance, has a small package size, and can be used in a small processor space.
Preferably, the on-chip clock has the following condition: (1) the initial clocks that satisfy the condition are usually the case where as many as possible of all the initial clocks are already available, which is usually based on a global resource placed in the clock data tree.
(2) Internal logic clocks with different working frequencies required by system work can be generated by using DCM and PLL inside FPGA, so that system delay is avoided, and the clock generated by the internal logic can generate certain delay for the system, thereby directly influencing system function and time sequence.
As shown in fig. 7, the configuration circuit module adopts an XCF32P chip as a hardware core to configure a master control chip, the capacity range is 32MB, the VCCINT of the XCF32P chip is connected to a 1.8v internal power supply and is connected to a 3.3v power supply voltage, the CLK pin is connected to the FPGA clock signal output, the D0 pin is connected to the FPGA, and the XCF32P is required to be able to automatically decompress PROM data files at a 40MHz working clock frequency. When the FPGA is normally in master serial mode, a configurable clock is automatically generated to drive the PROM, and when CF is high, only a short data access burst time is found after the CE and OE signals are enabled, at which time data can be obtained from the PROM (D0) pin connected to the DIN pin driving the FPGA[7]. The FPGA automatically completes the configuration of data by generating a series of clock pulse signals through an external clock. For example, when the FPGA is in a slave serial mode, both the PROM and FPGA can typically be clocked directly using an external clock signal, and the clock that produces the PROM only on the XCFxxP family can be used directly to drive one configurable serial clock of the FPGA.
As shown in fig. 8, the SRAM IS generally widely considered as a high-speed data flow and cache storage device capable of having very low system response time and very fast and high throughput, and the interface IS also very simple, the SRAM static storage module of this patent employs an IS61NLP204836B memory chip, IS connected with a 3.3v power supply voltage, IS a memory with a static data access function, and can correctly store a large amount of data stored inside it without replacing or refreshing an external storage circuit, and has a high storage performance, the serial high-speed and low-power SRAM controllers can provide a stable and high-performance "no-wait" state for a user, and generally can be mounted to a pcb bus of MicroBlaze when in use, and the controller of the Xilinx multi-channel external storage interface controls the user.
As shown in fig. 9, the SATA storage module employs two groups of MOLEX connectors, each group has a pair of differential input and differential output, and performs data transmission with the solid state disk by using the SATA storage module, the SATA storage module is collocated with an 840pro solid state disk from samsung, which has a particularly strong random read-write capability, and the main control unit employs an ARM architecture-based Cortex-R4 series three-core processor S4LN021X01-8030 MDX chip independently developed and produced by samsung, and has strong multitask and multi-path data transmission capability. .
Preferably, the power module comprises a low dropout linear voltage stabilizing circuit, a switch type voltage stabilizing circuit and an MGT power supply, wherein the switch type voltage stabilizing circuit inputs an external direct current power supply and converts the external direct current power supply into a direct current power supply by voltage reduction; the low-voltage-difference linear voltage stabilizing circuit is connected with 3.3V of input voltage and outputs 0.9V and 2.5V of voltage; the MGT power supply is connected with the output voltage of the switch type voltage stabilizing circuit, and the MGT power supply outputs 1.0v and 1.2v voltages and is used for supplying power to the I/O interface.
As shown in fig. 10, the switching regulator is provided with 3 sets, and has the characteristics of high power supply efficiency and high output current. The voltage output conversion efficiency is high, but the voltage output conversion efficiency has disadvantages that the output noise is high, so that a plurality of switch inductance circuit elements are needed for voltage conversion, the switch type voltage stabilizing circuit adopts a PTH08T240 chip, a VIN pin of the PTH08T240 chip is connected with an external direct current power supply, a VOUT pin of the PTH08T240 chip is connected with an SNSP pin, a resistor is connected between the SNSP pin and a TT pin, and direct current voltage after voltage reduction is output between the SNSP pin and the SNSN pin; and the output voltage of the PTH08T240 chip is different due to the difference in resistance between the SNSP pin and the TT pin.
As shown IN fig. 11, the low dropout linear voltage regulator circuit has 3 sets, the design of the low dropout linear voltage regulator (LDO) circuit greatly saves the space of the circuit, the noise of the output load circuit is small, and the input load voltage can be responded to the change immediately, the capacitance of the input end can effectively reduce the inductance of the input end, and the capacitance of the output end can greatly improve the stability, the low dropout linear voltage regulator circuit adopts two sets of TPS7a8400ARGRR chips and 1 set of TPS51206DSQR chips, IN each set of TPS7a8400ARGRR chips, the BIAS of the TPS7a8400ARGRR chip and the pin IN are connected to 3.3v voltage, the FB pin and the pin of the TPS7a8400ARGRR chip are connected to a capacitor, the pin OUT and the pin PG are connected to a resistor, and the pin PG is different IN the output voltage; the TPS51206DSQR chip inputs a 3.3v power supply voltage, a 1.8v VTTREF voltage and a 1.8v VTT LDO voltage and outputs a 0.9v buffer reference voltage and a 0.9v feedback voltage.
As shown IN fig. 12, the MGT power supply adopts a TPS7a8400ARGRR chip, a voltage of 3.3v or 1.8v is input to an IN pin of the TPS7a8400ARGRR chip, a capacitor is connected to an FB pin and an OUT pin, a resistor is connected between the OUT pin and a PG pin, and output voltages of the PG pin are different, and the MGT power supply adopts three sets of circuits, namely, an input of 3.3v and an output of 1.0v, an input of 1.8v and an output of 1.0v, and an input of 3.3v and an output of 1.2 v.
Referring to the software functional part shown in fig. 2, the data acquisition and storage system works in the following manner: firstly, a system is powered on, a MicroBlaze (an embedded soft core, a RISC processor soft core embedded in an FPGA) is started, and GPS output time information is synchronized with an atomic clock; after the completion, the MicroBlaze starts to update operations such as FAT (table for recording the position of a file), directory entry, file name creation and the like, and then informs a state machine, the state machine controls a digital signal output by the A/D to be cached in an A/D FIFO module, when the A/D FIFO is full of storage, an FSM (finite state machine) state machine gives an instruction, and the SATA IP core extracts data in the A/D FIFO to a data port of the SATA IP core and then stores the data in an appointed sector of the SATA hard disk; when data needs to be called, firstly, MicroBlaze sends a data calling instruction, then receives a data address and size and transmits the information to an FSM state machine of the system, the FSM state machine controls an SATA IP core, data of an appointed sector address of an SATA hard disk is uploaded to a dual-port RAM through a SATA IP core data port, then MicroBlaze modifies the data in the dual-port RAM and transmits the modified data back to an appointed sector of the SATA hard disk, and finally, the computer can be connected through an interface, and software is used for checking data of FAT file types.
Finally, it should be noted that: although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that: modifications and equivalents may be made thereto without departing from the spirit and scope of the invention, and the appended claims are intended to cover such modifications and equivalents as fall within the true spirit and scope of the invention.

Claims (10)

1. The utility model provides an underwater sound data storage device based on FPGA which characterized in that: the method comprises the following steps: the system comprises an FPGA, an acquisition module, a clock module, a configuration circuit module, an SRAM static storage module, an SATA storage module and a power module, wherein the power module provides reliable power for the working modules; the acquisition module is used for acquiring underwater acoustic data, and transmitting the underwater acoustic data to the FPGA after analog-to-digital conversion; the clock module comprises an on-chip clock and an off-chip clock, and the off-chip clock is connected with the FPGA; the configuration circuit module is in communication connection with the FPGA, the FPGA generates and outputs a clock signal to the configuration circuit, and the configuration circuit decompresses the PROM data file output by the FPGA at the working clock frequency; the SRAM static storage module is in communication connection with the FPGA; the SATA storage module is connected with the FPGA and provides multi-path data read-write transmission.
2. The FPGA-based underwater acoustic data storage device of claim 1, wherein: the acquisition module adopts an AD7608 chip, is powered by a 5v single power supply and is internally provided with a sampling amplifier and a digital filter; the FPGA employs XC5VFX 30T.
3. The FPGA-based underwater acoustic data storage device of claim 1, wherein: the FPGA is connected with a 5v working voltage, and the FPGA generates a logic clock signal through an internal DCM and a PLL.
4. The FPGA-based underwater acoustic data storage device of claim 1, wherein: the off-chip clock includes: the SATA storage module clock circuit comprises a reference clock generating circuit and a SATA storage module clock circuit, wherein the reference clock generating circuit adopts an IDT5V9885 programmable clock generator, the IDT5V9885 comprises two input clocks CLKIN and XTALIN/REFIN, wherein CLKIN is grounded, the IDT5V9885 is programmed through a JTAG interface chip, the IDT5V9885 has 6 output paths, 4 output paths are connected with an FPGA, 1 output path outputs a differential driving clock signal to an Ethernet controller, and 1 output path of the 4 output paths connected with the FPGA provides a differential working clock signal; the clock circuit of the SATA storage module adopts an ICS844071 chip, and the ICS844071 chip outputs a differential clock signal to the STAT storage module.
5. The FPGA-based underwater acoustic data storage device of claim 2, wherein: the configuration circuit module adopts an XCF32P chip as a hardware core configuration main control chip, the VCCINT of the XCF32P chip is connected with a 1.8v internal power supply and is connected with a 3.3v power supply voltage, a CLK pin is connected with FPGA clock pulse signal output, and a D0 pin is connected with the FPGA.
6. The FPGA-based underwater acoustic data storage device of claim 1, wherein: the SRAM static storage module adopts an IS61NLP204836B storage chip and IS connected with 3.3v power voltage, the SATA storage module adopts two MOLEX connectors and utilizes the SATA storage module to carry out data transmission with the solid state disk.
7. The FPGA-based underwater acoustic data storage device of claim 1, wherein: the power supply module comprises a low-dropout linear voltage stabilizing circuit, a switch type voltage stabilizing circuit and an MGT power supply, wherein the switch type voltage stabilizing circuit inputs an external direct-current power supply and converts the external direct-current power supply into a direct-current power supply in a voltage reduction manner; the low-voltage-difference linear voltage stabilizing circuit is connected with 3.3V of input voltage and outputs 0.9V and 2.5V of voltage; the MGT power supply is connected with the output voltage of the switch type voltage stabilizing circuit, and the MGT power supply outputs 1.0v and 1.2v voltages and is used for supplying power to the I/O interface.
8. The FPGA-based underwater acoustic data storage device of claim 7, wherein: the switch type voltage stabilizing circuit is provided with a plurality of groups, the switch type voltage stabilizing circuit adopts a PTH08T240 chip, a VIN pin of the PTH08T240 chip is connected with an external direct-current power supply, a VOUT pin of the PTH08T240 chip is connected with an SNSP pin, a resistor is connected between the SNSP pin and a TT pin, and direct-current voltage after voltage reduction is output between the SNSP pin and the SNSN pin; and the output voltage of the PTH08T240 chip is different due to the difference in resistance between the SNSP pin and the TT pin.
9. The FPGA-based underwater acoustic data storage device of claim 7, wherein: the low-dropout linear voltage stabilizing circuit is provided with a plurality of groups, the low-dropout linear voltage stabilizing circuit adopts TPS7A8400ARGRR chips and TPS51206DSQR chips, the BIAS pin of the TPS7A8400ARGRR chip is connected with 3.3v voltage, the FB pin and the OUT pin of the TPS7A8400ARGRR chip are connected with capacitors, resistors are connected between the OUT pin and the PG pin, the resistors are different, and the output voltages of the PG pin are different; the TPS51206DSQR chip inputs a 3.3v power supply voltage, a 1.8v VTTREF voltage and a 1.8v VTT LDO voltage and outputs a 0.9v buffer reference voltage and a 0.9v feedback voltage.
10. The FPGA-based underwater acoustic data storage device of claim 7, wherein: the MGT power supply adopts a TPS7A8400ARGRR chip, 3.3v or 1.8v voltage is input into an IN pin of the TPS7A8400ARGRR chip, a FB pin and an OUT pin are connected with a capacitor, a resistor is connected between the OUT pin and a PG pin, the resistor is different, and the PG pin has different output voltages.
CN202011377247.7A 2020-11-30 2020-11-30 Underwater acoustic data storage device based on FPGA Pending CN112558864A (en)

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