CN109343109B - Embedded dominant second-order pole type seismic data collector - Google Patents
Embedded dominant second-order pole type seismic data collector Download PDFInfo
- Publication number
- CN109343109B CN109343109B CN201811428468.5A CN201811428468A CN109343109B CN 109343109 B CN109343109 B CN 109343109B CN 201811428468 A CN201811428468 A CN 201811428468A CN 109343109 B CN109343109 B CN 109343109B
- Authority
- CN
- China
- Prior art keywords
- digital
- electrically connected
- digital signal
- dominant
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012545 processing Methods 0.000 claims abstract description 29
- 239000013078 crystal Substances 0.000 claims abstract description 21
- 238000001514 detection method Methods 0.000 claims description 20
- 230000006870 function Effects 0.000 claims description 9
- 238000001914 filtration Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 5
- 238000000605 extraction Methods 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 3
- 238000012546 transfer Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000007613 environmental effect Effects 0.000 description 5
- 238000006073 displacement reaction Methods 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 238000013480 data collection Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01V—GEOPHYSICS; GRAVITATIONAL MEASUREMENTS; DETECTING MASSES OR OBJECTS; TAGS
- G01V1/00—Seismology; Seismic or acoustic prospecting or detecting
- G01V1/24—Recording seismic data
- G01V1/247—Digital recording of seismic data, e.g. in acquisition units or nodes
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/38—Determining a navigation solution using signals transmitted by a satellite radio beacon positioning system
- G01S19/39—Determining a navigation solution using signals transmitted by a satellite radio beacon positioning system the satellite radio beacon positioning system transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/42—Determining position
Abstract
The invention relates to the technical field of seismic data receiving and recording devices, provides an embedded dominant second-order pole type seismic data collector, and aims to solve the problem of low seismic observation precision in the prior art. The seismic data collector comprises an analog input channel, a digital filter chip, a first-order high-pass filter, a digital signal processing module, a data output port, a GPS module, a digital control crystal oscillator circuit, a calibration signal output circuit and a system power module. The analog input channel, the digital filter chip, the first-order high-pass filter, the data output port, the GPS module and the digital control crystal oscillator circuit are electrically connected with the digital signal processing module; and the input end of the calibration signal output circuit is electrically connected with the digital signal processing module, and the output end of the calibration signal output circuit is electrically connected with the seismometer. The invention can obtain the dominant second-order pole by using the digital filter chip, and the earthquake observation precision is higher.
Description
Technical Field
The invention relates to the technical field of seismic data receiving and recording devices, in particular to an embedded dominant second-order pole type seismic data collector.
Background
The earthquake data acquisition system mainly comprises two parts, namely an earthquake meter and an earthquake data acquisition device, wherein the earthquake meter is used for picking up mechanical vibration signals and converting the mechanical vibration signals into analog electric signals; the seismic data collector is used for receiving the analog electric signals, converting the analog electric signals into digital electric signals, and outputting or transmitting the digital electric signals in the form of waveform data after filtering. The application with publication number of CN107247288A discloses a seismic observation system and a method for generating a seismic transfer function, the background section of the application introduces that the transfer function of the existing seismic data acquisition system is mainly synthesized by the transfer functions of a seismometer and a seismic data acquisition device, and a 'dominant second-order pole' in the transfer function is jointly generated by an analog element and mechanical swing in the seismometer, so that high precision and high stability of the existing seismic data acquisition system are difficult to ensure in a large temperature range and in long-term continuous operation, and the observation precision of the existing seismic data acquisition system is low.
Disclosure of Invention
In view of the above, the present invention aims to provide an embedded dominant second-order pole type seismic data collector, which aims to solve the problem of low seismic observation precision of the existing seismic data collection system.
In order to achieve the above object, the present invention provides the following technical solutions:
an embedded dominant second order pole type seismic data collector comprising:
the analog quantity input channel is used for inputting analog electric signals and converting the analog electric signals into digital electric signals;
the digital filter chip is used for carrying out three-section digital decimation filtering on the digital electric signal;
the first-order high-pass filter is used for removing zero offset from the digital electric signal subjected to three-section digital extraction and filtration to obtain seismic waveform data;
a digital signal processing module for performing a driving function;
a data output port for packaging the seismic waveform data for output;
the GPS module is used for providing time service signals and positioning information;
a digital control crystal oscillator circuit;
a calibration signal output circuit; the method comprises the steps of,
a system power module for providing electrical energy;
the analog input channel, the digital filter chip, the first-order high-pass filter, the data output port, the GPS module and the digital control crystal oscillator circuit are electrically connected with the digital signal processing module; and the input end of the calibration signal output circuit is electrically connected with the digital signal processing module, and the output end of the calibration signal output circuit is electrically connected with the seismometer.
In the technical scheme, firstly, an analog electric signal formed by detection can be input into the embedded dominant second-order pole type seismic data collector through an analog input channel, and meanwhile, the analog input channel is converted into a digital electric signal; then the digital electric signal can be filtered by a digital filter chip and obtain a dominant second-order pole so as to synthesize a transfer function; then the digital electric signal is subjected to zero displacement removal through a first-order high-pass filter, so that the precision is improved, and seismic waveform data are obtained; and finally outputting the seismic waveform data through a data output port. In the period, the digital signal processing module is used as a main control chip to play a driving role; the GPS module provides high-precision time service signals and positioning information, so that the embedded dominant second-order pole type seismic data collector and other equipment in the network keep the consistency of time; the calibration signal output circuit may provide a current input of square wave and sine wave set calibration signals to the seismometer. The dominant second-order pole embedded seismic data collector provided by the invention can obtain the dominant second-order pole by utilizing the digital filter chip, and has the advantages of less influence on the precision by environmental factors and time lapse and higher seismic observation precision.
As the optimization of the technical scheme, the embedded dominant second-order pole type seismic data collector further comprises a temperature and voltage detection module, and the temperature and voltage detection module is electrically connected with the digital signal processing module. In the preferred technical scheme, the temperature and voltage detection module can monitor variables such as input power supply voltage, working state of the GPS module, time difference between the current GPS module and the digital control crystal oscillator circuit, temperature inside the case and the like. These environmental variables can be transmitted out with the data stream at regular time, enabling the user to track the operating state of the harvester at any time.
As a preferable aspect of the foregoing technical solution, the digital signal processing module includes:
a digital signal processor DSP;
a programmable logic device PLD;
a flash memory module; the method comprises the steps of,
a universal asynchronous receiver transmitter UART;
the programmable logic device PLD, the flash memory module and the universal asynchronous receiver transmitter UART are connected with the digital signal processor DSP through parallel bus interfaces, and the flash memory module and the universal asynchronous receiver transmitter UART are also electrically connected with the programmable logic device PLD;
the GPS module is electrically connected with the UART; the input end of the digital control crystal oscillator circuit is electrically connected with the digital signal processor DSP, and the output end of the digital control crystal oscillator circuit is electrically connected with the programmable logic device PLD; the input end of the calibration signal output circuit is electrically connected with the digital signal processor DSP; the temperature and voltage detection module is electrically connected with the digital signal processor DSP.
In the preferred technical scheme, a programmable logic device PLD, a flash memory module, a universal asynchronous receiver transmitter UART and the like are used as expansion modules of the digital signal processor DSP and used for enriching interfaces of the digital signal processor DSP and expanding storage space of the digital signal processor DSP. The programmable logic device PLD is also used for converting control signals of the DSP into control signals matched with other expansion modules.
As a preferable mode of the above technical solution, the digital signal processing module further includes a random access memory RAM, and the random access memory RAM is electrically connected with the programmable logic device PLD. The beneficial effect of the preferred technical proposal is that the storage space of the DSP is further expanded through the RAM.
As the optimization of the technical scheme, the embedded dominant second-order pole type seismic data collector further comprises a DOC data cache module, and the DOC data cache module is electrically connected with the digital signal processing module.
As a preferable mode of the above technical solution, the digital filter chip is a CS 5376A-type filter chip.
As the preferable choice of the technical scheme, the DSP is a TMS320VC5416 chip.
As a preferable mode of the above technical solution, the programmable logic device PLD is an XC2C 384-type chip; the UART is an SC16C554 chip.
As the optimization of the technical scheme, the temperature and voltage detection module comprises a voltage division circuit and a MAX1299 chip, wherein the voltage division circuit is electrically connected with the MAX1299 chip, the voltage division circuit is electrically connected with the system power supply module, and the MAX1299 chip is electrically connected with the digital signal processor DSP.
As a preferable mode of the above technical solution, the analog input channel includes three analog input sub-channels, each analog input sub-channel includes an input amplifier and a 24-bit analog-to-digital converter electrically connected to each other, wherein the input amplifier is electrically connected to the seismometer, and the 24-bit analog-to-digital converter is electrically connected to the digital filter chip.
Compared with the prior art, the invention has the beneficial effects that:
the analog input channel inputs an analog electric signal formed by seismometer detection into the embedded dominant second-order pole type seismic data collector, and simultaneously converts the analog input channel into a digital electric signal; then the digital electric signal can be filtered by a digital filter chip and obtain a dominant second-order pole so as to synthesize a transfer function; then the digital electric signal is subjected to zero displacement removal through a first-order high-pass filter, so that the precision is improved, and seismic waveform data are obtained; and finally outputting the seismic waveform data through a data output port. In the period, the digital signal processing module is used as a main control chip to play a driving role; the GPS module provides high-precision time service signals and positioning information, so that the embedded dominant second-order pole type seismic data collector and other equipment in the network keep the consistency of time; the calibration signal output circuit may provide a current input of square wave and sine wave set calibration signals to the seismometer. The seismic data collector embedded with the dominant second-order pole can be obtained by utilizing the digital filter chip, so that the precision of the dominant second-order pole is less influenced by environmental factors and time lapse, and the seismic observation precision is higher.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram illustrating a structure of an embedded dominant second order pole type seismic data collector according to an embodiment.
Fig. 2 is a schematic circuit diagram of a digitally controlled crystal oscillator circuit according to an embodiment.
Fig. 3 is a schematic circuit diagram of the calibration signal output circuit according to the embodiment.
Fig. 4 is a schematic circuit diagram of the temperature and voltage detection module according to the embodiment.
Fig. 5 is a schematic circuit diagram of a system power module according to an embodiment.
FIG. 6 is a flow chart of signals embedded in a dominant second order pole type seismic data collector, as provided by an embodiment.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without creative efforts, are included in the protection scope of the present invention based on the embodiments of the present invention.
Referring to fig. 1, the embodiment provides an embedded dominant second-order pole type seismic data collector, which mainly includes an analog input channel, a digital filter chip, a first-order high-pass filter, a digital signal processing module, a data output port, a GPS module, a digital control crystal oscillator circuit, a calibration signal output circuit and a system power module.
The analog input channel, the digital filter chip, the first-order high-pass filter, the data output port, the GPS module and the digital control crystal oscillator circuit are electrically connected with the digital signal processing module; and the input end of the calibration signal output circuit is electrically connected with the digital signal processing module, and the output end of the calibration signal output circuit is electrically connected with the seismometer.
The analog input channel is used for inputting analog electric signals and converting the analog electric signals into digital electric signals; the digital filter chip is used for carrying out three-section digital decimation filtering on the digital electric signal; the first-order high-pass filter is used for removing zero offset of the digital electric signal subjected to three-section digital extraction and filtration so as to obtain seismic waveform data; the digital signal processing module is used as a main control chip to play a driving role; the data output port is used for packaging and outputting the seismic waveform data to the acquisition card; the GPS module is used for providing time service signals and positioning information; the calibration signal output circuit may provide a current input of square wave and sine wave set calibration signals to the seismometer.
When in use, referring to fig. 6, the seismometer can input the analog electric signal formed by detection into the embedded dominant second-order pole type seismic data collector through the analog input channel, and simultaneously convert the analog input channel into a digital electric signal; then the digital electric signal can be filtered by a digital filter chip and obtain a dominant second-order pole so as to synthesize a transfer function; then the digital electric signal is subjected to zero displacement removal through a first-order high-pass filter, so that the precision is improved, and seismic waveform data are obtained; and finally outputting the seismic waveform data through a data output port. In the period, the digital signal processing module is used as a main control chip to play a driving role; the GPS module provides high-precision time service signals and positioning information, so that the embedded dominant second-order pole type seismic data collector and other equipment in the network keep the consistency of time; the calibration signal output circuit may provide a current input of square wave and sine wave set calibration signals to the seismometer. Because the dominant second-order pole embedded type seismic data collector provided by the embodiment can obtain the dominant second-order pole by utilizing the digital filter chip, the accuracy is less influenced by environmental factors and time lapse, and the seismic observation accuracy is higher.
Referring to fig. 1, in this embodiment, the embedded dominant second-order pole type seismic data collector may further include a temperature and voltage detection module, where the temperature and voltage detection module is electrically connected to the digital signal processing module. The temperature and voltage detection module can monitor variables such as input power supply voltage, working state of the GPS module, time difference between the current GPS module and the digital control crystal oscillator circuit, temperature in the case and the like. These environmental variables can be transmitted out with the data stream at regular time, enabling the user to track the operating state of the harvester at any time.
Referring to fig. 1, in this embodiment, the embedded dominant second order pole type seismic data collector may further include a DOC data buffer module, where the DOC data buffer module is electrically connected to the digital signal processing module.
Referring to fig. 1, in this embodiment, the analog input channel includes three analog input sub-channels, each of which includes an input amplifier and a 24-bit analog-to-digital converter electrically connected to each other, wherein the input amplifier is electrically connected to the seismometer, and the 24-bit analog-to-digital converter is electrically connected to the digital filter chip. The three analog input sub-channels are one seismometer UD direction detection data, seismometer EW direction detection data, and seismometer NS direction detection data, respectively.
Based on the above-described embedded dominant second order pole-type seismic data collector, the present embodiment provides examples of the following specific embodiments.
Referring to fig. 1, the digital signal processing module may specifically include a digital signal processor DSP, a programmable logic device PLD, a FLASH memory module FLASH, and a universal asynchronous receiver transmitter UART; the programmable logic device PLD, the flash memory module and the universal asynchronous receiver transmitter UART are connected with the digital signal processor DSP through parallel bus interfaces, and the flash memory module and the universal asynchronous receiver transmitter UART are also electrically connected with the programmable logic device PLD. Specifically, the programmable logic device PLD, the flash memory module and the universal asynchronous receiver transmitter UART are used as parallel expansion peripherals of the digital signal processor DSP. The internal memory space of the digital signal processor DSP is divided into three parts, namely a data space, a program space and an I/O space, wherein the program space is controlled by a PS, MSTRB, RW signal, the data space is controlled by a DS, MSTRB, RW signal, the I/O space is controlled by a IS, IOSTRB, RW signal, all the modules are connected through parallel bus interfaces, a programmable logic device PLD and a universal asynchronous receiver transmitter UART are mapped to the external I/O space of the digital signal processor DSP, and the FLASH is simultaneously mapped to the program space and the data space of the digital signal processor DSP. Among them, the programmable logic device PLD mainly plays the following roles: because the control pins of the DSP are not matched with other expansion peripherals, one of the roles of the PLD is to convert the control signals of the DSP into control signals that match other expansion modules.
The GPS module is electrically connected with the UART; the input end of the digital control crystal oscillator circuit is electrically connected with the digital signal processor DSP, and the output end of the digital control crystal oscillator circuit is electrically connected with the programmable logic device PLD; the input end of the calibration signal output circuit is electrically connected with the digital signal processor DSP; the temperature and voltage detection module is electrically connected with the digital signal processor DSP.
In addition, the digital signal processing module may further include a random access memory RAM, where the random access memory RAM is electrically connected to the programmable logic device PLD, and further expands a storage space of the DSP.
Based on the above-mentioned hardware modules embedded with the dominant second-order pole type seismic data collector, the present embodiment provides examples of specific models of the hardware modules.
For example, three analog input sub-channels all adopt a balanced differential input mode, so that the common-mode interference resistance of data acquisition is improved. And switching two full-scale input gears of +/-20V and +/-10V of the external seismometer by adopting a differential input differential output high-precision operational amplifier with programmable gain at an input end. Each 24-bit analog-to-digital converter may optionally use a separate 4-order sigma delta modulator CS5371.
For example, the digital filter chip is a CS5376A type filter chip. The CS5376A type filter chip extracts and filters the 512KSPS oversampling code stream converted by the 24-bit analog-to-digital converter into 24-bit seismic data, the CS5376A type filter chip is a four-channel signal processing filter, the output sampling rate is 4000 SPS-1 SPS, and the passband range is 1600 Hz-400 MHz. After 512K bit stream enters CS5376A filter chip, the three sections of filters can be used for filtering the seismic signals, and the three sections of filters are respectively: three-stage comb filter (abbreviated as SINC), two-stage finite impulse response filter (abbreviated as FIR) and two-stage infinite impulse response filter (abbreviated as IIR). Wherein the infinite impulse response filter generates a dominant second order pole of the seismic survey. Considering that the CS 5376A-type filter chip is a commercially available chip, the description of this embodiment is omitted.
For example, the first-order high-pass filter may be implemented by a circuit, and considering that the circuit of the first-order high-pass filter is an existing circuit structure, the embodiment is not described in detail, and reference may be made to a circuit diagram in the text of "first-order high-pass filter" in a hundred-degree library, where the website is https:// wenku.
For example, the DSP is a TMS320VC5416 type chip. The maximum clock frequency of the chip is 160MHz, and in order to reduce power consumption, the clock of the chip in the current system is 100MHz. TMS320VC5416 provides rich peripherals such as a 16-BIT counter, three MCBSP serial ports, an HPI host interface, and an external bus interface with 128K x 16BIT RAM inside the chip. The core voltage of the chip was 1.6V and the I/O voltage was 3.3V. Under typical test conditions, the nuclear current is 60mA and the I/O current is 40mA. Three external interfaces of the DSP are mainly used in the system, namely a parallel bus interface, a serial interface and GPIO.
For example, the programmable logic device PLD is an XC2C384 chip, the UART is an SC16C554 chip, and the RAM is 62WV 25616.
For example, the data output port is specifically an RS-232 serial interface, and is used for connecting with a computer.
For example, the GPS module may be an M12ONECORE of motorola, and the data interface of the GPS module is a UART interface, where the baud rate is fixed to 9600BPS. In the earthquake data collector, a UART interface of a GPS module is connected with a UART expansion chip SC16C554 of a universal asynchronous receiving and transmitting transmitter, and a digital signal processor DSP controls the GPS module by reading and writing the UART expansion chip of the universal asynchronous receiving and transmitting transmitter.
For example, referring to fig. 2, the digitally controlled crystal oscillator circuit may specifically include a DAC8512 type digital-to-analog converter and a voltage controlled crystal oscillator VCXO electrically connected to each other, where the DAC8512 type digital-to-analog converter is electrically connected to the digital signal processor DSP through the interface shown in fig. 2, and the voltage controlled crystal oscillator VCXO is electrically connected to the programmable logic device PLD.
For example, referring to FIG. 3, the calibration signal is generated by a 16-bit DAC5061 type digital-to-analog converter from ADI. The reference source of DAC5061 is +2.5v, and is generated by external reference source chip LT1019, as shown in fig. 5, the voltage output is converted from unipolar voltage output to bipolar voltage output by an arithmetic circuit. The bipolar voltage is passed through a constant current source circuit to convert the voltage output signal into a current output signal, and is input to the seismometer.
For example, referring to fig. 4, the temperature and voltage detection module includes a voltage division circuit and a MAX1299 chip, the voltage division circuit is electrically connected to the system power module, and the MAX1299 chip is electrically connected to the digital signal processor DSP.
For example, referring to fig. 5, after 9-15V power is input, the digital power provided by the system power module finally includes: +3.3V DSP and PLD I/O port power supply, +1.6V DSP core power supply, +1.8V PLD core power supply, +3V GPS module power supply, +3.3V calibration signal output circuit digital power supply, +5V relay power supply, +5V voltage controlled crystal oscillator VCXO power supply, +12V sensor power supply and +3.3V acquisition card digital power supply; the analog power supply provided by the system power supply module comprises: +2.5V DAC5061 reference power supply, +12V collection card operational amplifier positive power supply, -12V collection card operational amplifier negative power supply, +12V calibration operational amplifier positive power supply and-12V calibration operational amplifier negative power supply.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that changes and substitutions are within the scope of the present invention.
Claims (7)
1. An embedded dominant second order pole type seismic data collector comprising:
the analog quantity input channel is used for inputting analog electric signals and converting the analog electric signals into digital electric signals;
the digital filter chip is used for carrying out three-section digital decimation filtering on the digital electric signal;
the first-order high-pass filter is used for removing zero offset from the digital electric signal subjected to three-section digital extraction and filtration to obtain seismic waveform data;
a digital signal processing module for performing a driving function;
a data output port for packaging the seismic waveform data for output;
the GPS module is used for providing time service signals and positioning information;
a digital control crystal oscillator circuit;
a calibration signal output circuit; the method comprises the steps of,
a system power module for providing electrical energy;
the analog input channel, the digital filter chip, the first-order high-pass filter, the data output port, the GPS module and the digital control crystal oscillator circuit are electrically connected with the digital signal processing module; the input end of the calibration signal output circuit is electrically connected with the digital signal processing module, and the output end of the calibration signal output circuit is electrically connected with the seismometer;
the temperature and voltage detection module is electrically connected with the digital signal processing module;
the digital signal processing module includes:
a digital signal processor DSP;
a programmable logic device PLD;
a flash memory module; the method comprises the steps of,
a universal asynchronous receiver transmitter UART;
the programmable logic device PLD, the flash memory module and the universal asynchronous receiver transmitter UART are connected with the digital signal processor DSP through parallel bus interfaces, and the flash memory module and the universal asynchronous receiver transmitter UART are also electrically connected with the programmable logic device PLD;
the GPS module is electrically connected with the UART; the input end of the digital control crystal oscillator circuit is electrically connected with the digital signal processor DSP, and the output end of the digital control crystal oscillator circuit is electrically connected with the programmable logic device PLD; the input end of the calibration signal output circuit is electrically connected with the digital signal processor DSP; the temperature and voltage detection module is electrically connected with the digital signal processor DSP;
the analog input channel comprises three analog input sub-channels, each analog input sub-channel comprises an input amplifier and a 24-bit analog-to-digital converter which are electrically connected with each other, wherein the input amplifier is used for being electrically connected with the seismometer, and the 24-bit analog-to-digital converter is electrically connected with the digital filter chip.
2. The embedded dominant second order pole type seismic data collector of claim 1, wherein the digital signal processing module further comprises a random access memory RAM electrically connected to the programmable logic device PLD.
3. The embedded dominant second order pole type seismic data collector of claim 1, wherein the digital signal processor DSP is a TMS320VC5416 type chip.
4. The embedded dominant second order pole type seismic data collector of claim 1, wherein the programmable logic device PLD is an XC2C 384-type chip; the UART is an SC16C554 chip.
5. The embedded dominant second order pole type seismic data collector of claim 1, wherein the temperature and voltage detection module comprises a voltage divider circuit and a MAX1299 chip, the voltage divider circuit is electrically connected to the system power module, and the MAX1299 chip is electrically connected to the digital signal processor DSP.
6. The embedded dominant second order pole type seismic data collector of claim 1, further comprising a DOC data caching module electrically connected to the digital signal processing module.
7. The embedded dominant second order pole type seismic data collector of claim 1, wherein the digital filter chip is a CS5376A type filter chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811428468.5A CN109343109B (en) | 2018-11-27 | 2018-11-27 | Embedded dominant second-order pole type seismic data collector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811428468.5A CN109343109B (en) | 2018-11-27 | 2018-11-27 | Embedded dominant second-order pole type seismic data collector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109343109A CN109343109A (en) | 2019-02-15 |
| CN109343109B true CN109343109B (en) | 2024-03-08 |
Family
ID=65318186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811428468.5A Active CN109343109B (en) | 2018-11-27 | 2018-11-27 | Embedded dominant second-order pole type seismic data collector |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109343109B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000038288A (en) * | 1998-12-05 | 2000-07-05 | 이종훈 | Earthquake monitoring system |
| CN1664615A (en) * | 2005-04-19 | 2005-09-07 | 中国科学技术大学 | Earthquake data acquisition board for geophysical exploration |
| CN203870267U (en) * | 2014-05-29 | 2014-10-08 | 中国地震局地震预测研究所 | Large-dynamic high-precision seismic data collector based on delta-sigma modulation |
| CN107247288A (en) * | 2017-07-26 | 2017-10-13 | 四川省地震局 | A kind of seismic observation system and the method for generating earthquake transmission function |
| CN108008359A (en) * | 2017-11-08 | 2018-05-08 | 武汉滨湖电子有限责任公司 | A kind of cascade digital based on pattern-band radio frequency sampling filters anti-Communication Jamming method |
| CN208937712U (en) * | 2018-11-27 | 2019-06-04 | 四川省地震局水库地震研究所 | It is embedded in leading second order pole type seismic data collector |
-
2018
- 2018-11-27 CN CN201811428468.5A patent/CN109343109B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000038288A (en) * | 1998-12-05 | 2000-07-05 | 이종훈 | Earthquake monitoring system |
| CN1664615A (en) * | 2005-04-19 | 2005-09-07 | 中国科学技术大学 | Earthquake data acquisition board for geophysical exploration |
| CN203870267U (en) * | 2014-05-29 | 2014-10-08 | 中国地震局地震预测研究所 | Large-dynamic high-precision seismic data collector based on delta-sigma modulation |
| CN107247288A (en) * | 2017-07-26 | 2017-10-13 | 四川省地震局 | A kind of seismic observation system and the method for generating earthquake transmission function |
| CN108008359A (en) * | 2017-11-08 | 2018-05-08 | 武汉滨湖电子有限责任公司 | A kind of cascade digital based on pattern-band radio frequency sampling filters anti-Communication Jamming method |
| CN208937712U (en) * | 2018-11-27 | 2019-06-04 | 四川省地震局水库地震研究所 | It is embedded in leading second order pole type seismic data collector |
Non-Patent Citations (2)
| Title |
|---|
| DSP控制数据采集仪系统设计;李忠勤, 王欢, 胡丹;煤炭技术(11);第29-30页 * |
| 一种高精度地震数据采集单元的系统设计与实现;王京京;罗维炳;李宁;徐善辉;蒋冬伟;张学彬;;地球物理学进展(04);第1828-1837页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109343109A (en) | 2019-02-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203520081U (en) | Time-based synchronous multichannel data acquisition instrument | |
| CN204425298U (en) | A kind of faint AC signal amplitude lock-in amplifier | |
| CN103257271A (en) | Device and method for detecting micro grid harmonic wave and inter-harmonics based on STM32F107VCT6 | |
| CN103488112A (en) | Multichannel data acquisition instrument based on time synchronization | |
| CN201845051U (en) | Three-phase intelligent electric energy meter | |
| CN106289256A (en) | Signal calculated processing system based on two CSTR Yu FPGA architecture | |
| CN109510625A (en) | A kind of high-precision AD sampling of quartz flexible accelerometer and conversion circuit | |
| CN103033675A (en) | Alternating current synchronous collecting system and achieving method thereof | |
| CN104237905A (en) | Big Dipper detector | |
| CN106230481A (en) | A kind of power line interference signal extraction and synchronous playback means | |
| CN209543097U (en) | Data collection system | |
| CN109343109B (en) | Embedded dominant second-order pole type seismic data collector | |
| CN110908321A (en) | Data acquisition device for steam turbine set sensor | |
| CN205333219U (en) | Multichannel temperature measuring circuit based on quartz crystal temperature sensor | |
| CN208937712U (en) | It is embedded in leading second order pole type seismic data collector | |
| CN107490719A (en) | Electronic mutual inductor based on Rogowski coil principle in GIS | |
| CN207816478U (en) | Temperature measurement circuit | |
| Fertitta et al. | A low power and high resolution data logger for submarine seismic monitoring | |
| CN201804035U (en) | Dynamic monitoring storage oscilloscope | |
| CN104101900A (en) | Field discrete type seismic digital recording instrument | |
| CN112014636A (en) | Radio frequency module test system based on high-speed AD | |
| CN207036332U (en) | A kind of signal processing system of high pressure flow auto-controlling apparatus | |
| CN202435412U (en) | Noise signal imitation system for low-voltage power line carrier test | |
| CN102420664A (en) | Simulation system of noise signal for carrier test of low-voltage power line | |
| CN202066973U (en) | High resolution petroleum and seismic exploration instrument power supply circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |