CN201327635Y

CN201327635Y - High-speed data acquisition unit

Info

Publication number: CN201327635Y
Application number: CNU2008201636692U
Authority: CN
Inventors: 万旭; 沈亚强; 王宇; 彭保进; 金洪震; 钱惠国
Original assignee: Zhejiang Normal University CJNU
Current assignee: Zhejiang Normal University CJNU
Priority date: 2008-09-04
Filing date: 2008-09-04
Publication date: 2009-10-14
Anticipated expiration: 2018-09-04

Abstract

The utility model relates to a high- speed data acquisition unit, which takes a CPLD as a center and mainly comprises a plurality of parts such as a data acquisition circuit, a data processing, data storage, a power module and the like. The utility model is formed by sequentially connecting an input port, an adjustable amplification circuit, a high-speed A/D chip, a CPLD chip and an output port. Further, the CPLD chip utilizes VHDL language, and functional modules realized by the CPLD chip primarily include a jitter-eliminating module, a control module and an FIFO memory module. Besides, the CPLD chip is specifically composed of four parts including amplitude determination, FIFO storage, clock generation and timing generation. By utilizing the high speed CPLD chip with a plurality of I/O ports to control an ADC and a RAM and the like, the utility model, which resolves the problem of timing synchronization when sampling speed is too high, has the advantages of easy modification and optimization of design, fine system applicability, simple circuit, small volume and the like.

Description

High speed data acquisition system

Technical field

The utility model relates to the high speed data acquisition system of high-frequency data detection system, especially based on CPLD (CPLD), adopts the high speed data acquisition system of VHDL (high-speed hardware descriptive language) hardware description language design.

Background technology

Traditional high speed data acquisition system adopts single-chip microcomputer or DSP as the major control module usually, the work of control ADC, storer and other peripheral circuits.Along with data acquisition is more and more higher to the requirement of speed ability, the drawback of traditional acquisition system is just more and more obvious.The clock frequency of single-chip microcomputer is lower and need realize data acquisition with software, and this makes picking rate and efficient reduce, and the running software time also accounts for very big ratio in the whole sampling time in addition.And CPLD (CPLD) has the incomparable advantage of single-chip microcomputer.CPLD clock frequency height, internal delay time is little, and all steering logic is finished by hardware, and speed is fast, efficient is high.On this technical foundation, satisfied the requirement of data acquisition to speed.Can be applicable to fields such as radar, sonar, Flame Image Process, speech recognition, communication, transient signal test.

The utility model content

Usually the normal MCU (microprocessor) that uses controls in the low speed high speed data acquisition system, but in high-speed data acquistion system, tend to be subjected to the influence of the running software speed of MCU, and along with the raising ADC of device speed, RAM, the sequential stationary problem between the MCU also can display.Therefore the utility model has used at a high speed, the CPLD chip of many I/O mouth controls ADC and RAM etc., thereby well solved the synchronous problem of sequential when sample rate is too high.

The technical scheme that its technical matters that solves the utility model adopts is: be the center with CPLD, mainly comprise several parts such as data acquisition circuit, data processing, data storage, power module.

High speed data acquisition system mainly is made of the CPLD chip of a slice high-speed AD chip and a slice Altera.The inner functional module that realizes of CPLD mainly contains:

(1) disappears and tremble module.Finishing software to the mode of operation control signal disappears and trembles.

(2) control module.Receive the beginning sampled signal START that the drainage pattern switch sends, realize control, beginning AD conversion ADC; Being responsible for the logic control of each several part and the auspicious processing module of volume of AD sampled data, is the core of high speed data acquisition system.

(3) FIFO memory module, and can send half-full and spacing wave.When half-full, send a HalfFlag signal, the notice associated components can reading, when the FIFO storer be empty, sends an EmptyFlag signal, and prompting is correlated with and is stopped reading.

The function logic of CPLD uses VHDL language to realize that this is a kind of hardware description language, is mainly used in structure, behavior, function and the interface of describing digital display circuit.When using VHDL language design hardware circuit, can make the deviser exempt the work of writing logical expression or truth table.Make the difficulty of hardware circuit design that significantly reduction has been arranged like this, thereby can increase work efficiency, shorten the design cycle of hardware circuit.

The beneficial effects of the utility model are, have finished at a high speed, the CPLD design of multichannel data acquisition system (DAS), and this circuit has advantages such as circuit is simple, volume is little.Utilize eda tool and language to CPLD design, emulation and checking, the Products Development design cycle has been shortened in modification that this is convenient to design and optimization.The characteristics that had online programming by CPLD can be made amendment to the internal logic configuration of FPGA according to the concrete condition at scene, have further increased the dirigibility of system applies, and this design is a kind of more satisfactory hyperchannel, high-speed data acquisition scheme after tested.

Description of drawings

Fig. 1 is an external form synoptic diagram of the present utility model.

Fig. 2 is a schematic block circuit diagram of the present utility model.

Embodiment

The utility model is described in further detail below in conjunction with drawings and Examples.

As shown in fig. 1,1. be the start stop switch of data acquisition in the device of the present utility model; 2. be the power input of high speed data acquisition system; 3. be the simulating signal of input; 4. be the digital signal of output; 5. be data ready whether sign.

As shown in Figure 2, inside is to be the center with CPLD, mainly comprises several parts such as data acquisition circuit, data processing, data storage, power module.

Power module is for the power supply of this system the time, also provides+power supply of 9V for front end sensors.

Simulating signal among Fig. 2, is carried out AD (modulus) and is transformed through amplifying by the 3. port input of Fig. 1, becomes digital signal.Amplifying circuit adopts high-speed wideband operational amplifier LM318, and the enlargement factor of amplifier realizes that by negative feedback resistor this negative feedback resistor is the DS1804 that digital potentiometer uses Dallas company.The amplifier magnification ratio adjustment is finished automatically by the amplitude judge module.

High-speed A/D converter adopts the TLC1550 chip of TI company.It is the parallel AD chip of 8bit that a kind of CMOS of employing technology is made, and the high conversion rate that can provide is 20Msps.Because TLC1550 inside has sampling hold circuit and standard divider resistance, thereby has simplified the design of peripheral circuit greatly.The clock signal clk of TLC1550 is gathered analog input signal at each negative edge.After the delay of data that the N time is gathered, be sent on the internal data bus through 2.5 clock period.If this moment, output enable OE was effective, then data can be sent on the 8bit data bus (DB).

It is suitable that amplifier is adjusted, and after the AD conversion, the metadata cache that collects to FIFO, when storage reaches the remaining of user's setting, just sent a request signal (data ready), notice associated components reading of data.The big I of FIFO remaining value is set by user oneself, but this value can not be too near the degree of depth of FIFO.Because respond this request signal at fetch unit, carry out in the process of reading processing, CPLD is still in the collection of carrying out data and storage.If the remaining value is too near the FIFO degree of depth, FIFO is easy to generate the mistake of overflowing.Therefore, the design is half-full as the remaining of setting with fifo chip, and when storing the half that data reach its capacity, CPLD will send the signal of a requests data reading.The FIFO control signal has: asynchronous resetting; Read and write data; Read-write enables; Sky/half-full sign.Data (data) enable under the effective situation according to writing clock toward the storage of FIFO the inside writing, and when reading to enable, data are exported from data bus according to the speed of reading clock.4. the data of FIFO output to Fig. 1 among Fig. 2, and 5. the data ready of FIFO outputs to Fig. 1 among Fig. 2.

Finish above data acquisition and need following steps: the amplifier output amplitude is adjusted, the AD conversion, data are preserved (data are write), data read processes such as (data are read), these processes should be undertaken by certain sequential, and this sequential is by the time sequence status circuit control of CPLD.Being provided with the one of four states corresponding with above-mentioned steps altogether at this time sequence status is controlled respectively.

Clock generator among the CPLD produces time clock, the action of control AD conversion.

It in Fig. 2 frame of broken lines the inner modular circuit that needs design of CPLD.CPLD selects the EMP72128-6 chip for use, and gate delay is 6ns.

Claims

1, a kind of high speed data acquisition system, mainly comprise data acquisition circuit, data processing, data storage, power module etc., it is characterized in that: data processing and data storage add the realization of CPLD chip by the high-speed a/d chip, it comprises the input port that is connected successively, adjustable amplifying circuit, high-speed a/d chip, CPLD chip, output port, and data processing and data storage add the realization of CPLD chip by the high-speed a/d chip.

2, high speed data acquisition system as claimed in claim 1 is characterized in that: the inner functional module that realizes of CPLD mainly contains to disappear trembles module, control module, FIFO memory module.