CN108768394A - A kind of numerical model analysis micro-system ADC unit dynamic parameter testing systems - Google Patents
A kind of numerical model analysis micro-system ADC unit dynamic parameter testing systems Download PDFInfo
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- CN108768394A CN108768394A CN201711458673.1A CN201711458673A CN108768394A CN 108768394 A CN108768394 A CN 108768394A CN 201711458673 A CN201711458673 A CN 201711458673A CN 108768394 A CN108768394 A CN 108768394A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
- H03M1/1085—Measuring or testing using domain transforms, e.g. Fast Fourier Transform
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
- H03M1/1095—Measuring or testing for ac performance, i.e. dynamic testing
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Abstract
A kind of numerical model analysis micro-system ADC unit dynamic parameter testing systems, including host computer and test board；Host computer is responsible for test result and shows and store；Test board includes signal generating module, Signal-regulated kinase, clock generation module, micro-system ADC units and micro-system FPGA unit；Test board is responsible for generating micro-system ADC cell input signals and sampling clock, and completes the acquisition of ADC unit output datas, storage and processing, finally obtains the main dynamic performance parameter of micro-system ADC units.The present invention makes full use of the FPGA unit high-speed data processing capacity that micro-system is internally integrated; micro-system ADC unit sampling output datas are acquired, stored and handled by micro-system FPGA unit; the interference between the expense and signal of additional data transmissions is reduced, system can be mixed micro-system ADC unit dynamic parameters with logarithmic mode and carry out reliable accurately test.
Description
Technical field
The present invention relates to integrated circuit testing field, especially a kind of numerical model analysis micro-system ADC unit dynamic parameters are surveyed
Test system.
Background technology
As the miniaturization of weaponry, space system and aircraft, low-power consumption and highly reliable demand are increasingly strong, adopt
Be individually encapsulated with discrete circuit, then the framework interconnected into andante grade, cannot be satisfied aerospace system small size of new generation, high-precision,
High density, the demand of high reliability.The numerical model analysis micro-system of the functions such as integrated ADC, DAC and FPGA has become field hair
Exhibition trend.With the raising of encapsulation integration density, micro-system internal node accessibility declines, after how realizing that micro-system is integrated
The test of the inside chip of high coverage rate becomes a problem.ADC units are the important modules in numerical model analysis micro-system, as
The interface of analogue technique and digital technology, the performance of ADC units directly determine the quality of micro-system performance, therefore, logarithmic mode
The test for mixing ADC performances in micro-system is particularly important.
Existing patent mainly has：(1) a kind of high-performance pipeline ADC frequency domain parameter assessment system based on SoPC, Shen
Please number：201610225902.4 publication No.：CN105808405A, the data that ADC is acquired in the patent need to be uploaded to by serial ports
Host computer analyzing processing, volume of transmitted data is big and processing capability in real time is poor；(2) survey of ADC chip characteristics parameter testing precision
Test system, application number：201510107533.4 publication No.：CN104734710A, ADC output ends are surveyed with special ATE in the patent
Equipment connection is tried, test system expensive is huge, and test operation difficulty is big.
In short, existing patent not yet carries out numerical model analysis micro-system ADC unit dynamic parametric tests research, and it is directed to ADC
Sampled data mostly uses greatly host computer or ATE equipment carries out analyzing processing, and the present invention overcomes the shortage of prior art, and fully combines micro-
The FPGA unit integrated in system, provides a kind of high-performance numerical model analysis micro-system ADC unit dynamic parameter testing systems.
Invention content
Present invention solves the technical problem that being：A kind of numerical model analysis micro-system ADC is overcome the deficiencies of the prior art and provide
Unit dynamic parameter testing system is generated and by Signal-regulated kinase by the acquisition of micro-system ADC units by signal generating module
Input signal is converted to digital signal by the input signal of processing by analog signal；Micro-system FPGA unit is mono- to micro-system ADC
Member sampling output data is acquired, stores and handles, and obtains the main dynamic performance parameter of micro-system ADC units.
Technical solution of the invention is：A kind of numerical model analysis micro-system ADC unit dynamic parameter testing systems, including
Including：Host computer and test board, wherein：
Host computer is responsible for that test result is shown and stored；
Test board includes signal generating module, Signal-regulated kinase, clock generation module, micro-system ADC units and micro-
System FPGA unit；Signal-regulated kinase is connected with signal generating module, micro-system ADC units and micro-system FPGA unit；
Clock generation module is connected with micro-system ADC units and micro-system FPGA unit；Micro-system FPGA unit passes through communication interface
It is connected with host computer；
Signal generating module generates a single tone sine wave signal using crystal oscillator；Signal-regulated kinase sends out signal
The signal that raw module generates is filtered, and generates ADC cell input signals；Clock generation module is by phase-locked loop pll circuit
It generates, clock is provided for ADC units and FPGA unit；The acquisition of micro-system ADC units is generated by signal generating module and by signal
The input signal of conditioning module processing, digital signal is converted to by the analog signal of input；Micro-system FPGA unit is to micro-system
ADC unit sampling output datas are acquired, store and handle, and obtain the dynamic performance parameter of micro-system ADC units, will test
As a result host computer is uploaded to by USB communication interface to be shown and stored.
The micro-system FPGA unit includes data acquisition module, data memory module, data processing module, excessively program-controlled
Molding block and communication module；
Data collecting module collected micro-system ADC unit samplings output data is simultaneously sent to data memory module, data processing
Module, data memory module store micro-system ADC unit sampling output datas, and data processing module is according to micro-system ADC units
Sampling output data obtains the dynamic performance parameter of micro-system ADC units and send to communication module, and communication module is by micro-system ADC
The dynamic performance parameter of unit is uploaded to host computer as test result, by USB communication interface and is shown and stored, process
Control module is realized to data acquisition module, data memory module, data processing module, the process control of communication module and tune
Degree.
The processing of the ADC unit sampling output datas is completed using micro-system FPGA unit.
The communication interface uses USB interface.
The advantages of the present invention over the prior art are that：
(1) FPGA unit that is internally integrated using micro-system completes micro-system ADC unit dynamic parameters in the present invention
Test, solves that micro-system internal node accessibility is poor, is not easy to carry out the problem of test；
(2) in the present invention in addition to external signal generates and improves, other processing are completed in micro-system, are compared in the past first
Caching is uploaded to upper computer software processing again, reduces the interference between the expense and signal of additional data transmissions, the test system
System enhances the accuracy and reliability of test data.
Description of the drawings
Fig. 1 is present invention test system global structure frame diagram.
Specific implementation mode
As shown in Figure 1, a kind of numerical model analysis micro-system ADC unit dynamic parameter testing systems of the present invention, including it is upper
Machine and test board；Host computer is responsible for that test result is shown and stored；Test board includes signal generating module, signal condition
Module, clock generation module, micro-system ADC units and micro-system FPGA unit；The Signal-regulated kinase respectively with signal
Module, micro-system ADC units and micro-system FPGA unit occurs to be connected；Clock generation module respectively with micro-system ADC units
And micro-system FPGA unit is connected；Micro-system FPGA unit is connected by communication interface with host computer；Micro-system FPGA unit
Including data acquisition module, data memory module, data processing module, process control module and communication module；
Signal generating module generates a single tone sine wave signal by crystal oscillator；Signal occurs for Signal-regulated kinase
The signal that module generates is filtered, and generates ADC cell input signals；Clock generation module is by phaselocked loop (PLL) circuit
It generates, clock is provided for ADC units and FPGA unit；The acquisition of micro-system ADC units is generated by signal generating module and by signal
The input signal of conditioning module processing, digital signal is converted to by the analog signal of input；Micro-system FPGA unit is to micro-system
ADC unit sampling output datas are acquired, store and handle, and obtain the main dynamic performance parameter of micro-system ADC units, survey
Test result is uploaded to host computer by USB communication interface and is shown and stored.
Signal generating module generates a single tone sine wave signal by crystal oscillator, and wherein crystal oscillator has low phase
Position noise, flat frequency response, appropriate harmonic performance.
The signal that Signal-regulated kinase selects bandpass filter to generate signal generating module is filtered, and is eliminated big
Part broadband noise obtains high quality ADC cell input signals.
Phaselocked loop (PLL) circuit that clock generation module is made of crystal oscillator, frequency synthesizer and voltage controlled oscillator realizes,
The module can provide required phase noise and shake the clock of index.
The input signal that the acquisition of micro-system ADC units is generated by signal generating module and handled by Signal-regulated kinase,
Input signal is sampled under the sampling clock provided by clock generation module, input analog signal is finally converted into number
Signal.
Micro-system FPGA unit, high-speed data of the analog signal by the acquisition output of ADC units is first with data acquisition module
Block receives and carries out serioparallel exchange, then the data after reduction of speed are cached by data memory module, finally utilizes at data
Reason module is to data cached windowed function and carries out Fast Fourier Transform (FFT) (FFT) operation and obtains spectrogram, true based on spectrogram
Determine fundamental wave energy, harmonic energy, DC energy and noise energy, the dynamic of ADC units is finally obtained according to dynamic parameter formula
Performance parameter.
The content that description in the present invention is not described in detail belongs to the known technology of those skilled in the art.
Claims (4)
1. a kind of numerical model analysis micro-system ADC unit dynamic parameter testing systems, it is characterised in that including including：Host computer and survey
Test plate (panel), wherein：
Host computer is responsible for that test result is shown and stored；
Test board includes signal generating module, Signal-regulated kinase, clock generation module, micro-system ADC units and micro-system
FPGA unit；Signal-regulated kinase is connected with signal generating module, micro-system ADC units and micro-system FPGA unit；Clock
Generation module is connected with micro-system ADC units and micro-system FPGA unit；Micro-system FPGA unit by communication interface with it is upper
Position machine is connected；
Signal generating module generates a single tone sine wave signal using crystal oscillator；To signal mould occurs for Signal-regulated kinase
The signal that block generates is filtered, and generates ADC cell input signals；Clock generation module is generated by phase-locked loop pll circuit,
Clock is provided for ADC units and FPGA unit；The acquisition of micro-system ADC units is generated by signal generating module and by signal condition mould
The input signal of block processing, digital signal is converted to by the analog signal of input；Micro-system FPGA unit is to micro-system ADC units
Sampling output data is acquired, stores and handles, and obtains the dynamic performance parameter of micro-system ADC units, test result is led to
It crosses USB communication interface and is uploaded to host computer and shown and stored.
2. a kind of numerical model analysis micro-system ADC unit dynamic parameter testing systems according to claim 1, feature exist
In：The micro-system FPGA unit includes data acquisition module, data memory module, data processing module, process control mould
Block and communication module；
Data collecting module collected micro-system ADC unit samplings output data is simultaneously sent to data memory module, data processing module,
Data memory module stores micro-system ADC unit sampling output datas, and data processing module is defeated according to micro-system ADC unit samplings
Go out data to obtain the dynamic performance parameter of micro-system ADC units and send to communication module, communication module is by micro-system ADC units
Dynamic performance parameter is uploaded to host computer as test result, by USB communication interface and is shown and stored, process control mould
Block realizes the process control and scheduling to data acquisition module, data memory module, data processing module, communication module.
3. a kind of numerical model analysis micro-system ADC unit dynamic parameter testing systems according to claim 1 or 2, feature
It is：The processing of the ADC unit sampling output datas is completed using micro-system FPGA unit.
4. a kind of numerical model analysis micro-system ADC unit dynamic parameter testing systems according to claim 1 or 2, feature
It is：The communication interface uses USB interface.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111130545A (en) * | 2019-12-02 | 2020-05-08 | 北京时代民芯科技有限公司 | DAC/ADC unit loop test system of digital-analog hybrid microsystem |
| CN112910463A (en) * | 2021-01-27 | 2021-06-04 | 湖南品腾电子科技有限公司 | Data acquisition and analysis test platform and method for ADC (analog to digital converter) static parameters and noise indexes |
| CN117691999A (en) * | 2023-12-25 | 2024-03-12 | 湖南进芯电子科技有限公司 | Dynamic parameter testing method for ADC in DSP |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111130545A (en) * | 2019-12-02 | 2020-05-08 | 北京时代民芯科技有限公司 | DAC/ADC unit loop test system of digital-analog hybrid microsystem |
| CN111130545B (en) * | 2019-12-02 | 2023-07-04 | 北京时代民芯科技有限公司 | Digital-analog hybrid microsystem DAC/ADC unit loop test system |
| CN112910463A (en) * | 2021-01-27 | 2021-06-04 | 湖南品腾电子科技有限公司 | Data acquisition and analysis test platform and method for ADC (analog to digital converter) static parameters and noise indexes |
| CN117691999A (en) * | 2023-12-25 | 2024-03-12 | 湖南进芯电子科技有限公司 | Dynamic parameter testing method for ADC in DSP |
| CN117691999B (en) * | 2023-12-25 | 2024-06-21 | 湖南进芯电子科技有限公司 | Dynamic parameter testing method for ADC in DSP |
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