CN207397263U - A kind of proof of algorithm device - Google Patents
A kind of proof of algorithm device Download PDFInfo
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- CN207397263U CN207397263U CN201721416194.9U CN201721416194U CN207397263U CN 207397263 U CN207397263 U CN 207397263U CN 201721416194 U CN201721416194 U CN 201721416194U CN 207397263 U CN207397263 U CN 207397263U
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Abstract
In proof of algorithm, simple software emulation is often not accurate enough, and is verified again if being converted to hardware, than relatively time-consuming.The present apparatus makes full use of the function of existing instrument, and directly the communication of algorithms is put into actual environment and is tested, and accelerates the iteration of proof of algorithm.It combines the advantages of software emulation and hardware testing, can fast and effectively verification algorithm.
Description
Technical field
The present apparatus is related to FPGA and the communications field, and in particular to a kind of device of proof of algorithm, available for fast and effectively
Verify the communication of algorithms.
Background technology
In communication products development process, the exploitation and verification of physical layer algorithm are first carried out with matlab or C language etc., so
After could carry out hardware design.A critically important step is the verification to physical layer algorithm among these.
Two kinds of the general component software mode of traditional proof of algorithm and hardware mode：
（1）Software mode needs to establish channel model, and then the algoritic module of sending and receiving is communicated by the model.By
The limitation of model accuracy it is difficult to close to real physical channel, even differs greatly sometimes.
（2）Hardware mode will design circuit or algorithm is converted into HDL language, and compiling, placement-and-routing download to
On FPGA.Hardware design takes a long time, easily the even several months in several weeks.And algorithm changes every time, will change hardware and set
Meter, the iteration cycle for causing verification are very long.
As it can be seen that software mode ratio is very fast, but it is not actual physical channel；Hardware mode is slow, but can be in actual channel
Upper test.
It if both modes combined, maximizes favourable factors and minimizes unfavourable ones, then can fast and effectively verify the communication of algorithms.
Presently relevant way is：Algorithm software（On computer）, data buffer storage device is connect, then connects AFE(analog front end).Wherein, number
It is used to store the transmission data of algorithm generation according to buffer storage and is transmitted to the DAC of AFE(analog front end), and the adc data of AFE(analog front end)
It is transmitted to computer.Receiving portion in AFE(analog front end) is typically complex, including circuit coupling, gain-adjusted, filtering, ADC etc.,
Most of is analog circuit.As it can be seen that the buffer storage, AFE(analog front end) in this mode are required for specially designing hardware, still need
Want no small workload.
The present apparatus further reduces the workload of hardware design, and directly the communication of algorithms is put into actual environment and is tested,
Accelerate the iteration of proof of algorithm.
The content of the invention
The mentality of designing of the present apparatus is to reduce the required hardware development of proof of algorithm to the greatest extent, i.e., with general device and
Instrument is substituted for the hardware verified certain algorithm and specially developed.Specifically：
The present apparatus, which is divided into, sends and receives two parts：
Transmitting portion includes computer, FPGA plates, AFE(analog front end), and computer connects FPGA plates, the connection of FPGA plates by JTAG lines
Matlab and Quartus softwares are run on AFE(analog front end), wherein computer, the communication of algorithms is run on matlab and generates transmission number
According to Quartus downloads to transmission data in the embedded RAM of FPGA by JTAG, and the ADC interface control circuit of FPGA is RAM
In data be transmitted to the ADC of AFE(analog front end), the analog signal of ADC outputs is connected to communication line by line interface；
Receiving portion includes computer, digital oscilloscope, AFE(analog front end), and oscilloprobe is at the line interface of AFE(analog front end)
Pickup receives signal, and the data that oscillograph is adopted are transmitted to computer by USB line, the matlab operation communication of algorithms run on computer
And handle the data that oscillograph receives.
Specific operation process is accordingly：
The first step establishes newly built construction in Quartus, comprising RAM and ADC interface circuit, compiles and is configured in FPGA；
Second step, algorithm to be verified are run on matlab, and generation sends data and is converted into the file of mif forms；
3rd step, Quartus call its instrument " In-System Memory Content Editor " by second step
Mif files are updated into RAM；
4th step, ADC interface circuit pass to data sending in RAM to ADC, generation analog signal on communication line；
5th step is picked up at the line interface of AFE(analog front end) with oscilloprobe and receives signal, adjusts oscillograph manually
Vertical gain knob waveform is made to enter OK range, base knob is to obtain suitable sample rate when adjusting oscillograph manually；
6th step, the data adopted with the oscillograph driving acquirement oscillograph on computer are simultaneously stored to hard disk with document form；
7th step, the data file that matlab readings receive, and algorithm is run to handle the data, the knot demodulated
Fruit data；
The result data of demodulation with original transmission data is compared, carrys out the transmitting-receiving effect of check algorithm by the 8th step,
If it is not up to standard to receive and dispatch effect, changes algorithm and repeat second step to the 8th step.
In above device, transmitting portion make use of FPGA and Quartus softwares general in the industry, be utilized in receiving portion
Common digital oscilloscope.The function replacements such as sampling, gain-adjusted, DAC in oscillograph traditional analog front end receiving unit
The correlation function divided.In this way, the hardware designed for verification algorithm is just seldom, only ADC portion and line interface circuit.
The advantageous effect of the device is that the communication of algorithms can be placed directly in actual environment and test, so as to direct and effective
Examine algorithm；Simultaneously as general instrument and device have been used, it is easily operated, and to verify the hardware done
Exploitation is reduced to minimum.Such verification is not only effectively but also quick.
Description of the drawings
Fig. 1 is the block diagram of the present apparatus.
Specific embodiment
With reference to Fig. 1, device, which is divided into, sends and receives two parts, and the two is connected by communication channel, wherein：
Transmitting portion includes computer, FPGA plates, AFE(analog front end), and computer connects FPGA plates, the connection of FPGA plates by JTAG lines
Matlab and Quartus softwares are run on AFE(analog front end), wherein computer, the communication of algorithms is run on matlab and generates transmission number
According to Quartus downloads to transmission data in the embedded RAM of FPGA by JTAG, and the ADC interface control circuit of FPGA is RAM
In data be transmitted to the ADC of AFE(analog front end), the analog signal of ADC outputs is connected to communication line by line interface；
Receiving portion includes computer, digital oscilloscope, AFE(analog front end), and oscilloprobe is at the line interface of AFE(analog front end)
Pickup receives signal, and the data that oscillograph is adopted are transmitted to computer by USB line, the matlab operation communication of algorithms run on computer
And handle the data that oscillograph receives.
Specific operation process is accordingly：
The first step establishes newly built construction in Quartus, comprising RAM and ADC interface circuit, compiles and is configured in FPGA；
Second step, algorithm to be verified are run on matlab, and generation sends data and is converted into the file of mif forms；
3rd step, Quartus call its instrument " In-System Memory Content Editor " by second step
Mif files are updated into RAM；
4th step, ADC interface circuit pass to data sending in RAM to ADC, generation analog signal on communication line；
5th step is picked up at the line interface of AFE(analog front end) with oscilloprobe and receives signal, adjusts oscillograph manually
Vertical gain knob waveform is made to enter OK range, base knob is to obtain suitable sample rate when adjusting oscillograph manually；
6th step, the data adopted with the oscillograph driving acquirement oscillograph on computer are simultaneously stored to hard disk with document form；
7th step, the data file that matlab readings receive, and algorithm is run to handle the data, the knot demodulated
Fruit data；
The result data of demodulation with original transmission data is compared, carrys out the transmitting-receiving effect of check algorithm by the 8th step,
If it is not up to standard to receive and dispatch effect, changes algorithm and repeat second step to the 8th step.
Claims (1)
1. a kind of proof of algorithm device, is divided into and sends and receives two parts, it is characterised in that：
Transmitting portion includes computer, FPGA plates, AFE(analog front end), and computer connects FPGA plates, the connection simulation of FPGA plates by JTAG lines
Matlab and Quartus softwares are run on front end, wherein computer, the communication of algorithms is run on matlab and generates transmission data,
Quartus downloads to transmission data in the embedded RAM of FPGA by JTAG, and the ADC interface control circuit of FPGA is in RAM
Data are transmitted to the ADC of AFE(analog front end), and the analog signal of ADC outputs is connected to communication line by line interface；
Receiving portion includes computer, digital oscilloscope, AFE(analog front end), and oscilloprobe picks up at the line interface of AFE(analog front end)
Signal is received, the data that oscillograph is adopted are transmitted to computer by USB line, and the matlab operation communication of algorithms run on computer is simultaneously located
The data that reason oscillograph receives.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721416194.9U CN207397263U (en) | 2017-10-31 | 2017-10-31 | A kind of proof of algorithm device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201721416194.9U CN207397263U (en) | 2017-10-31 | 2017-10-31 | A kind of proof of algorithm device |
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| CN207397263U true CN207397263U (en) | 2018-05-22 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107544911A (en) * | 2017-10-31 | 2018-01-05 | 南京火零信息科技有限公司 | A kind of proof of algorithm device |
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2017
- 2017-10-31 CN CN201721416194.9U patent/CN207397263U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107544911A (en) * | 2017-10-31 | 2018-01-05 | 南京火零信息科技有限公司 | A kind of proof of algorithm device |
| CN107544911B (en) * | 2017-10-31 | 2024-06-07 | 南京火零信息科技有限公司 | Algorithm verification device |
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| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: An algorithm verification device Effective date of registration: 20211229 Granted publication date: 20180522 Pledgee: China Construction Bank Corporation Nanjing Gulou sub branch Pledgor: NANJING HUOLING INFORMATION TECHNOLOGY CO.,LTD. Registration number: Y2021980016918 |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20221212 Granted publication date: 20180522 Pledgee: China Construction Bank Corporation Nanjing Gulou sub branch Pledgor: NANJING HUOLING INFORMATION TECHNOLOGY CO.,LTD. Registration number: Y2021980016918 |
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