CN116909935B - Chip joint simulation method, device and medium based on single processing module interface - Google Patents
Chip joint simulation method, device and medium based on single processing module interface Download PDFInfo
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- CN116909935B CN116909935B CN202311176044.5A CN202311176044A CN116909935B CN 116909935 B CN116909935 B CN 116909935B CN 202311176044 A CN202311176044 A CN 202311176044A CN 116909935 B CN116909935 B CN 116909935B
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- 238000012545 processing Methods 0.000 title claims abstract description 35
- 238000012795 verification Methods 0.000 claims abstract description 53
- 238000013461 design Methods 0.000 claims abstract description 45
- 238000012360 testing method Methods 0.000 claims abstract description 14
- 230000000052 comparative effect Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 5
- 230000009286 beneficial effect Effects 0.000 description 2
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- 238000001514 detection method Methods 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3652—Software debugging using additional hardware in-circuit-emulation [ICE] arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3656—Software debugging using additional hardware using a specific debug interface
Abstract
The invention relates to the technical field of chip verification, in particular to a chip joint simulation method, device and medium based on a single processing module interface, wherein the method comprises the following steps of S1, inputting the same test cases into a chip design to be tested and a simulation model; step S2, simulating the ith single processing module to output an interface C i The output data is stored to C i Corresponding first-in first-out queue Q i In (a) and (b); step S3, acquiring an ith single processing module to-be-tested output interface D of the chip to be tested design in real time i Output data DA i And from Q i Reads out the current Q i Data CA stored first in i The method comprises the steps of carrying out a first treatment on the surface of the Step S4, contrast DA i 、CA i If all DA i =CA i Step S1-step S4 are circularly executed to carry out joint simulation, if DA appears i ≠CA i And ending the joint simulation and generating chip verification failure prompt information. The invention improves the efficiency of chip verification and reduces the cost of chip verification.
Description
Technical Field
The present invention relates to the field of chip verification technologies, and in particular, to a method, an apparatus, and a medium for joint simulation of chips based on a single processing module interface.
Background
In the process of chip verification, test stimulus is required to be input into a chip design under Test (Design Under Test, DUT for short) and data output by the chip design under Test is stored, a simulation model (CModel) written by a C program, which is the same as the logic of the chip design under Test, is required to be set, the same Test stimulus (Test Case) is input into the simulation model, and data output by the simulation model is stored. The chip design to be tested and the simulation model are independently operated respectively, a large amount of time is required for the complete operation of the chip design to be tested and the simulation model to be tested, the output data are also independently stored respectively, the output data are huge, and a large amount of storage space is required to be occupied. And after the chip design to be tested and the simulation model are completely operated, comparing the data output by the chip design to be tested and the simulation model to verify the chip design to be tested. However, the chip verification method has no real-time performance, complicated verification process and time-consuming verification process, so that the chip verification efficiency is low and the cost is high. Therefore, how to improve the efficiency of chip verification and reduce the cost of chip verification is a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a chip joint simulation method, device and medium based on a single processing module interface, which improves the efficiency of chip verification and reduces the cost of chip verification.
According to a first aspect of the present invention, there is provided a chip joint simulation method based on a single processing module interface, including:
s1, inputting the same test case to a chip design to be tested and a simulation model at the same time, wherein the chip design to be tested is generated based on a hardware description language, the simulation model is generated based on a high-level language, and the running speed of the simulation model is faster than that of the chip design to be tested;
step S2, simulating the ith single processing module to output an interface C i The output data is stored to C i Corresponding first-in first-out queue Q i Wherein, the value range of I is 1 to I, I is the total number of output interfaces of a single processing module, C i The output data is only used for outputting the output data of a single processing module;
step S3, acquiring an ith single processing module to-be-tested output interface D of the chip to be tested design in real time i Output data DA i And from Q i Reads out the current Q i Data CA stored first in i ，D i The output data is only used for outputting the output data of a single processing module;
step S4, contrast DA i 、CA i If all DA i =CA i Step S1-step S4 are circularly executed to carry out joint simulation, if DA appears i ≠CA i And ending the joint simulation and generating chip verification failure prompt information.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium having computer instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the chip joint simulation method, the device and the medium based on the single processing module interface can achieve quite technical progress and practicality, and have wide industrial utilization value, and the chip joint simulation method, the device and the medium have at least the following beneficial effects:
the invention directly carries out joint simulation on the chip design to be tested and the simulation model, only needs to store the data output by the single processing module interface of the simulation model, compares the data output by the chip design to be tested with the data corresponding to the simulation model in real time, detects in real time, deletes the data corresponding to the simulation model when the detection passes, reduces the occupation of storage space, improves the efficiency of chip verification and reduces the cost of chip verification.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for joint simulation of chips based on a single processing module interface according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
An embodiment of a first aspect of the present invention provides a chip joint simulation method based on a single processing module interface, as shown in fig. 1, including:
s1, inputting the same test case to a chip design to be tested and a simulation model at the same time, wherein the chip design to be tested is generated based on a hardware description language, the simulation model is generated based on a high-level language, and the running speed of the simulation model is faster than that of the chip design to be tested.
It should be noted that the chip to be tested has the same functions as the simulation model, and the single processing module interfaces are the same, but are written and generated by different languages, and as an example, the hardware description language is Verilog, and the high-level language is C language. The test system comprises a drive processing module arranged on a chip verification platform (Testbench), and the same test case is input to a chip design to be tested and a simulation model.
Step S2, simulating the ith single processing module to output an interface C i The output data is stored to C i Corresponding first-in first-out queue Q i Wherein, the value range of I is 1 to I, I is the total number of output interfaces of a single processing module, C i Only for outputting output data of a single processing module.
Wherein the fifo queue may be a FIFO (First Input First Output) memory, it being understood that in the simulation model, only a single processing module and C are present i Is connected through C i Outputting data, wherein the chip to be tested is designed to have only a single processing module and D i Is connected through D i Outputting the data.
Step S3, acquiring an ith single processing module to-be-tested output interface D of the chip to be tested design in real time i Output data DA i And from Q i Reads out the current Q i Data CA stored first in i ，D i Only for outputting output data of a single processing module.
It should be noted that only one integer "int" data buffer DA needs to be set i Can be obtained without additional D i A memory is provided. Only need to be C i Setting first-in first-out queues to store C i And outputting the data. As an example, in the step S3, when Q is i Reads out the current Q i Data CA stored first in i Thereafter, the read CA i From Q i And deleted. In the prior art, the design and simulation model of the chip to be tested need to be independently operated, all output data need to be stored in a memory respectively after the operation is finished, and then comparison is carried out, and a large amount of space needs to be occupied.
Step S4, contrast DA i 、CA i If all DA i =CA i Step S1-step S4 are circularly executed to carry out joint simulation, if DA appears i ≠CA i And ending the joint simulation and generating chip verification failure prompt information.
It should be noted that, for each design of the chip to be tested and the data output by the simulation output interface of the simulation model, the manner of step S1-step S4 is adopted to compare in real time, when any DA appears i ≠CA i The method and the device for verifying the chip have the advantages that the chip verification fails, the joint simulation is immediately ended, prompt is carried out, subsequent operation is not needed to be executed, and in the prior art, data comparison can be carried out after the chip design to be tested and the simulation model are operated respectively, so that compared with the prior art, the method and the device for verifying the chip have the advantages that the chip verification efficiency is greatly improved, and the chip verification cost is reduced.
As an embodiment, the step S2 includes:
step S21, simulating the ith single processing module to output an interface C i The output data are converted into data described in SystemVerilog language.
Step S22, storing the data converted into SystemVerilog language description into C i Corresponding first-in first-out queue Q i Is a kind of medium.
C is the same as i The output data is the data described in a high-level language and cannot be directly connected with D i The output data is compared, thus C i Firstly, the output data is transmitted to a chip verification platform, and the chip verification platform transmits C i The output data is converted into data described by SystemVerilog language, and the data described by SystemVerilog language can be directly combined with D i And comparing the output data of the hardware description language.
Because the running speed of the simulation model is faster than that of the chip design to be tested, the simulation model can run before the chip design to be tested, but the simulation model needs to wait for the condition that the recovery information needs to be waited for before the continuous execution, and the simulation model can run before the chip design to be tested for the data without waiting for the recovery information, so that the accuracy of the joint simulation is ensured. As an embodiment, the step S2 includes:
step S211, if present C i Output data CA i For the preset first type data, then continue C i If the current C is the output operation of i Output data CA i For the preset second type of data, pause C i Output operation of (D) to be D i Output corresponding to CA i Comparative data DA i And CA i =DA i When based on DA i Generating corresponding reply information H i Simultaneously sent to C i And D i When C i Receiving H i When continue C i The first type data is data without waiting for reply information, and the second type data is data with need of receiving the reply information.
Through step S211, it can be ensured that the input information of the chip design to be tested and the simulation model are always synchronous, and the input information is the same.
C i Output data CA i Specifically, control data, read instruction data, write instruction data, and the like may be used.
As an example, in the step S211, if C i Output data CA i To read instruction data, CA i Includes a target read address, if the read instruction data is the second type data, waiting for CA i =DA i When based on DA i Acquiring target read data corresponding to the target read address from a preset memory, and simultaneously transmitting the target read data to C i And D i 。
It should be noted that, in the process of joint simulation, the chip design to be tested and the simulation model always correspond to the same memory, when the read instruction data is the second type data, C i Output data CA i The data is not read immediately into memory, but need to wait until D i Output DA i And comparing to obtain CA i =DA i After the result, based on DA i Acquiring target read data corresponding to the target read address from a preset memory, and simultaneously transmitting the target read data to C i And D i Thereby avoiding C i And D i Different read data are acquired based on the same read instruction data, resulting in joint simulation errors.
As an example, in the step S211, if C i Output data CA i To write instruction data, CA i Includes target write address information and target write data, if the write instruction data is the second type data, waiting for CA i =DA i When based on DA i Writing target writing data into a target writing address of a preset memory, generating confirmation writing information, and simultaneously transmitting the confirmation writing information to C i And D i 。
It should be noted that, in the process of joint simulation, the chip design to be tested and the simulation model always correspond to the same memory, and when the write instruction data is the second type data, C i Output data CA i Data is not written immediately into memory at that time, but is required to wait until D i Output DA i And comparing to obtain CA i =DA i After the result, based on DA i Writing target writing data into a target writing address of a preset memory, and simultaneously transmitting confirmed writing information to C i And D i Thereby avoiding causing joint simulation errors.
As an embodiment, in the step S4, generating chip verification failure prompting information includes:
step S41, DA based on inequality i 、CA i Corresponding D i And C i And generating chip verification failure prompt information.
As can be seen from step S41, the embodiment of the present invention not only can acquire the chip verification result in real time, but also can include error data and corresponding interface information in the chip verification result, thereby providing support for user debugging.
In some application scenarios, although each set of CAs i 、DA i The comparison is passed, but the chip verification is not necessarily successful, because there is no comparison data in the design of the chip to be tested or the simulation model at the end of the joint simulation, and under the condition, the chip verification is problematic, and the corresponding error reporting is needed.
As an embodiment, the method further includes step S10, obtaining a simulation state identifier from a state machine corresponding to the chip design to be tested, and if the obtained simulation ending identifier is an ending state, executing step S20;
step S20, judging whether at least one D exists currently i There is also an uncompromised DA i If so, generating chip verification failure prompt information.
In the step S20, generating chip verification failure prompt information includes:
step S201, based on the DA without contrast i Corresponding D i And C i And generating chip verification failure prompt information.
When the simulation ending mark is obtained to be in an ending state, the joint simulation is ended, and DA does not appear in the joint simulation process i ≠CA i But currently if there is at least one D i There is also an uncompromised DA i It is indicated that the chip verification was not successful and that the problem that may be the chip design under test at this time may be that of the simulation model, and thus based on the uncompromised DA i Corresponding D i And C i GeneratingThe chip verification failure prompt information provides reference for subsequent debugging of the user.
As an embodiment, the method further includes step S100, obtaining a simulation state identifier from a state machine corresponding to the chip design to be tested, and if the obtained simulation ending identifier is an ending state, executing step S200;
step S200, judging whether at least one Q exists currently i If the chip is not empty, generating chip verification failure prompt information.
In the step S200, generating chip verification failure prompt information includes:
step S2001, based on Q not being empty i The current first stored data CA i And corresponding D i And C i And generating chip verification failure prompt information.
When the simulation ending mark is obtained to be in an ending state, the joint simulation is ended, and DA does not appear in the joint simulation process i ≠CA i But currently if there is at least one Q i If not empty, it is indicated that the chip verification is not successful, and the problem of the chip design to be tested may be the problem of the simulation model at the moment, so the method is based on Q which is not empty i The current first stored data CA i And corresponding D i And C i Generating chip verification failure prompt information and providing reference for subsequent debugging of a user.
As an embodiment, the method further includes step S01, obtaining a simulation state identifier from the state machine corresponding to the chip design to be tested, if the obtained simulation ending identifier is an ending state, and all D i None of them has an uncompromised DA i All Q i And if the chip verification is empty, generating a prompt message of successful chip verification.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, and the computer instructions are used for executing the method of the embodiment of the invention.
The embodiment of the invention directly carries out joint simulation on the chip design to be tested and the simulation model, only needs to store the data output by the single processing module interface of the simulation model, compares the data output by the chip design to be tested with the data corresponding to the simulation model in real time, detects in real time, deletes the data corresponding to the simulation model when the detection passes, reduces the occupation of storage space, improves the efficiency of chip verification and reduces the cost of chip verification.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (10)
1. The chip joint simulation method based on the single processing module interface is characterized by comprising the following steps of:
s1, inputting the same test case to a chip design to be tested and a simulation model at the same time, wherein the chip design to be tested is generated based on a hardware description language, the simulation model is generated based on a high-level language, and the running speed of the simulation model is faster than that of the chip design to be tested;
step S2, simulating the ith single processing module to output an interface C i The output data is stored to C i Corresponding first-in first-out queue Q i Wherein, the value range of I is 1 to I, I is the total number of output interfaces of a single processing module, C i The output data is only used for outputting the output data of a single processing module;
the step S2 includes:
step S211, if present C i Output data CA i For the preset first type data, then continue C i If the current C is the output operation of i Output data CA i For the preset second type of data, pause C i Output operation of (D) to be D i Output corresponding to CA i Comparative data DA i And CA i =DA i When based on DA i Generating corresponding reply information H i Simultaneously sent to C i And D i When C i Receiving H i When continue C i The preset first type data is data without waiting for reply information, and the preset second type data is data with the need of receiving the reply information;
step S3, acquiring an ith single processing module to-be-tested output interface D of the chip to be tested design in real time i Output data DA i And from Q i Reads out the current Q i Data CA stored first in i ，D i The output data is only used for outputting the output data of a single processing module;
step S4, contrast DA i 、CA i If all DA i =CA i Step S1-step S4 are circularly executed to carry out joint simulation, if DA appears i ≠CA i And ending the joint simulation and generating chip verification failure prompt information.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S2 includes:
step S21, simulating the ith single processing module to output an interface C i Converting the output data into data described by SystemVerilog language;
step S22, storing the data converted into SystemVerilog language description into C i Corresponding first-in first-out queue Q i Is a kind of medium.
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
in the step S4, generating chip verification failure prompt information includes:
step S41, DA based on inequality i 、CA i Corresponding D i And C i And generating chip verification failure prompt information.
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
step S10, a simulation state identifier is obtained from a state machine corresponding to the chip design to be tested, and if the obtained simulation ending identifier is an ending state, step S20 is executed;
step S20, judging whether at least one D exists currently i There is also an uncompromised DA i If so, generating chip verification failure prompt information.
5. The method of claim 4, wherein the step of determining the position of the first electrode is performed,
in the step S20, generating chip verification failure prompt information includes:
step S201, based on the DA without contrast i Corresponding D i And C i And generating chip verification failure prompt information.
6. The method of claim 1, wherein the step of determining the position of the substrate comprises,
step S100, a simulation state identifier is obtained from a state machine corresponding to the chip design to be tested, and if the obtained simulation ending identifier is an ending state, step S200 is executed;
step S200, judging whether at least one Q exists currently i If the chip is not empty, generating chip verification failure prompt information.
7. The method of claim 6, wherein the step of providing the first layer comprises,
in the step S200, generating chip verification failure prompt information includes:
step S2001, based on Q not being empty i The current first stored data CA i And corresponding D i And C i And generating chip verification failure prompt information.
8. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the hardware description language is Verilog, and the high-level language is C language.
9. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-8.
10. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-8.
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