CN114429095B - Fault simulation method and system of quantum circuit, storage medium and electronic device - Google Patents

Fault simulation method and system of quantum circuit, storage medium and electronic device Download PDF

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CN114429095B
CN114429095B CN202210352795.7A CN202210352795A CN114429095B CN 114429095 B CN114429095 B CN 114429095B CN 202210352795 A CN202210352795 A CN 202210352795A CN 114429095 B CN114429095 B CN 114429095B
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官极
黄鸣宇
应明生
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Beijing Zhongke Arc Quantum Software Technology Co ltd
Institute of Software of CAS
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Abstract

The invention relates to the technical field of quantum circuit fault simulation, in particular to a fault simulation method, a fault simulation system, a storage medium and electronic equipment of a quantum circuit, wherein the method comprises the following steps: the method comprises the steps of obtaining a super operator corresponding to a fault quantum circuit to be tested, obtaining a Kraus matrix set corresponding to each logic super operator in the super operator, and calculating the fault influence rate of faults in the fault quantum circuit to be tested based on input state data, expected output state data and all Kraus matrix sets.

Description

Fault simulation method and system of quantum circuit, storage medium and electronic equipment
Technical Field
The invention relates to the technical field of quantum circuit fault simulation, in particular to a fault simulation method and system of a quantum circuit, a storage medium and electronic equipment.
Background
Simulation plays an important role in digital circuit verification, test development, design debugging and diagnostics before a circuit is physically built. In particular, fault emulation simulates a faulty digital circuit. It has two main purposes: firstly, fault-free (logic) simulation is carried out, so that a designer is helped to verify whether the design of a digital circuit conforms to the expected functional description; the second is to determine the efficiency of test patterns in detecting faults of interest, such patterns typically being generated by an Automatic Test Pattern Generator (ATPG). Fault simulation can now be effectively applied to large scale integrated circuits and standard techniques for Electronic Design Automation (EDA) have been developed.
However, currently in quantum computing, physicists often construct designed quantum circuits through experimentation and then estimate their performance in the presence of quantum faults. Among them, the quantum fault includes not only a design error and a manufacturing defect of the quantum circuit as the classical fault but also quantum noise from the surrounding environment, and the quantum noise is inevitable in the current noisy medium quantum (NISQ) era. For example, researchers have implemented a circuit with four qubits and four controlled quantum logic gates for the experiments of the HHL algorithm (which can exponentially accelerate the solution of a linear system of equations on a quantum computer). In circuit performance testing, three different states were input into the circuit, with the fidelity of the actual output state compared to the ideal output state being 99.3%, 82.5%, and 83.6%, respectively. Google also uses a similar approach to identify quantum dominance (i.e., beyond classical calculations), sampling 53 qubit quantum circuits with 0.2% fidelity.
It is clear that due to the expensive resources and the stringent conditions of experimentally implementing quantum circuits (e.g. the ambient temperature must be close to absolute zero) and the uncertainty of reading the quantum states, it is helpful and more cost-effective to fault-simulate quantum circuits (on classical computers) before physically building them. On the other hand, it is not expected to be successful to directly popularize the existing fault simulation method of the classical circuit to the quantum circuit. One major reason is that quantum fault simulation is usually quantitative, rather than qualitative as in classical fault simulation: the input/output of a quantum circuit is a vector or matrix of complex numbers, while the input/output of a classical circuit is a boolean value, i.e. 0 or 1. This root distinction requires quantum fault simulation to be built in a new way.
At present, there are mainly two methods for simulating quantum faults. One is a vector-based simulation method for specific design errors (e.g., single quantum gate missing) and manufacturing defects (e.g., actually manufactured quantum CNOT gates). And secondly, aiming at the faults caused by the quantum noise, a simulation method based on a density matrix is provided and is embedded into almost all the currently popular quantum circuit programming platforms, such as IBM Qiskit, Microsoft Q # and Google Cirq. Its strategy is to update the density matrix of stored quantum states by applying matrix operations directly in the mathematical model of each fault of interest.
Unfortunately, since the dimension of the state space increases exponentially with the number of qubits (qubits), the scalability (≦ 10 qubits) of the above simulation method is far from satisfying the applications of the NISQ (NISQ is an abbreviation of noise Intermediate-Scale Quantum, which means: medium Quantum with noise) era (the number of bits of the Quantum circuit is ≧ 50qubits and
Figure 956576DEST_PATH_IMAGE001
complex matrix of (a).
Disclosure of Invention
The invention provides a fault simulation method and system of a quantum circuit, a storage medium and electronic equipment, aiming at the defects of the prior art.
The invention discloses a fault simulation method of a quantum circuit, which comprises the following technical scheme:
acquiring a super operator corresponding to a fault quantum circuit to be tested, and acquiring a Kraus matrix set corresponding to each logic super operator in the super operators;
calculating a fault influence rate of a fault in the fault quantum circuit to be tested based on input state data, expected output state data and all Kraus matrix sets, wherein the expected output state data refers to: and when the input state data is input into the quantum circuit to be tested, which eliminates the fault, outputting the data.
The fault simulation method of the quantum circuit has the following beneficial effects:
simulation experiment results show that the invention can simulate the fault quantum circuit with the size exceeding 5000 quantum bits, can meet the application of the NISQ era, has wide applicability, can be independently used, and can also be integrated into a currently developed quantum automatic test mode generation program for verifying and detecting the design error, the manufacturing defect and the quantum noise effect of the quantum circuit.
On the basis of the scheme, the fault simulation method of the quantum circuit can be further improved as follows.
Further, the calculating the fault influence rate of the fault in the fault quantum circuit to be tested includes:
the fault influence rate is as follows:
Figure 661227DEST_PATH_IMAGE002
wherein, in the step (A),
Figure 265384DEST_PATH_IMAGE003
representing the input state data of the said device,
Figure 702181DEST_PATH_IMAGE004
to represent
Figure 657368DEST_PATH_IMAGE005
The complex number of the first and second phase is conjugated and transposed,
Figure 837814DEST_PATH_IMAGE006
representing the desired output state data, and,
Figure 562056DEST_PATH_IMAGE007
the complex number of the,
Figure 169755DEST_PATH_IMAGE008
the complex number of the,
Figure 81079DEST_PATH_IMAGE009
，
Figure 65216DEST_PATH_IMAGE010
is shown as
Figure 643964DEST_PATH_IMAGE011
Logical super operator
Figure 422565DEST_PATH_IMAGE012
The total number of Kraus matrixes in the corresponding Kraus matrix set,
Figure 821185DEST_PATH_IMAGE013
represents: first, the
Figure 343433DEST_PATH_IMAGE011
Logical super operator
Figure 776689DEST_PATH_IMAGE012
The second in the corresponding set of Kraus matrices
Figure 726190DEST_PATH_IMAGE014
A matrix of a number of Kraus's,
Figure 877686DEST_PATH_IMAGE015
is that
Figure 938046DEST_PATH_IMAGE016
The complex number of the,
Figure 491387DEST_PATH_IMAGE017
，
Figure 611789DEST_PATH_IMAGE018
denotes the first
Figure 985002DEST_PATH_IMAGE019
Logical super operator
Figure 849053DEST_PATH_IMAGE020
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure 256900DEST_PATH_IMAGE021
denotes the first
Figure 548204DEST_PATH_IMAGE022
Logical super operator
Figure 408713DEST_PATH_IMAGE023
The second in the corresponding set of Kraus matrices
Figure 76455DEST_PATH_IMAGE024
A matrix of a number of Kraus's,
Figure 338809DEST_PATH_IMAGE025
the complex number of the,
Figure 801014DEST_PATH_IMAGE026
，
Figure 148819DEST_PATH_IMAGE027
representing the 1 st logical super operator
Figure 620251DEST_PATH_IMAGE028
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure 940374DEST_PATH_IMAGE029
representing the 1 st logical super operator
Figure 698115DEST_PATH_IMAGE030
The second in the corresponding set of Kraus matrices
Figure 674161DEST_PATH_IMAGE031
A matrix of a number of Kraus's,
Figure 808339DEST_PATH_IMAGE032
is that
Figure 982969DEST_PATH_IMAGE033
The complex number of the,
Figure 52556DEST_PATH_IMAGE034
，
Figure 109373DEST_PATH_IMAGE035
representing the total number of all logical super operators,
Figure 188188DEST_PATH_IMAGE036
、
Figure 14061DEST_PATH_IMAGE011
、
Figure 254550DEST_PATH_IMAGE037
and
Figure 533084DEST_PATH_IMAGE038
are all positive integers.
The invention discloses a fault simulation system of a quantum circuit, which comprises the following technical scheme:
comprises an acquisition module and a calculation module;
the acquisition module is configured to: acquiring a super operator corresponding to a fault quantum circuit to be tested, and acquiring a Kraus matrix set corresponding to each logic super operator in the super operators;
the calculation module is configured to: calculating a fault influence rate of a fault in the fault quantum circuit to be tested based on input state data, expected output state data and all Kraus matrix sets, wherein the expected output state data refers to: and when the input state data is input into the quantum circuit to be tested with the fault eliminated, outputting the data.
The fault simulation system of the quantum circuit has the following beneficial effects:
the quantum circuit to be tested, namely the defective quantum circuit, is represented as a plurality of Kraus matrix sets, the quantum circuit to be tested can be coded into a tensor network with double size, the contraction calculation efficiency of the tensor network is high, the contraction of the tensor network can be calculated quickly, fault simulation can be completed in a short time, and the fault influence rate of the fault in the quantum circuit to be tested can be obtained.
On the basis of the scheme, the fault simulation system of the quantum circuit can be further improved as follows.
Further, the fault influence rate is as follows:
Figure 884431DEST_PATH_IMAGE039
wherein, in the process,
Figure 95970DEST_PATH_IMAGE003
representing the input stateThe data of the data is transmitted to the data receiver,
Figure 100835DEST_PATH_IMAGE040
the complex number of the first and second phase is conjugated and transposed,
Figure 7611DEST_PATH_IMAGE006
representing the desired output state data, and,
Figure 287283DEST_PATH_IMAGE041
the complex number of the,
Figure 963115DEST_PATH_IMAGE042
the complex number of (a) is conjugated,
Figure 670040DEST_PATH_IMAGE043
，
Figure 64112DEST_PATH_IMAGE044
，
Figure 881895DEST_PATH_IMAGE045
is shown as
Figure 677813DEST_PATH_IMAGE011
Logical super operator
Figure 290060DEST_PATH_IMAGE046
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure 171428DEST_PATH_IMAGE047
represents: first, the
Figure 792902DEST_PATH_IMAGE011
Logical super operator
Figure 443326DEST_PATH_IMAGE046
The second in the corresponding set of Kraus matrices
Figure 492054DEST_PATH_IMAGE014
A matrix of a number of Kraus's,
Figure 595139DEST_PATH_IMAGE048
the complex number of the,
Figure 754725DEST_PATH_IMAGE049
，
Figure 525235DEST_PATH_IMAGE018
is shown as
Figure 744864DEST_PATH_IMAGE019
Logical super operator
Figure 335245DEST_PATH_IMAGE046
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure 298522DEST_PATH_IMAGE050
is shown as
Figure 923538DEST_PATH_IMAGE022
Logical super operator
Figure 314068DEST_PATH_IMAGE051
The second in the corresponding set of Kraus matrices
Figure 391746DEST_PATH_IMAGE052
A matrix of a number of Kraus's,
Figure 893134DEST_PATH_IMAGE053
the complex number of the,
Figure 372657DEST_PATH_IMAGE054
，
Figure 957526DEST_PATH_IMAGE055
representing the 1 st logical super operator
Figure 522499DEST_PATH_IMAGE028
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure 827579DEST_PATH_IMAGE056
representing the 1 st logical super operator
Figure 161608DEST_PATH_IMAGE030
The second in the corresponding set of Kraus matrices
Figure 893941DEST_PATH_IMAGE037
The number of the Kraus matrix is,
Figure 946210DEST_PATH_IMAGE057
is that
Figure 54981DEST_PATH_IMAGE058
The complex number of the,
Figure 243517DEST_PATH_IMAGE059
，
Figure 146751DEST_PATH_IMAGE035
representing the total number of all logical super operators,
Figure 686316DEST_PATH_IMAGE060
、
Figure 333198DEST_PATH_IMAGE011
、
Figure 641820DEST_PATH_IMAGE037
and
Figure 715955DEST_PATH_IMAGE038
are all positive integers.
A storage medium of the present invention stores therein instructions that, when read by a computer, cause the computer to execute a method of fault simulation of a quantum circuit according to any one of the above.
An electronic device of the present invention includes a processor and the storage medium, where the processor executes instructions in the storage medium.
Drawings
Fig. 1 is a schematic flow chart of a fault simulation method of a quantum circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a structure of a quantum circuit to be tested for failure;
FIG. 3 is a schematic structural diagram of a fault quantum circuit to be tested after eliminating a fault;
FIG. 4 is a schematic diagram of tensor shrinkage of the failure quantum circuit under test of FIG. 2;
fig. 5 is a schematic structural diagram of a fault simulation system of a quantum circuit according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, a fault simulation method for a quantum circuit according to an embodiment of the present invention includes the following steps:
s1, acquiring a super operator corresponding to the fault quantum circuit to be tested, and acquiring a Kraus matrix set corresponding to each logic super operator in the super operators;
s2, calculating the fault influence rate of the fault in the fault quantum circuit to be tested based on the input state data, the expected output state data and all Kraus matrix sets, wherein the expected output state data refers to: and when the input state data is input into the quantum circuit to be tested, which eliminates the fault, outputting the data.
Wherein, can set up input state data according to actual conditions, in the technical field of quantum computation, input state data means: the matrix corresponding to the quantum state is specifically the matrix corresponding to the quantum state, and the expected output state data is also the matrix corresponding to the quantum state.
Simulation experiment results show that the invention can simulate the fault quantum circuit with the size exceeding 5000 quantum bits, can meet the application of the NISQ era, has wide applicability, can be independently used, and can also be integrated into the currently developed automatic quantum test mode generation program for verifying and detecting the design error, the manufacturing defect and the quantum noise effect of the quantum circuit.
Optionally, in the above technical solution, the fault influence rate is:
Figure 742817DEST_PATH_IMAGE061
wherein, in the step (A),
Figure 927811DEST_PATH_IMAGE003
representing the input state data of the said device,
Figure 90939DEST_PATH_IMAGE062
to represent
Figure 601555DEST_PATH_IMAGE063
The complex number of the first and second phase is conjugated and transposed,
Figure 850133DEST_PATH_IMAGE064
representing the desired output state data, and,
Figure 838818DEST_PATH_IMAGE065
is that
Figure 122032DEST_PATH_IMAGE066
The complex number of the,
Figure 537969DEST_PATH_IMAGE067
the complex number of the,
Figure 273844DEST_PATH_IMAGE068
，
Figure 66220DEST_PATH_IMAGE069
，
Figure 203940DEST_PATH_IMAGE070
is shown as
Figure 790779DEST_PATH_IMAGE011
Logical super operator
Figure 13950DEST_PATH_IMAGE071
The total number of Kraus matrixes in the corresponding Kraus matrix set,
Figure 344437DEST_PATH_IMAGE072
represents: first, the
Figure 336664DEST_PATH_IMAGE011
Logical super operator
Figure 359984DEST_PATH_IMAGE071
The second in the corresponding set of Kraus matrices
Figure 70451DEST_PATH_IMAGE014
A matrix of a number of Kraus's,
Figure 939050DEST_PATH_IMAGE073
the complex number of (a) is conjugated,
Figure 51362DEST_PATH_IMAGE074
，
Figure 980004DEST_PATH_IMAGE075
denotes the first
Figure 177767DEST_PATH_IMAGE019
Logical super operator
Figure 850057DEST_PATH_IMAGE071
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure 816876DEST_PATH_IMAGE076
denotes the first
Figure 181998DEST_PATH_IMAGE022
Logical super operator
Figure 929374DEST_PATH_IMAGE077
The second in the corresponding set of Kraus matrices
Figure 77459DEST_PATH_IMAGE078
The number of the Kraus matrix is,
Figure 226680DEST_PATH_IMAGE079
the complex number of (a) is conjugated,
Figure 638070DEST_PATH_IMAGE080
，
Figure 669480DEST_PATH_IMAGE081
representing the 1 st logical super operator
Figure 558939DEST_PATH_IMAGE028
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure 624984DEST_PATH_IMAGE082
representing the 1 st logical super operator
Figure 4012DEST_PATH_IMAGE030
The second in the corresponding set of Kraus matrices
Figure 398085DEST_PATH_IMAGE037
The number of the Kraus matrix is,
Figure 215868DEST_PATH_IMAGE083
the complex number of the,
Figure 746206DEST_PATH_IMAGE084
，
Figure 624033DEST_PATH_IMAGE035
representing the total number of all logical super operators,
Figure 505401DEST_PATH_IMAGE085
、
Figure 126875DEST_PATH_IMAGE011
、
Figure 777299DEST_PATH_IMAGE037
and
Figure 560448DEST_PATH_IMAGE086
are all positive integers.
Because each logic super operator corresponds to the Kraus matrix setThe number of the Kraus matrixes is the same, so the Kraus matrixes are used uniformly
Figure 257008DEST_PATH_IMAGE037
And (4) showing.
The quantum circuit to be tested, namely the defective quantum circuit, is represented as a plurality of Kraus matrix sets, the quantum circuit to be tested can be coded into a tensor network with double size, the contraction calculation efficiency of the tensor network is high, the contraction of the tensor network can be calculated quickly, fault simulation can be completed in a short time, and the fault influence rate of the fault in the quantum circuit to be tested can be obtained.
The fault simulation method for the quantum circuit is described by using one embodiment as follows, and specifically includes:
s10, acquiring a Kraus matrix set corresponding to each logic super operator in the super operators of the fault quantum circuit to be tested shown in FIG. 2,
Figure 88698DEST_PATH_IMAGE087
wherein
Figure 859208DEST_PATH_IMAGE088
Representing the ith logical super operator
Figure 813257DEST_PATH_IMAGE089
Corresponding Kraus matrix set
Figure 669218DEST_PATH_IMAGE090
。
Wherein H, S, T is standard single quantum basic gate in quantum circuit, symbol "
Figure 632495DEST_PATH_IMAGE091
"is a standard controlled not gate, and is denoted as C gate, and those skilled in the art can directly determine the Kraus matrix set corresponding to each logical super operator in the super operator according to fig. 2,
Figure 991932DEST_PATH_IMAGE092
logic super operator, table for polarization noiseIndicating a fault in a quantum circuit to be tested, the fault
Figure 382462DEST_PATH_IMAGE092
Can be expressed as:
Figure 460139DEST_PATH_IMAGE093
；
s11, determining input state data and desired output state data:
inputting status data
Figure 227107DEST_PATH_IMAGE094
Comprises the following steps:
Figure 706630DEST_PATH_IMAGE095
expected output of state data
Figure 268061DEST_PATH_IMAGE096
Comprises the following steps:
Figure 833035DEST_PATH_IMAGE097
；
the acquisition process of the expected output state data comprises the following steps: and (3) eliminating the fault of the quantum circuit to be tested shown in the figure 2 to obtain the quantum circuit shown in the figure 3, and inputting the input state data into the quantum circuit shown in the figure 3 to obtain the expected output state data.
S12, use of
Figure 138114DEST_PATH_IMAGE098
And calculating the tensor network contraction as shown in fig. 4, namely, the fault influence rate.
And whether the fault quantum circuit to be tested can be used or not can be judged according to the fault influence rate. The value range of the fault influence rate is 0-1, 1 represents no influence, 0 represents the maximum influence, and when the fault influence rate is 0, the quantum circuit to be tested completely cannot be used.
In the foregoing embodiments, although the steps are numbered as S1, S2, etc., but only the specific embodiments given in this application are provided, and those skilled in the art may adjust the execution sequence of S1, S2, etc. according to the actual situation, which is also within the protection scope of the present invention, it is understood that some embodiments may include some or all of the above embodiments.
As shown in fig. 5, a fault simulation system 200 of a quantum circuit according to an embodiment of the present invention includes an obtaining module 210 and a calculating module 220;
the obtaining module 210 is configured to: acquiring a super operator corresponding to a fault quantum circuit to be tested, and acquiring a Kraus matrix set corresponding to each logic super operator in the super operators;
the calculation module 220 is configured to: calculating the fault influence rate of the fault in the to-be-tested fault quantum circuit based on input state data, expected output state data and all Kraus matrix sets, wherein the expected output state data refers to: and when the input state data is input into the quantum circuit to be tested with the fault eliminated, outputting the data.
Simulation experiment results show that the invention can simulate the fault quantum circuit with the size exceeding 5000 quantum bits, can meet the application of the NISQ era, has wide applicability, can be independently used, and can also be integrated into the currently developed automatic quantum test mode generation program for verifying and detecting the design error, the manufacturing defect and the quantum noise effect of the quantum circuit.
Optionally, in the above technical solution, the fault influence rate is:
Figure 472144DEST_PATH_IMAGE099
wherein, in the step (A),
Figure 204476DEST_PATH_IMAGE003
representing the input state data of the said device,
Figure 256746DEST_PATH_IMAGE062
to represent
Figure 99937DEST_PATH_IMAGE063
The complex number of the first and second phase is conjugated and transposed,
Figure 554052DEST_PATH_IMAGE064
representing the desired output state data, and,
Figure 457286DEST_PATH_IMAGE100
is that
Figure 996852DEST_PATH_IMAGE101
The complex number of the,
Figure 643734DEST_PATH_IMAGE102
the complex number of the,
Figure 952355DEST_PATH_IMAGE103
，
Figure 26491DEST_PATH_IMAGE104
，
Figure 787773DEST_PATH_IMAGE105
denotes the first
Figure 238346DEST_PATH_IMAGE011
Logical super operator
Figure 401474DEST_PATH_IMAGE106
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure 646511DEST_PATH_IMAGE107
represents: first, the
Figure 160669DEST_PATH_IMAGE011
Logical super operator
Figure 149353DEST_PATH_IMAGE108
The second in the corresponding set of Kraus matrices
Figure 166988DEST_PATH_IMAGE014
A matrix of a number of Kraus's,
Figure 848505DEST_PATH_IMAGE109
the complex number of the,
Figure 584380DEST_PATH_IMAGE110
，
Figure 376755DEST_PATH_IMAGE111
is shown as
Figure 248896DEST_PATH_IMAGE112
Logical super operator
Figure 101315DEST_PATH_IMAGE113
The total number of Kraus matrixes in the corresponding Kraus matrix set,
Figure 324486DEST_PATH_IMAGE114
is shown as
Figure 654973DEST_PATH_IMAGE022
Logical super operator
Figure 647200DEST_PATH_IMAGE023
The second in the corresponding set of Kraus matrices
Figure 670519DEST_PATH_IMAGE115
A matrix of a number of Kraus's,
Figure 115407DEST_PATH_IMAGE116
the complex number of the,
Figure 984006DEST_PATH_IMAGE117
，
Figure 361898DEST_PATH_IMAGE118
representing the 1 st logical super operator
Figure 290539DEST_PATH_IMAGE028
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure 488303DEST_PATH_IMAGE119
representing the 1 st logical super operator
Figure 160592DEST_PATH_IMAGE030
The second in the corresponding set of Kraus matrices
Figure 127411DEST_PATH_IMAGE037
A matrix of a number of Kraus's,
Figure 430217DEST_PATH_IMAGE120
the complex number of the,
Figure 505489DEST_PATH_IMAGE121
，
Figure 856836DEST_PATH_IMAGE035
representing the total number of all logical super-operators,
Figure 802795DEST_PATH_IMAGE122
、
Figure 542081DEST_PATH_IMAGE011
、
Figure 448857DEST_PATH_IMAGE037
and
Figure 462950DEST_PATH_IMAGE086
are all positive integers.
The quantum circuit to be tested, namely the defective quantum circuit, is represented as a plurality of Kraus matrix sets, the quantum circuit to be tested can be coded into a tensor network with double size, the contraction calculation efficiency of the tensor network is high, the contraction of the tensor network can be calculated quickly, fault simulation can be completed in a short time, and the fault influence rate of the fault in the quantum circuit to be tested can be obtained.
The above steps for realizing the corresponding functions of each parameter and each unit module in the fault simulation system 200 of a quantum circuit according to the present invention can refer to each parameter and step in the above embodiments of the fault simulation method of a quantum circuit, which are not described herein again.
In an embodiment of the present invention, the storage medium stores instructions, and when a computer reads the instructions, the computer is caused to execute any one of the above-described method for simulating a fault of a quantum circuit.
The electronic device of the embodiment of the invention comprises a processor and the storage medium, wherein the processor executes instructions in the storage medium, and the electronic device can be a computer, a mobile phone, a tablet computer or the like.
As will be appreciated by one skilled in the art, the present invention may be embodied as a system, method or computer program product.
Accordingly, the present disclosure may be embodied in the form of: may be embodied entirely in hardware, entirely in software (including firmware, resident software, micro-code, etc.) or in a combination of hardware and software, and may be referred to herein generally as a "circuit," module "or" system. Furthermore, in some embodiments, the invention may also be embodied in the form of a computer program product in one or more computer-readable media having computer-readable program code embodied in the medium.
Any combination of one or more computer-readable media may be employed. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims (4)

1. A fault simulation method of a quantum circuit is characterized by comprising the following steps:
acquiring a super operator corresponding to a fault quantum circuit to be tested, and acquiring a Kraus matrix set corresponding to each logic super operator in the super operators;
calculating a fault influence rate of a fault in the fault quantum circuit to be tested based on input state data, expected output state data and all Kraus matrix sets, wherein the expected output state data refers to: when the input state data is input into the quantum circuit to be tested with the fault eliminated, the output data;
the fault influence rate is as follows:
Figure DEST_PATH_IMAGE002
wherein, in the process,
Figure DEST_PATH_IMAGE004
representing the input state data of the said device,
Figure DEST_PATH_IMAGE006
to represent
Figure DEST_PATH_IMAGE008
The complex number of the first and second phase is conjugated and transposed,
Figure DEST_PATH_IMAGE009
representing the desired output state data, and,
Figure DEST_PATH_IMAGE011
is that
Figure DEST_PATH_IMAGE013
The complex number of the,
Figure DEST_PATH_IMAGE015
is that
Figure DEST_PATH_IMAGE017
The complex number of (a) is conjugated,
Figure DEST_PATH_IMAGE019
，
Figure DEST_PATH_IMAGE021
，
Figure DEST_PATH_IMAGE023
is shown as
Figure DEST_PATH_IMAGE025
Logical super operator
Figure DEST_PATH_IMAGE027
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure DEST_PATH_IMAGE029
represents: first, the
Figure DEST_PATH_IMAGE025A
Logical super operator
Figure DEST_PATH_IMAGE030
The second in the corresponding set of Kraus matrices
Figure DEST_PATH_IMAGE032
A matrix of a number of Kraus's,
Figure DEST_PATH_IMAGE034
is that
Figure DEST_PATH_IMAGE035
The complex number of the,
Figure DEST_PATH_IMAGE037
，
Figure DEST_PATH_IMAGE039
is shown as
Figure DEST_PATH_IMAGE041
Logical super operator
Figure DEST_PATH_IMAGE042
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure DEST_PATH_IMAGE044
is shown as
Figure DEST_PATH_IMAGE045
Logical super operator
Figure DEST_PATH_IMAGE047
The second in the corresponding set of Kraus matrices
Figure DEST_PATH_IMAGE048
A matrix of a number of Kraus's,
Figure DEST_PATH_IMAGE050
is that
Figure DEST_PATH_IMAGE051
The complex number of the,
Figure DEST_PATH_IMAGE053
，
Figure DEST_PATH_IMAGE055
representing the 1 st logical super operator
Figure DEST_PATH_IMAGE057
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure DEST_PATH_IMAGE059
representing the 1 st logical super operator
Figure DEST_PATH_IMAGE061
The second in the corresponding set of Kraus matrices
Figure DEST_PATH_IMAGE062
A matrix of a number of Kraus's,
Figure DEST_PATH_IMAGE064
is that
Figure DEST_PATH_IMAGE065
The complex number of the,
Figure DEST_PATH_IMAGE067
，
Figure DEST_PATH_IMAGE068
representing the total number of all logical super operators,
Figure DEST_PATH_IMAGE023A
、
Figure DEST_PATH_IMAGE025AA
、
Figure DEST_PATH_IMAGE069
and
Figure DEST_PATH_IMAGE070
are all positive integers.
2. A fault simulation system of a quantum circuit is characterized by comprising an acquisition module and a calculation module;
the acquisition module is used for: acquiring a super operator corresponding to a fault quantum circuit to be tested, and acquiring a Kraus matrix set corresponding to each logic super operator in the super operators;
the calculation module is configured to: calculating a fault influence rate of a fault in the fault quantum circuit to be tested based on input state data, expected output state data and all Kraus matrix sets, wherein the expected output state data refers to: when the input state data is input into the quantum circuit to be tested, the fault of which is eliminated, the data is output;
the fault influence rate is as follows:
Figure DEST_PATH_IMAGE002A
wherein, in the step (A),
Figure DEST_PATH_IMAGE004A
representing the input state data of the said device,
Figure DEST_PATH_IMAGE071
to represent
Figure DEST_PATH_IMAGE008A
The complex number of the first and second phase is conjugated and transposed,
Figure DEST_PATH_IMAGE072
representing the data of the desired output state,
Figure DEST_PATH_IMAGE011A
is that
Figure DEST_PATH_IMAGE013A
The complex number of the,
Figure DEST_PATH_IMAGE015A
is that
Figure DEST_PATH_IMAGE017A
The complex number of the,
Figure DEST_PATH_IMAGE073
，
Figure 687603DEST_PATH_IMAGE021
，
Figure DEST_PATH_IMAGE023AA
denotes the first
Figure DEST_PATH_IMAGE025AAA
Logical super operator
Figure DEST_PATH_IMAGE042A
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure DEST_PATH_IMAGE074
represents: first, the
Figure DEST_PATH_IMAGE025AAAA
Logical super operator
Figure DEST_PATH_IMAGE030A
The second in the corresponding set of Kraus matrices
Figure DEST_PATH_IMAGE075
A matrix of a number of Kraus's,
Figure DEST_PATH_IMAGE076
is that
Figure DEST_PATH_IMAGE035A
The complex number of the,
Figure DEST_PATH_IMAGE077
，
Figure 572120DEST_PATH_IMAGE039
denotes the first
Figure DEST_PATH_IMAGE078
Logical super operator
Figure DEST_PATH_IMAGE042AA
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure DEST_PATH_IMAGE079
denotes the first
Figure DEST_PATH_IMAGE080
Logical super operator
Figure 335546DEST_PATH_IMAGE047
The second in the corresponding set of Kraus matrices
Figure DEST_PATH_IMAGE081
A matrix of a number of Kraus's,
Figure 653393DEST_PATH_IMAGE050
is that
Figure 936607DEST_PATH_IMAGE051
The complex number of the,
Figure DEST_PATH_IMAGE053A
，
Figure DEST_PATH_IMAGE082
representing the 1 st logical super operator
Figure 477178DEST_PATH_IMAGE057
The total number of the Kraus matrixes in the corresponding Kraus matrix set,
Figure DEST_PATH_IMAGE083
representing the 1 st logical super operator
Figure 540949DEST_PATH_IMAGE061
The second in the corresponding set of Kraus matrices
Figure DEST_PATH_IMAGE084
A matrix of a number of Kraus's,
Figure 21740DEST_PATH_IMAGE064
is that
Figure 284095DEST_PATH_IMAGE065
The complex number of the,
Figure DEST_PATH_IMAGE067A
，
Figure DEST_PATH_IMAGE085
representing the total number of all logical super-operators,
Figure DEST_PATH_IMAGE086
、
Figure DEST_PATH_IMAGE087
、
Figure DEST_PATH_IMAGE088
and
Figure DEST_PATH_IMAGE089
are all positive integers.
3. A storage medium having stored therein instructions which, when read by a computer, cause the computer to execute a fault simulation method of a quantum circuit according to claim 1.
4. An electronic device comprising the storage medium of claim 3 and a processor, the processor executing instructions in the storage medium.
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