CN114429095B - Fault simulation method and system of quantum circuit, storage medium and electronic device - Google Patents
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Abstract
本发明涉及量子电路故障仿真技术领域,尤其涉及一种量子电路的故障仿真方法、系统、存储介质和电子设备,方法包括:获取待测试故障量子电路所对应的超算子,并获取所述超算子中的每个逻辑超算子所分别对应的Kraus矩阵集合,基于输入状态数据、期望输出状态数据以及所有的Kraus矩阵集合,计算所述待测试故障量子电路中的故障的故障影响率,通过仿真实验结果表明,本发明能够模拟大小超过5000个量子比特的故障量子电路,能够满足NISQ时代的应用,而且适用性广泛,既可以独立使用,也可以集成到当前开发的量子自动测试模式生成程序中,用于验证和检测量子电路的设计错误、制造缺陷和量子噪声效应。
The invention relates to the technical field of quantum circuit fault simulation, in particular to a fault simulation method, system, storage medium and electronic device for a quantum circuit. The Kraus matrix set corresponding to each logical super-operator in the operator, based on the input state data, the expected output state data and all the Kraus matrix sets, calculate the failure influence rate of the failure in the fault quantum circuit to be tested, The simulation experiment results show that the invention can simulate the fault quantum circuit with a size of more than 5000 qubits, can meet the application in the NISQ era, and has a wide range of applicability, which can be used independently or integrated into the currently developed quantum automatic test mode generation. A program used to verify and detect design errors, manufacturing defects, and quantum noise effects in quantum circuits.
Description
技术领域technical field
本发明涉及量子电路故障仿真技术领域,尤其涉及一种量子电路的故障仿真方法、系统、存储介质和电子设备。The invention relates to the technical field of quantum circuit fault simulation, in particular to a quantum circuit fault simulation method, system, storage medium and electronic device.
背景技术Background technique
在物理构建电路之前,仿真在数字电路验证、测试开发、设计调试和诊断中起着重要作用。具体来说,故障仿真是对有故障的数字电路进行仿真。其主要有两个目的:一是无故障(逻辑)仿真,帮助设计者验证数字电路的设计是否符合预期的功能描述;二是确定测试模式在检测感兴趣的故障时的效率,此类模式通常由自动测试模式生成器(ATPG)生成。现在故障仿真可以有效地应用于大规模集成电路,并已发展成电子设计自动化(EDA)的标准技术。Simulation plays an important role in digital circuit verification, test development, design debugging, and diagnostics before a circuit is physically built. Specifically, fault simulation is the simulation of a faulty digital circuit. It has two main purposes: one is fault-free (logic) simulation, which helps designers verify that the design of digital circuits conforms to the expected functional description; Generated by Automatic Test Pattern Generator (ATPG). Fault simulation can now be effectively applied to large-scale integrated circuits and has developed into a standard technique for electronic design automation (EDA).
然而,目前在量子计算中,物理学家通常通过实验构建设计的量子电路,然后估计它们在存在量子故障时的性能。其中,量子故障不仅包括与经典故障一样的量子电路的设计错误和制造缺陷,还包括来自周围环境的量子噪声,而且,在当前的嘈杂中型量子(NISQ)时代中量子噪声是不可避免的。例如,研究者实现了一个具有四个量子比特和四个受控量子逻辑门的电路,用于HHL算法的实验(HHL算法可以在量子计算机上指数加速求解线性方程组)。在电路性能测试中,三种不同状态被输入到电路中,实际输出状态与理想输出状态相比的保真度分别为99.3%、82.5%和83.6%。谷歌也使用类似的方法来确认量子霸权(即超越经典计算),以0.2%的保真度对53量子比特的量子电路进行采样。Currently in quantum computing, however, physicists typically experimentally build designed quantum circuits and then estimate their performance in the presence of quantum glitches. Among them, quantum faults include not only design errors and manufacturing defects of quantum circuits like classical faults, but also quantum noise from the surrounding environment, which is unavoidable in the current Noisy Intermediate Scale Quantum (NISQ) era. For example, the researchers implemented a circuit with four qubits and four controlled quantum logic gates for use in experiments with the HHL algorithm (the HHL algorithm can solve linear equations exponentially faster on a quantum computer). In the circuit performance test, three different states were input into the circuit, and the fidelity of the actual output state compared with the ideal output state was 99.3%, 82.5% and 83.6%, respectively. Google also used a similar approach to confirm quantum supremacy (i.e. beyond classical computing), sampling a 53-qubit quantum circuit with 0.2% fidelity.
显然,由于实验实施量子电路的昂贵资源和严格条件(例如环境温度必须接近绝对零度)以及读取量子状态的不确定性,在物理构建它们之前对量子电路(在经典计算机上)进行故障仿真是有帮助的并且更具有性价比。另一方面,将经典电路的现有故障仿真方法直接推广到量子电路上可以想象是不会成功。一个主要原因是量子故障仿真通常是定量的,而不是经典故障仿真中定性的:量子电路的输入/输出是复数的向量或矩阵,而经典电路的输入/输出是布尔值,即0或1。这一根本区别需要以新的方式构建量子故障仿真。Clearly, due to the expensive resources and stringent conditions of experimentally implementing quantum circuits (e.g. the ambient temperature must be close to absolute zero) and the uncertainty of reading quantum states, failure simulation of quantum circuits (on a classical computer) before physically building them is Helpful and more cost-effective. On the other hand, it is conceivably unsuccessful to directly generalize existing fault simulation methods for classical circuits to quantum circuits. A major reason is that quantum fault simulations are often quantitative, rather than qualitative in classical fault simulations: the inputs/outputs of quantum circuits are vectors or matrices of complex numbers, while the inputs/outputs of classical circuits are Boolean values, i.e. 0 or 1. This fundamental distinction requires building quantum fault simulations in new ways.
目前主要有两种仿真量子故障的方法。一是针对特定设计错误(例如单个量子门缺失)和制造缺陷(例如实际制造出的量子CNOT门)的基于矢量的仿真方法。二是针对量子噪声引起的故障,提出了基于密度矩阵的仿真方法,并嵌入到几乎所有目前流行的量子电路编程平台中,如IBM的Qiskit、微软的Q#和谷歌的Cirq。它的策略是通过在每个感兴趣的故障的数学模型中直接应用矩阵运算来更新存储的量子态的密度矩阵。There are currently two main methods for simulating quantum faults. One is a vector-based simulation approach for specific design errors (e.g. missing a single quantum gate) and fabrication defects (e.g. actually fabricated quantum CNOT gates). Second, for the failure caused by quantum noise, a simulation method based on density matrix is proposed and embedded in almost all the currently popular quantum circuit programming platforms, such as IBM's Qiskit, Microsoft's Q# and Google's Cirq. Its strategy is to update the density matrix of stored quantum states by directly applying matrix operations in the mathematical model of each fault of interest.
不幸的是,由于状态空间的维数随着量子比特(qubits)的数量呈指数增长,目前 上述的仿真方法的可扩展性(≤10 qubits)远未满足NISQ(NISQ为Noisy Intermediate- Scale Quantum的缩写,表示:含噪声的中型量子)时代的应用(量子电路的比特数≥ 50qubits和的复数矩阵)。Unfortunately, since the dimensionality of the state space grows exponentially with the number of quantum bits (qubits), the scalability (≤10 qubits) of the above simulation methods is far from NISQ (NISQ is a Noisy Intermediate-Scale Quantum Abbreviation for: Noisy medium quantum) applications in the era (quantum circuits with bits ≥ 50qubits and complex matrix).
发明内容SUMMARY OF THE INVENTION
本发明所要解决的技术问题是针对现有技术的不足,提供了一种量子电路的故障仿真方法、系统、存储介质和电子设备。The technical problem to be solved by the present invention is to provide a fault simulation method, system, storage medium and electronic device for a quantum circuit aiming at the deficiencies of the prior art.
本发明的一种量子电路的故障仿真方法的技术方案如下:The technical scheme of the fault simulation method of a quantum circuit of the present invention is as follows:
获取待测试故障量子电路所对应的超算子,并获取所述超算子中的每个逻辑超算子所分别对应的Kraus矩阵集合;Obtain the super-operator corresponding to the fault quantum circuit to be tested, and obtain the Kraus matrix set corresponding to each logical super-operator in the super-operator;
基于输入状态数据、期望输出状态数据以及所有的Kraus矩阵集合,计算所述待测试故障量子电路中的故障的故障影响率,其中,所述期望输出状态数据指:将所述输入状态数据输入已消除故障的待测试故障量子电路时,所输出的数据。Based on the input state data, the expected output state data, and all the Kraus matrix sets, the failure influence rate of the failure in the fault quantum circuit to be tested is calculated, wherein the expected output state data refers to: inputting the input state data into the The data output when the faulty quantum circuit to be tested is eliminated.
本发明的一种量子电路的故障仿真方法的有益效果如下:The beneficial effects of the fault simulation method of a quantum circuit of the present invention are as follows:
通过仿真实验结果表明,本发明能够模拟大小超过5000个量子比特的故障量子电路,能够满足NISQ时代的应用,而且适用性广泛,既可以独立使用,也可以集成到当前开发的量子自动测试模式生成程序中,用于验证和检测量子电路的设计错误、制造缺陷和量子噪声效应。The simulation results show that the invention can simulate the fault quantum circuit with a size of more than 5000 qubits, can meet the application in the NISQ era, and has a wide range of applicability, which can be used independently or integrated into the currently developed quantum automatic test mode generation A program used to verify and detect design errors, manufacturing defects, and quantum noise effects in quantum circuits.
在上述方案的基础上,本发明的一种量子电路的故障仿真方法还可以做如下改进。On the basis of the above solution, the fault simulation method of a quantum circuit of the present invention can also be improved as follows.
进一步,所述计算所述待测试故障量子电路中的故障的故障影响率,包括:Further, the calculating the fault influence rate of the fault in the fault quantum circuit to be tested includes:
所述故障影响率为:,其中,表示所述输入状态数据,表示的复数共轭转置,表示所述期望输出状 态数据,的复数共轭,的复数共轭, ,表示第个逻辑超算子所对应的Kraus矩阵集合中Kraus矩阵的总 数量,表示:第个逻辑超算子对应的Kraus矩阵集合中的第个Kraus矩阵, 是的复数共轭,,表示第个逻辑超算子 所对应的Kraus矩阵集合中Kraus矩阵的总数量,表示第个逻辑超算子对应的 Kraus矩阵集合中的第个Kraus矩阵,的复数共轭,,表示第1个逻辑超算子所对应的Kraus矩阵集合中 Kraus矩阵的总数量,表示第1个逻辑超算子对应的Kraus矩阵集合中的第个 Kraus矩阵,是的复数共轭,,表示所有逻辑超算子的总数量,、 、和均为正整数。 The failure impact rate is: ,in, represents the input state data, express The complex conjugate transpose of , represents the desired output status data, The complex conjugate of , The complex conjugate of , , means the first logical superoperator The total number of Kraus matrices in the corresponding Kraus matrix set, means: the first logical superoperator The first in the corresponding set of Kraus matrices a Kraus matrix, Yes The complex conjugate of , , means the first logical superoperator The total number of Kraus matrices in the corresponding Kraus matrix set, means the first logical superoperator The first in the corresponding set of Kraus matrices a Kraus matrix, The complex conjugate of , , represents the first logical superoperator The total number of Kraus matrices in the corresponding Kraus matrix set, represents the first logical superoperator The first in the corresponding set of Kraus matrices a Kraus matrix, Yes The complex conjugate of , , represents the total number of all logical superoperators, , , and All are positive integers.
本发明的一种量子电路的故障仿真系统的技术方案如下:The technical scheme of the fault simulation system of a quantum circuit of the present invention is as follows:
包括获取模块和计算模块;Including acquisition module and calculation module;
所述获取模块用于:获取待测试故障量子电路所对应的超算子,并获取所述超算子中的每个逻辑超算子所分别对应的Kraus矩阵集合;The acquisition module is used for: acquiring the super-operator corresponding to the fault quantum circuit to be tested, and acquiring the Kraus matrix set corresponding to each logical super-operator in the super-operator;
所述计算模块用于:基于输入状态数据、期望输出状态数据以及所有的Kraus矩阵集合,计算所述待测试故障量子电路中的故障的故障影响率,其中,所述期望输出状态数据指:将所述输入状态数据输入已消除故障的待测试故障量子电路时,所输出的数据。The calculation module is used for: based on the input state data, the expected output state data and all the Kraus matrix sets, to calculate the failure influence rate of the failure in the to-be-tested failure quantum circuit, wherein the expected output state data refers to: The input state data is the output data when the faulty quantum circuit to be tested whose fault has been eliminated is input.
本发明的一种量子电路的故障仿真系统的有益效果如下:The beneficial effects of the fault simulation system of a quantum circuit of the present invention are as follows:
通过将待测试故障量子电路即有缺陷的量子电路表示为多个Kraus矩阵集合,能够编码到在一个双倍大小的张量网络中,张量网络的收缩计算效率高,能够快速计算张量网络收缩,从而能够在很短的时间内完成故障仿真,即得到待测试故障量子电路中的故障的故障影响率。By representing the faulty quantum circuit to be tested, that is, the defective quantum circuit, as a set of multiple Kraus matrices, it can be encoded into a double-sized tensor network. The shrinkage of the tensor network has high computational efficiency and can quickly calculate the tensor network Therefore, the fault simulation can be completed in a very short time, that is, the fault influence rate of the fault in the fault quantum circuit to be tested can be obtained.
在上述方案的基础上,本发明的一种量子电路的故障仿真系统还可以做如下改进。On the basis of the above solution, the fault simulation system of a quantum circuit of the present invention can also be improved as follows.
进一步,所述故障影响率为:, 其中,表示所述输入状态数据,的复数共轭转置,表示所述 期望输出状态数据,的复数共轭,的复数共轭,,,表示第个逻辑超算子所对应的Kraus 矩阵集合中Kraus矩阵的总数量,表示:第个逻辑超算子对应的Kraus矩阵集合中 的第个Kraus矩阵,的复数共轭,, 表示第个逻辑超算子所对应的Kraus矩阵集合中Kraus矩阵的总数量,表示第 个逻辑超算子对应的Kraus矩阵集合中的第个Kraus矩阵,的复数共轭,,表示第1个逻辑超算子所对应的Kraus矩阵集合中 Kraus矩阵的总数量,表示第1个逻辑超算子对应的Kraus矩阵集合中的第个 Kraus矩阵,是的复数共轭,,表示所有逻辑超算子的总数量,、 、和均为正整数。 Further, the failure influence rate is: , in, represents the input state data, The complex conjugate transpose of , represents the desired output status data, The complex conjugate of , The complex conjugate of , , , means the first logical superoperator The total number of Kraus matrices in the corresponding Kraus matrix set, means: the first logical superoperator The first in the corresponding set of Kraus matrices a Kraus matrix, The complex conjugate of , , means the first logical superoperator The total number of Kraus matrices in the corresponding Kraus matrix set, means the first logical superoperator The first in the corresponding set of Kraus matrices a Kraus matrix, The complex conjugate of , , represents the first logical superoperator The total number of Kraus matrices in the corresponding Kraus matrix set, represents the first logical superoperator The first in the corresponding set of Kraus matrices a Kraus matrix, Yes The complex conjugate of , , represents the total number of all logical superoperators, , , and All are positive integers.
本发明的一种存储介质,所述存储介质中存储有指令,当计算机读取所述指令时,使所述计算机执行上述任一项所述的一种量子电路的故障仿真方法。According to a storage medium of the present invention, instructions are stored in the storage medium, and when a computer reads the instructions, the computer is made to execute any one of the above-mentioned methods for simulating a fault of a quantum circuit.
本发明的一种电子设备,包括处理器和上述的存储介质,所述处理器执行所述存储介质中的指令。An electronic device of the present invention includes a processor and the above-mentioned storage medium, wherein the processor executes the instructions in the storage medium.
附图说明Description of drawings
图1为本发明实施例的一种量子电路的故障仿真方法的流程示意图;1 is a schematic flowchart of a method for simulating a fault of a quantum circuit according to an embodiment of the present invention;
图2为待测试故障量子电路的结构示意图;Fig. 2 is the structural schematic diagram of the fault quantum circuit to be tested;
图3为消除故障后的待测试故障量子电路的结构示意图;Fig. 3 is the structural schematic diagram of the quantum circuit to be tested after the fault is eliminated;
图4为为图2的待测试故障量子电路的张量收缩示意图;4 is a schematic diagram of tensor contraction of the faulty quantum circuit to be tested of FIG. 2;
图5为本发明实施例的一种量子电路的故障仿真系统的结构示意图。FIG. 5 is a schematic structural diagram of a fault simulation system for a quantum circuit according to an embodiment of the present invention.
具体实施方式Detailed ways
如图1所示,本发明实施例的一种量子电路的故障仿真方法,包括如下步骤:As shown in FIG. 1 , a method for simulating a fault of a quantum circuit according to an embodiment of the present invention includes the following steps:
S1、获取待测试故障量子电路所对应的超算子,并获取所述超算子中的每个逻辑超算子所分别对应的Kraus矩阵集合;S1, obtain the superoperator corresponding to the fault quantum circuit to be tested, and obtain the Kraus matrix set corresponding to each logical superoperator in the superoperator;
S2、基于输入状态数据、期望输出状态数据以及所有的Kraus矩阵集合,计算所述待测试故障量子电路中的故障的故障影响率,其中,所述期望输出状态数据指:将所述输入状态数据输入已消除故障的待测试故障量子电路时,所输出的数据。S2. Calculate the failure influence rate of the failure in the to-be-tested failure quantum circuit based on the input state data, the expected output state data, and all the Kraus matrix sets, wherein the expected output state data refers to: the input state data The output data when the faulty quantum circuit to be tested with the fault removed is input.
其中,可根据实际情况设置输入状态数据,在量子计算的技术领域内,输入状态数据指:量子状态对应的矩阵,期望输出状态数据具体也为量子状态对应的矩阵。Among them, the input state data can be set according to the actual situation. In the technical field of quantum computing, the input state data refers to the matrix corresponding to the quantum state, and the expected output state data is also the matrix corresponding to the quantum state.
通过仿真实验结果表明,本发明能够模拟大小超过5000个量子比特的故障量子电路,能够满足NISQ时代的应用,而且适用性广泛,既可以独立使用,也可以集成到当前开发的量子自动测试模式生成程序中,用于验证和检测量子电路的设计错误、制造缺陷和量子噪声效应。The simulation results show that the invention can simulate the fault quantum circuit with a size of more than 5000 qubits, can meet the application in the NISQ era, and has a wide range of applicability, which can be used independently or integrated into the currently developed quantum automatic test mode generation A program used to verify and detect design errors, manufacturing defects, and quantum noise effects in quantum circuits.
可选地,在上述技术方案中,所述故障影响率为:,其中,表示所述输入状态 数据,表示的复数共轭转置,表示所述期望输出状态数据,是的 复数共轭,的复数共轭,,,表 示第个逻辑超算子所对应的Kraus矩阵集合中Kraus矩阵的总数量,表示:第个 逻辑超算子对应的Kraus矩阵集合中的第个Kraus矩阵, 的复数共轭,,表示第个逻辑超算子所对应的Kraus矩阵 集合中Kraus矩阵的总数量,表示第个逻辑超算子对应的Kraus矩阵集合中的第个Kraus矩阵,的复数共轭,,表示第1个逻辑 超算子所对应的Kraus矩阵集合中Kraus矩阵的总数量,表示第1个逻辑超算子对 应的Kraus矩阵集合中的第个Kraus矩阵,的复数共轭,,表示所 有逻辑超算子的总数量,、、和均为正整数。 Optionally, in the above technical solution, the failure impact rate is: ,in, represents the input state data, express The complex conjugate transpose of , represents the desired output status data, Yes The complex conjugate of , The complex conjugate of , , , means the first logical superoperator The total number of Kraus matrices in the corresponding Kraus matrix set, means: the first logical superoperator The first in the corresponding set of Kraus matrices a Kraus matrix, The complex conjugate of , , means the first logical superoperator The total number of Kraus matrices in the corresponding Kraus matrix set, means the first logical superoperator The first in the corresponding set of Kraus matrices a Kraus matrix, The complex conjugate of , , represents the first logical superoperator The total number of Kraus matrices in the corresponding Kraus matrix set, represents the first logical superoperator The first in the corresponding set of Kraus matrices a Kraus matrix, The complex conjugate of , , represents the total number of all logical superoperators, , , and All are positive integers.
由于每个逻辑超算子对应的Kraus矩阵集合中的Kraus矩阵的数量相同,故统一用表示。 Since the number of Kraus matrices in the Kraus matrix set corresponding to each logical superoperator is the same, it is unified to use express.
通过将待测试故障量子电路即有缺陷的量子电路表示为多个Kraus矩阵集合,能够编码到在一个双倍大小的张量网络中,张量网络的收缩计算效率高,能够快速计算张量网络收缩,从而能够在很短的时间内完成故障仿真,即得到待测试故障量子电路中的故障的故障影响率。By representing the faulty quantum circuit to be tested, that is, the defective quantum circuit, as a set of multiple Kraus matrices, it can be encoded into a double-sized tensor network. The shrinkage of the tensor network has high computational efficiency and can quickly calculate the tensor network Therefore, the fault simulation can be completed in a very short time, that is, the fault influence rate of the fault in the fault quantum circuit to be tested can be obtained.
通过如下一个实施例,对本申请的一种量子电路的故障仿真方法进行说明,具体包括:A method for simulating a fault of a quantum circuit of the present application will be described through the following embodiment, which specifically includes:
S10、获取图2所示的待测试故障量子电路的超算子中每个逻辑超算子对应的 Kraus矩阵集合,,其中表示第i个 逻辑超算子所对应的Kraus矩阵集合。 S10. Obtain the Kraus matrix set corresponding to each logical superoperator in the superoperator of the fault quantum circuit to be tested shown in FIG. 2, ,in represents the ith logical superoperator The corresponding Kraus matrix set .
其中,H、S、T为量子电路中的标准单量子基本门,符号“”为标准受控非门,记做 C门,本领域技术人员可根据图2直接确定超算子中每个逻辑超算子对应的Kraus矩阵集合,为极化噪音的逻辑超算子,表示待测试故障量子电路中的故障,该故障可表示 为:; Among them, H, S, T are standard single quantum fundamental gates in quantum circuits, and the symbol " " is a standard controlled NOT gate, denoted as C gate, those skilled in the art can directly determine the Kraus matrix set corresponding to each logical superoperator in the superoperator according to Fig. 2, is the logical superoperator of polarization noise, representing the fault in the fault quantum circuit to be tested, the fault can be expressed as: ;
S11、确定输入状态数据和期望输出状态数据:S11. Determine the input state data and the expected output state data:
输入状态数据为:,期望输出状态数据为:; Enter status data for: , expecting output status data for: ;
期望输出状态数据的获取过程为:将图2所示的待测试故障量子电路的故障进行消除,得到图3所示的量子电路,将输入状态数据输入图3所述的量子电路,得到期望输出状态数据。The acquisition process of the expected output state data is as follows: eliminate the fault of the quantum circuit to be tested shown in Figure 2 to obtain the quantum circuit shown in Figure 3, input the input state data into the quantum circuit described in Figure 3, and obtain the expected output status data.
S12、利用,计算如图4所示 中的张量网络收缩,即为故障影响率。 S12. Use , calculate the shrinkage of the tensor network as shown in Figure 4, which is the failure impact rate.
根据故障影响率能够用来判断待测试故障量子电路是否可以使用。其中,故障影响率的取值范围为0~1,1表示无影响,0表示影响最大,故障影响率为0时,表示完全待测试故障量子电路完全不能用。According to the fault influence rate, it can be used to judge whether the fault quantum circuit to be tested can be used. Among them, the value range of the fault influence rate is 0~1, 1 means no influence, 0 means the greatest influence, and when the fault influence rate is 0, it means that the fault quantum circuit to be tested is completely unusable.
在上述各实施例中,虽然对步骤进行了编号S1、S2等,但只是本申请给出的具体实施例,本领域的技术人员可根据实际情况调整S1、S2等的执行顺序,此也在本发明的保护范围内,可以理解,在一些实施例中,可以包含如上述各实施方式中的部分或全部。In the above embodiments, although the steps are numbered S1, S2, etc., they are only specific embodiments given in this application. Those skilled in the art can adjust the execution order of S1, S2, etc. according to the actual situation. Within the protection scope of the present invention, it can be understood that in some embodiments, some or all of the above-mentioned embodiments may be included.
如图5所示,本发明实施例的一种量子电路的故障仿真系统200,包括获取模块210和计算模块220;As shown in FIG. 5 , a
所述获取模块210用于:获取待测试故障量子电路所对应的超算子,并获取所述超算子中的每个逻辑超算子所分别对应的Kraus矩阵集合;The obtaining
所述计算模块220用于:基于输入状态数据、期望输出状态数据以及所有的Kraus矩阵集合,计算所述待测试故障量子电路中的故障的故障影响率,其中,所述期望输出状态数据指:将所述输入状态数据输入已消除故障的待测试故障量子电路时,所输出的数据。The
通过仿真实验结果表明,本发明能够模拟大小超过5000个量子比特的故障量子电路,能够满足NISQ时代的应用,而且适用性广泛,既可以独立使用,也可以集成到当前开发的量子自动测试模式生成程序中,用于验证和检测量子电路的设计错误、制造缺陷和量子噪声效应。The simulation results show that the invention can simulate the fault quantum circuit with a size of more than 5000 qubits, can meet the application in the NISQ era, and has a wide range of applicability, which can be used independently or integrated into the currently developed quantum automatic test mode generation A program used to verify and detect design errors, manufacturing defects, and quantum noise effects in quantum circuits.
可选地,在上述技术方案中,所述故障影响率为:,其中,表示所述输入 状态数据,表示的复数共轭转置,表示所述期望输出状态数据,是的复数共轭,的复数共轭,,,表示第个逻辑超算子所对应的Kraus矩阵集合中Kraus矩阵的总 数量,表示:第个逻辑超算子对应的Kraus矩阵集合中的第个Kraus矩阵, 的复数共轭,,表示第个逻辑超 算子所对应的Kraus矩阵集合中Kraus矩阵的总数量,表示第个逻辑超算子对 应的Kraus矩阵集合中的第个Kraus矩阵,的复数共轭,,表示第1个逻辑超算子所对应的Kraus矩阵集合中 Kraus矩阵的总数量,表示第1个逻辑超算子对应的Kraus矩阵集合中的第个Kraus 矩阵,的复数共轭,,表示所有逻辑超算子的总数量,、、 和均为正整数。 Optionally, in the above technical solution, the failure impact rate is: ,in, represents the input state data, express The complex conjugate transpose of , represents the desired output status data, Yes The complex conjugate of , The complex conjugate of , , , means the first logical superoperator The total number of Kraus matrices in the corresponding Kraus matrix set, means: the first logical superoperator The first in the corresponding set of Kraus matrices a Kraus matrix, The complex conjugate of , , means the first logical superoperator The total number of Kraus matrices in the corresponding Kraus matrix set, means the first logical superoperator The first in the corresponding set of Kraus matrices a Kraus matrix, The complex conjugate of , , represents the first logical superoperator The total number of Kraus matrices in the corresponding Kraus matrix set, represents the first logical superoperator The first in the corresponding set of Kraus matrices a Kraus matrix, The complex conjugate of , , represents the total number of all logical superoperators, , , and All are positive integers.
通过将待测试故障量子电路即有缺陷的量子电路表示为多个Kraus矩阵集合,能够编码到在一个双倍大小的张量网络中,张量网络的收缩计算效率高,能够快速计算张量网络收缩,从而能够在很短的时间内完成故障仿真,即得到待测试故障量子电路中的故障的故障影响率。By representing the faulty quantum circuit to be tested, that is, the defective quantum circuit, as a set of multiple Kraus matrices, it can be encoded into a double-sized tensor network. The shrinkage of the tensor network has high computational efficiency and can quickly calculate the tensor network Therefore, the fault simulation can be completed in a very short time, that is, the fault influence rate of the fault in the fault quantum circuit to be tested can be obtained.
上述关于本发明的一种量子电路的故障仿真系统200中的各参数和各个单元模块实现相应功能的步骤,可参考上文中关于一种量子电路的故障仿真方法的实施例中的各参数和步骤,在此不做赘述。For the above-mentioned steps for each parameter and each unit module in the
本发明实施例的一种存储介质,所述存储介质中存储有指令,当计算机读取所述指令时,使所述计算机执行上述任一项所述的一种量子电路的故障仿真方法。An embodiment of the present invention is a storage medium, where instructions are stored in the storage medium, and when a computer reads the instructions, the computer is made to execute any one of the above-mentioned methods for simulating a fault of a quantum circuit.
本发明实施例的一种电子设备,包括处理器和上述的存储介质,所述处理器执行所述存储介质中的指令,其中,电子设备可为计算机、手机或平板电脑等。An electronic device according to an embodiment of the present invention includes a processor and the above-mentioned storage medium, where the processor executes instructions in the storage medium, where the electronic device may be a computer, a mobile phone, or a tablet computer.
所属技术领域的技术人员知道,本发明可以实现为系统、方法或计算机程序产品。As will be appreciated by one skilled in the art, the present invention may be implemented as a system, method or computer program product.
因此,本公开可以具体实现为以下形式,即:可以是完全的硬件、也可以是完全的软件(包括固件、驻留软件、微代码等),还可以是硬件和软件结合的形式,本文一般称为“电路”、“模块”或“系统”。此外,在一些实施例中,本发明还可以实现为在一个或多个计算机可读介质中的计算机程序产品的形式,该计算机可读介质中包含计算机可读的程序代码。Therefore, the present disclosure can be embodied in the following forms, that is, it can be completely hardware, can also be completely software (including firmware, resident software, microcode, etc.), or can be a combination of hardware and software. Called a "circuit," "module," or "system." Furthermore, in some embodiments, the present invention may also be implemented in the form of a computer program product on one or more computer-readable media having computer-readable program code embodied thereon.
可以采用一个或多个计算机可读的介质的任意组合。计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质。计算机可读存储介质例如可以是一一但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件,或者任意以上的组合。计算机可读存储介质的更具体的例子(非穷举的列表)包括:具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机存取存储器(RAM),只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本文件中,计算机可读存储介质可以是任何包含或存储程序的有形介质,该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。Any combination of one or more computer-readable media may be employed. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or a combination of any of the above. More specific examples (non-exhaustive list) of computer readable storage media include: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), Erasable programmable read only memory (EPROM or flash memory), optical fiber, portable compact disk read only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.
尽管上面已经示出和描述了本发明的实施例,可以理解的是,上述实施例是示例性的,不能理解为对本发明的限制,本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。Although the embodiments of the present invention have been shown and described above, it should be understood that the above-mentioned embodiments are exemplary and should not be construed as limiting the present invention. Embodiments are subject to variations, modifications, substitutions and variations.
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