CN104598699A - System C circuit model oriented soft error sensitivity analysis method - Google Patents

System C circuit model oriented soft error sensitivity analysis method Download PDF

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CN104598699A
CN104598699A CN 201510079568 CN201510079568A CN104598699A CN 104598699 A CN104598699 A CN 104598699A CN 201510079568 CN201510079568 CN 201510079568 CN 201510079568 A CN201510079568 A CN 201510079568A CN 104598699 A CN104598699 A CN 104598699A
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circuit
fault
systemc
soft error
model
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CN 201510079568
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Chinese (zh)
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徐东超
绳伟光
何卫锋
毛志刚
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上海交通大学
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Abstract

The invention discloses a System C circuit model oriented soft error sensitivity analysis method. The method comprises the following steps: performing System C modeling to a test circuit; verifying the functional validity of the System C simulation model; selecting fault injection points of the simulation model; in the operational process of the System C simulation model, performing random signal offset turnover to the selected fault injection points, so as to simulating soft error fault and realizing fault injection; combining the test circuit System C simulation model, the selection of the fault injection points and the fault injection, and constructing a simulation fault testing platform; based on the simulation fault testing platform, performing a statistic test; introducing an area factor to a soft error sensitiveness index, calculating and obtaining the soft error sensitivity of the circuit. The System C circuit model oriented soft error sensitivity analysis method disclosed by the invention realizes the circuit soft error sensitivity analysis and has higher assessment precision.

Description

面向SystemC电路模型的软错误敏感度分析方法 A method for a soft error sensitivity analysis of the circuit model SystemC

技术领域 FIELD

[0001] 本发明涉及电路设计可靠性领域,特别是涉及一种基于故障仿真和故障注入的面向SystemC电路模型的软错误敏感度分析方法。 [0001] The present invention relates to the field of circuit design reliability, in particular for a soft error sensitivity analysis is directed SystemC circuit model based fault injection and fault simulation.

背景技术 Background technique

[0002] 随着半导体制造工艺的不断进步,由粒子辐射、噪声干扰等原因引起的软错误问题日益凸显,对电路可靠性造成了越来越严重的影响。 [0002] With the progress of semiconductor manufacturing processes, the problem of soft errors caused by reasons particle radiation, noise, etc. has become increasingly prominent, the reliability of the circuit caused a more serious impact. 在电路设计流程各阶段引入软错误敏感度评估,能有效提高电路可靠性指标、减少设计反复、节约开发成本。 Introducing a soft error sensitivity evaluated in each stage of the circuit design process, the circuit can effectively improve the reliability index, reduce design iterations, save development costs.

[0003] 现有电路软错误敏感度分析方法主要面向传统VHDL/Verilog HDL电路模型与系统设计,以部分电路节点作为故障注入点,通过仿真命令修改电路节点逻辑值实现故障注入,并监控故障注入对系统运行结果的影响,最终基于大规模统计实验得到电路软错误敏感度。 [0003] The soft error sensitivity analysis method of the conventional circuit primarily for conventional VHDL / Verilog HDL circuit model and system design, part of the circuit node to fault as injection point, by modifying the logic value node circuit emulation commands implemented fault injection and fault monitoring injection impact on the operating results of the system, finally get a soft error sensitivity of the circuit is based on large-scale statistical experiments. 然而,现有软错误敏感度分析方法存在一下几点不足:未全面考虑故障注入点的选取,无法模拟绝大多数的软错误现象,从而降低了评估精度;未考虑电路面积因素对软错误发生概率的影响,从而增大了评估结果与实际电路情况间的差异;相较于SystemC语言,传统VHDL/Veri log HDL语言对大规模复杂系统设计的建模存在不足。 However, the existing soft error sensitivity analysis method has several disadvantages about: not take full account selected fault injection points, can not simulate most of the soft error phenomenon, which reduces the accuracy of assessments; the circuit area does not consider the factors of soft errors the impact probability, thereby increasing the difference between the assessment results with the actual circuit condition; compared to the SystemC language, traditions VHDL / Veri log HDL language designed for large-scale complex systems modeling deficiencies.

发明内容 SUMMARY

[0004] 为克服上述现有技术存在的不足,本发明之目的在于提供一种面向SystemC电路模型的软错误敏感度分析方法,通过对复杂电路系统的SystemC建模和仿真,对软错误故障的分析建模,对故障注入点的全面考虑,并将故障注入电路仿真模型中,分析和记录故障对系统运行的影响,并在此基础上进行大规模重复统计实验,从而得到电路软错误敏感度。 [0004] In order to overcome the above disadvantages of the prior art, an object of the present invention is to provide a method of soft error sensitivity analysis model circuit for SystemC, SystemC by modeling and simulation of complex circuitry for soft error failure circuit simulation model influence, failure analysis and documentation on the system operation model analysis, comprehensive consideration of fault injection points, and fault injection, and repeated large-scale statistical experiments on this basis, resulting in a soft error sensitivity of the circuit .

[0005] 为达上述及其它目的,本发明提出一种面向SystemC电路模型的软错误敏感度分析方法,包括如下步骤: [0005] To achieve the above and other objects, the present invention proposes a method for soft error sensitivity analysis model for SystemC circuit, comprising the steps of:

[0006] 步骤一,对测试电路进行SystemC建模; [0006] Step a, the test circuit SystemC modeling;

[0007] 步骤二,验证SystemC仿真模型的功能正确性; [0007] Step two, functional correctness verification SystemC simulation model;

[0008] 步骤三,选取仿真模型故障注入点; [0008] Step three, the fault simulation model selected injection point;

[0009] 步骤四,在SystemC仿真模型运行过程中,对所选取的故障注入点进行随机的信号位翻转,以模拟软错误故障,实现故障注入; [0009] Step 4 during operation of the simulation model SystemC, the failure of the injection point of the selected random bit inverted signal, to simulate a soft error failure to achieve fault injection;

[0010] 步骤五,结合测试电路SystemC仿真模型、故障注入点的选取以及故障注入实现, 构建仿真故障测试平台; [0010] Step 5 SystemC simulation model in conjunction with the test circuit, fault injection and fault injection point is selected to achieve constructed fault simulation test platform;

[0011] 步骤六,基于仿真故障测试平台进行统计实验; [0011] Step six, statistical simulation experiments based on fault test platform;

[0012] 步骤七,将面积因子引入软错误敏感度指标,获得电路的软错误敏感度。 [0012] Step seven, the area factor is introduced with sensitivity soft error, a soft error sensitivity of the circuit is obtained.

[0013] 进一步地,步骤一中,根据标准SystemC语言标准与参考手册以及测试电路实现细节对测试电路进行SystemC建模。 [0013] Further, in a step, according to standard implementation details of SystemC Standards and Reference test circuit and a test circuit model SystemC.

[0014] 进一步地,步骤二中,采用自底向上的验证策略,使用Verilog/SystemC混合仿真的验证方法,对电路各模块逐个进行功能验证。 [0014] Further, in step two, using the bottom-up authentication policy using Verilog / SystemC hybrid simulation method of verification, each module circuit individually for functional verification.

[0015] 进一步地,步骤二进一步包括: [0015] Further, two further comprising the step of:

[0016] 使用待验证SystemC模块替换原电路设计中对应模块,以组成混合系统; [0016] be authenticated using SystemC module replaces the original circuit design corresponding module, to form a hybrid system;

[0017] 以原电路设计作为对照系统,使用脚本语言实现不同测试负载的自动加载与系统运行; [0017] In the original design of the circuit as a control system, using a script language different test load operation and automatic loading system;

[0018] 对相应测试模块的输出端口数据进行周期记录; [0018] The data output port of the respective test modules is a recording period;

[0019] 使用脚本实现混合系统与对照系统运行所产生的数据记录文件的自动化比较,如果相同则表示SystemC模块功能正确,否则需要对SystemC模型进行修改。 [0019] using a script file to achieve more automated data recording and control of the hybrid system produced by the system is running, it means that if the same SystemC modules function correctly, or need to be modified SystemC models.

[0020] 进一步地,步骤三中,分析SystemC仿真模型实现细节,选择电路内部模块输出端口信号以及模块内部所有控制、数据信号作为故障注入点。 [0020] Further, in step three, SystemC analysis simulation model implementation details, the internal circuit block selection signal and an output port all the internal control module, the data signal as a fault injection point.

[0021] 进一步地,步骤四中,征是,使用仿真命令法实现故障注入,使用C++语言,通过对仿真模型内部随机信号数据位进行翻转,实现故障注入。 [0021] Further, the Step 4, characterized by, in order to achieve the simulation method using the fault injection, using the C ++ language, the inside of the simulation model by a random signal data bits flip and fault injection.

[0022] 进一步地,随机信号位的翻转包括单比特信号翻转以及多比特信号中某一随机位的翻转。 [0022] Further, the inverted signal bits randomly flipping a random bit comprising a multi-bit signal and the inverted signal of a single bit.

[0023] 进一步地,步骤五进一步包括 [0023] Furthermore, five further comprising the step of

[0024] 使用伪随机数生成函数产生故障注入时间与故障注入位置; [0024] using a pseudo-random number generation function injection time of failure and fault injection position;

[0025] 根据故障注入时间控制仿真模型的运行、暂停与重启; [0025] The injection time control operation fault simulation model, and restart the suspended;

[0026] 在仿真模型暂停时,根据步骤四内容以及故障注入位置进行故障注入; [0026] When simulation model pause, the injection position according to step four fault injection and fault content;

[0027] 将系统运行结果与未故障注入系统运行结果对比,输出比较结果与故障信息。 [0027] The results of the system operation and fault injection operation is not systematic comparison result, outputs a comparison result and fault information.

[0028] 进一步地,步骤六中,使用分层抽样策略进行统计实验,以电路模块个数作为分层数,以10倍模块故障注入点数作为层内样子数,针对电路各模块,基于仿真故障测试平台进行统计实验。 [0028] Further, in step six, using stratified sampling statistical experimental strategy, the number of circuit modules as to the number of layers to 10 times the number of module faults like injection points as the layer for each circuit block, based on the fault simulation test platform for statistical experiment.

[0029] 进一步地,步骤七中,通过分析软件综合得到测试电路内部各模块的电路面积,从而得到各模块所占电路总面积的比例因子Θ i;根据大规模统计实现记录数据,得到引起仿真模型功能错误的故障注入数占模块总故障注入数的比值/#_,结合面积比例因子与故障比值,根据软错误敏感度计算公式ES, =(ΛΤ"/Λ_")>^得到模块的软错误敏感度。 [0029] Furthermore, the step VII, obtained by the analysis software integrated circuit area through the internal circuit of each module, each module to obtain a scale factor Θ i the total area occupied by the circuit; mass effect recording data according to statistics, cause the simulation to give model function number of error fault injection at the ratio of the total number of fault injection module / # _, bonding area scale factor failure ratio based on the soft error sensitivity of formula ES, = (ΛΤ "/ Λ _")> ^ obtained module soft error sensitivity.

[0030] 与现有技术相比,本发明一种面向SystemC电路模型的软错误敏感度分析方法, 通过对复杂电路系统的SystemC建模和仿真,对软错误故障的分析建模,对故障注入点的全面考虑,并将故障注入电路仿真模型中,分析和记录故障对系统运行的影响,并在此基础上进行大规模重复统计实验,从而得到电路软错误敏感度。 [0030] Compared with the prior art, the present invention provides a method for soft error sensitivity analysis SystemC circuit model by SystemC modeling and simulation of complex circuitry, analytical modeling of the soft error failure, fault injection circuit simulation model influence, failure analysis and documentation of the system running full account of points, and fault injection, and repeated large-scale statistical experiments on this basis, resulting in a soft error sensitivity of the circuit.

附图说明 BRIEF DESCRIPTION

[0031] 图1为本发明一种面向SystemC电路模型的软错误敏感度分析方法的步骤流程图; [0031] FIG 1 A soft error sensitivity analysis for SystemC circuit model for the present invention, the step of the flowchart;

[0032] 图2为本发明较佳实施例的测试电路系统结构框图; [0032] Figure 2 a block diagram of the present invention, the preferred embodiment of the test circuitry of the embodiment;

[0033] 图3为本发明较佳实施例的SystemC/Verilog混合仿真验证平台结构框图; [0033] Figure 3 a preferred embodiment of SystemC / Verilog hybrid simulation platform validation block diagram of the present invention;

[0034] 图4为本发明较佳实施例的混合验证流程图; [0034] FIG. 4 were mixed verification flowchart of one embodiment of the present invention;

[0035] 图5为本发明较佳实施例的仿真故障测试平台结构框图。 [0035] FIG. 5 a block diagram showing a failure simulation test platform preferred embodiment of the present invention.

具体实施方式 detailed description

[0036] 以下通过特定的具体实例并结合附图说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点与功效。 [0036] The following description of embodiments and drawings of the present invention, by binding certain specific examples, those skilled in the art may be disclosed in the present specification easily understand other advantages and effects of the present invention. 本发明亦可通过其它不同的具体实例加以施行或应用,本说明书中的各项细节亦可基于不同观点与应用,在不背离本发明的精神下进行各种修饰与变更。 The present invention can also be practiced or applied by other different specific examples, the details of the specification may also, that various changes and modifications without departing from the spirit of the invention based on various concepts and applications.

[0037] 图1为本发明一种面向SystemC电路模型的软错误敏感度分析方法的步骤流程图。 [0037] FIG 1 A soft error sensitivity analysis for SystemC circuit model of the present invention the step of the flowchart. 如图1所示,本发明一种面向SystemC电路模型的软错误敏感度分析方法,包括如下步骤: 1 A method for a soft error sensitivity analysis SystemC circuit model of the present invention, comprising the steps of:

[0038] 步骤101,测试电路SystemC建模。 [0038] Step 101, the test circuit SystemC modeling.

[0039] 即,根据标准SystemC语言标准与参考手册以及测试电路实现细节对测试电路进行SystemC建模。 [0039] That is, the implementation details of the test circuit according to the standard SystemC SystemC modeling language standard and a test circuit and the reference manual. SystemC仿真模型作为本发明实现基础以及软错误敏感度评估对象。 SystemC simulation model of the present invention as a basis, and soft error sensitivity evaluation target.

[0040] 步骤102, SystemC仿真模型验证。 [0040] Step 102, SystemC simulation model validation. 采用自底向上的验证策略,在Modelsim仿真软件中,使用SystemC/Verilog混合仿真的验证方法验证测试电路SystemC仿真模型的功能正确性,确保仿真模型能正确运行。 Bottom-up authentication policy, in Modelsim simulation software, using SystemC / Verilog hybrid simulation method of verification of the correctness verification test circuit SystemC simulation model, the simulation model to ensure correct operation.

[0041] 步骤102的具体方法如下:具体做法如下: Specific Method [0041] Step 102 as follows: Specifically, the following:

[0042] 使用待验证SystemC模块替换原电路设计中对应模块,以组成混合系统,以原电路设计作为对照系统,使用脚本语言实现不同测试负载的自动加载与系统运行,对相应测试模块的输出端口数据进行周期记录,使用脚本实现混合系统与对照系统运行所产生的数据记录文件的自动化比较,如果相同则表示SystemC模块功能正确,否则需要对SystemC模型进行修改。 [0042] Use be authenticated SystemC module replaces the original circuit design of the corresponding module, to form a hybrid system, the original circuit design as a control system, using a script language automatic loading system to run different test load, the output ports of the respective test modules data recording period, using scripts to achieve more automated data log files mixed system with the control system operation generated, it means that if the same SystemC modules function correctly, or need to be modified SystemC models.

[0043] 步骤103,仿真模型故障注入点选取。 [0043] Step 103, the fault simulation model selected injection point.

[0044] 分析SystemC仿真模型实现细节,选择电路内部模块输出端口信号以及模块内部所有控制、数据信号作为故障注入点,以模拟绝大多数的电路软错误发生情况,从而提高本分析方法的分析精度。 [0044] Analysis SystemC simulation model implementation details, the internal circuit block selection signal and an output port all the internal control module, the data signal as a fault injection point to simulate the vast majority of soft error occurrence circuit, thereby improving the analysis accuracy of the present method of analysis .

[0045] 步骤104,仿真模型故障注入实现模型。 [0045] Step 104, the simulation model to achieve fault injection model.

[0046] 软错误故障会导致电路节点状态发生翻转,可以在SystemC仿真模型运行过程中,对所选取的故障注入点进行随机的信号位翻转,以模拟软错误故障,从而实现故障注入。 [0046] Soft errors can cause circuit failure condition occurs inverted node, can select for the fault signal injection point random bit flip operation in SystemC process simulation model to simulate the soft error failure, thereby achieving fault injection.

[0047] 步骤105,构建仿真故障测试平台 [0047] Step 105, a fault simulation test build platform

[0048] 结合测试电路SystemC仿真模型、故障注入点的选取以及故障注入实现,在VS2012软件开发环境中使用C++语言构建仿真故障测试平台。 [0048] The binding test SystemC simulation model circuit fault injection and fault injection point is selected to achieve, fault testing simulation platform constructed using the C ++ language in a software development environment VS2012. 测试平台实现自动化随机故障注入、故障仿真以及电路运行结果分析,并输出具体故障信息 Test automation platform random fault injection, the results of fault simulation and analysis circuit operation, and outputs failure information specific

[0049] 具体地说,步骤105进一步包括:使用伪随机数生成函数产生故障注入时间与故障注入位置;根据故障注入时间控制仿真模型的运行、暂停与重启;在仿真模型暂停时,根据步骤104内容以及故障注入位置进行故障注入;将系统运行结果与未故障注入系统运行结果对比,输出比较结果与故障信息。 [0049] Specifically, the step 105 further comprises: generating the fault injection time and fault injection position using the pseudo-random number generation function; injection time based on the fault simulation model of the control run, pause and restart; pause when a simulation model, according to step 104 SUMMARY fault injection and fault injection position; the operating system and the results of fault injection operation is not systematic comparison result, outputs a comparison result and fault information.

[0050] 步骤106,大规模统计实验。 [0050] Step 106, a large-scale statistical experiments.

[0051] 基于已有仿真故障测试平台,采用分层抽样策略,通过windows bat脚本语言调用已有仿真故障测试平台,进行10倍样本量的统计实验,并记录统计信息。 [0051] Based on the existing fault simulation test platform, using stratified sampling strategy, fault simulation test platform has been invoked by windows bat script language, statistical experiment 10 times the sample size, and record statistics.

[0052] 步骤107,软错误敏感度计算 [0052] Step 107, soft error sensitivity calculation

[0053] 通过EDA分析软件综合得到测试电路内部各模块的电路面积,从而得到各模块所占电路总面积的比例因子Θ i;根据大规模统计实现记录数据,得到引起仿真模型功能错误的故障注入数占该模块总故障注入数的比值。 [0053] The EDA software integrated circuit obtained by the test area of ​​the internal circuit of each module, each module to obtain a scale factor Θ i the total area occupied by the circuit; mass effect recording data according to statistics, the obtained function model errors causing simulation fault injection the total number of failures of the module ratio of the number of injection. 结合面积比例因子与故障比值, 根据软错误敏感度计算公式MS = (AT" 得到该模块的软错误敏感度。 Bonding area ratio of the scale factor and fault, MS = (AT "get soft error sensitivity of the module according to the sensitivity of the soft error calculation formula.

[0054] 以下将通过一具体实施例来进一步说明本发明:在本实施例中,以基于0R1200处理器的最小系统为测试电路,进行具体的电路软错误敏感度评估。 [0054] below by one embodiment to further illustrate the present invention: In the present embodiment, based on the minimum system 0R1200 processor circuit for testing, specific soft error sensitivity of the evaluation circuit.

[0055] 步骤一:测试电路SystemC建模 [0055] Step a: modeling test circuit SystemC

[0056] 首先,构建如图2所示的最小系统,系统以0R1200处理器为核心处理器,通过wishbone总线结构实现处理器与片外存储器的数据交互。 [0056] First, the minimum system constructed as shown in FIG. 2, the system processor 0R1200 processor core, data interaction with the external to the processor chip memory via bus structure wishbone. 然后,根据表1所示的Verilog/ SystemC语言结构等效性,对最小系统的Verilog代码进行改写,从而实现系统的SystemC 建模。 Then, according to the Verilog / SystemC language structure equivalence shown in Table 1, the minimum of system Verilog code rewriting, enabling the system modeling SystemC.

[0057] 表IVerilog/SystemC语言结构等效性 [0057] Table IVerilog / SystemC language structure equivalence

[0058] [0058]

Figure CN104598699AD00071

[0059] 步骤二:SystemC仿真模型验证 [0059] Step Two: SystemC simulation model validation

[0060] 构建如图3所示的SystemC/Verilog混合仿真验证平台。 [0060] Construction of SystemC / Verilog mixed simulation shown in FIG. 3 internet. 采用自底向上的验证策略,使用脚本语言实现自动化测试程序加载、系统仿真、数据记录与比较。 Bottom-up authentication policy, a scripting language to automate testing program is loaded, system simulation, data recording and comparison. 模块验证流程如图4所示,具体阐述如下: Verification process module shown in Figure 4, specifically described as follows:

[0061 ] 首先,对待验证模块进行SystemC建模,并替换原有纯Verilog描述仿真模型对应模块,构成混合系统SC,并以原有纯Verilog描述仿真模型作为对照系统V。 [0061] First, the authentication module treat SystemC model, and replace the original simulation model corresponding pure description Verilog modules constituting the mixed system SC, and the Verilog description to the original simulation model as pure control system V.

[0062] 其次,使用脚本文件,对混合系统与对照系统分别进行标准测试程序加载,并调用Modelsim仿真器进行系统仿真。 [0062] Next, using a script file, the hybrid system and the control system are standard test program loading, and calls Modelsim simulator system simulation. 系统仿真过程中对待验证模块的输出端口信号数据进行周期记录,生成数据文件。 A data output port signal treatment module system simulation verification performed during the recording period, generating a data file.

[0063] 然后,使用脚本文件对两组数据文件逐个对比。 [0063] Then, using a script file-by-file comparison of the two sets of data. 如果所有对比结构都显示相同,则表明模块的SystemC模型功能正确。 If all the comparative structure display the same, it indicates that the function module SystemC models correctly. 反之,贝Ij表明模块SystemC模型存在错误,重新进行模块建模与功能验证,直到验证通过。 On the other hand, Tony Ij indicates an error module SystemC models, re-modeling and functional verification module, the authentication succeeds.

[0064] 当测试电路系统所有模块均验证通过后,将系统SystemC模型完整移植到Visual Studio 2012软件开发环境中,以便于后续仿真故障测试平台的开发。 [0064] When the test circuitry verified by all modules, the system SystemC models transplanted to full Visual Studio 2012 software development environment, to facilitate the development of subsequent failure simulation test platform.

[0065] 步骤三:仿真模型故障注入点选取 [0065] Step Three: Fault Simulation Model selected injection point

[0066] 故障注入点的选取从仿真效率以及故障覆盖度两方面考虑。 [0066] failure to select the injection point from the viewpoint of both fault coverage and simulation efficiency. 较少的故障注入点虽然会提高仿真效率,但由于故障覆盖度的不足,会导致最终评估精度的降低。 Although fewer fault injection points will increase simulation efficiency, but due to lack of fault coverage, the final assessment will lead to reduced accuracy. 反之,较多的故障注入点虽然使得故障覆盖度增大,从而提高评估精度,但同时会降低仿真效率。 Conversely, although more injection points such that failure fault coverage is increased, thereby improving the estimation accuracy, but will also reduce the efficiency of the simulation.

[0067] 为了提高最终软错误敏感度评估精度,选取仿真系统中各模块的输出端口信号以及内部所有控制、数据信号作为故障注入点,以模拟绝大多数的电路软错误现象,提高故障模拟覆盖度,从而提高分析方法的评估精度。 [0067] In order to improve the final sensitivity soft error estimation accuracy, select an output port signal simulation system of each module and all the internal control, the data signal as a fault injection point, most of the circuitry to simulate the phenomenon of a soft error, fault simulation improve coverage degrees, thereby improving the estimation accuracy of the analytical method.

[0068] 步骤四:仿真模型故障注入实现模型 [0068] Step Four: the fault simulation model implementation model injection

[0069] 软错误故障会导致电路节点状态发生翻转,可以在SystemC仿真模型运行过程中,对所选取的故障注入点进行随机的信号位翻转,以模拟软错误故障,从而实现故障注入。 [0069] Soft errors can cause circuit failure condition occurs inverted node, can select for the fault signal injection point random bit flip operation in SystemC process simulation model to simulate the soft error failure, thereby achieving fault injection.

[0070] 随机信号位翻转包括两种类型,单比特信号翻转以及多比特信号中某一随机位的翻转。 [0070] Random signal includes two types of bit inversion, bit flipping a random signal and the inverted single-bit multi-bit signal. 位翻转操作实现随机信号位高电平变为低电平或者低电平变为高电平。 Bit flip operation random signal bits high to low or low to high.

[0071] 1.单比特位翻转 [0071] 1. The single-bit flipping

[0072] 随机信号宽度为1位,其示意代码如下: [0072] The width of a random signal, which is a schematic code is as follows:

[0073] OneBit_signal = OneBit_singal. read () == Log_l ? Log_0:Log_l ; . [0073] OneBit_signal = OneBit_singal read () == Log_l Log_0:? Log_l;

[0074] 2.多比特位翻转 [0074] 2. Multi-bit flipping

[0075] 随机信号宽度大于I位,对其中某一随机位进行翻转,其示意代码如下: [0075] The random signal is greater than the width of I bits, of which flip a random bit, which is a schematic code is as follows:

[0076] sc_lv<signal_length>temp = MultiBit_signal. read(); . [0076] sc_lv <signal_length> temp = MultiBit_signal read ();

[0077] temp [random_number % signal_length] = = Log_l ? [0077] temp [random_number% signal_length] = = Log_l?

[0078] temp. set_bit(random_number% signal_length,Log_0): . [0078] temp set_bit (random_number% signal_length, Log_0):

[0079] temp. set_bit(random_number% signal_length,Log_l); . [0079] temp set_bit (random_number% signal_length, Log_l);

[0080] MultiBit_signal = temp。 [0080] MultiBit_signal = temp.

[0081] 步骤五:构建仿真故障测试平台 [0081] Step Five: Build failure simulation test platform

[0082] 结合0R1200处理器最小系统的SystemC仿真模型、故障注入点的选取以及故障注入实现模型,在VS2012软件开发环境中使用C++语言构建仿真故障测试平台。 SystemC Simulation Model [0082] The minimum binding 0R1200 processor systems, fault injection and fault injection point implementation model selection, fault testing simulation platform constructed using the C ++ language in a software development environment VS2012. 图5所示为仿真故障测试平台结构框图,平台包括故障信息产生模块、系统运行分析模块、系统运行控制模块、故障注入模块以及测试电路SystemC仿真模型5部分组成。 Figure 5 is a block diagram showing the simulation fault test platform, the platform comprising a failure information generation module, an analysis module the system is running, the system control module, and the module fault injection test circuit simulation models SystemC 5 parts. 各部分功能以及实现如下所述: Each part of functions and implemented as follows:

[0083] 故障信息产生模块,使用伪随机数生成函数产生故障注入时间与故障注入位置。 [0083] Fault information generation module generates the fault injection and fault injection time position using a pseudorandom number generation function. 使用系统函数产生两个12位的伪随机数,并通过位拼接产生一个24位宽度的伪随机数;使用线性同余方法,通过取模操作产生一个指定范围内的伪随机数。 The system using two pseudo random number generating function 12 and generates a 24-bit pseudo-random number bit width by splicing; using linear congruential method for generating pseudorandom numbers within a specified range by the modulo operation.

[0084] [0084]

Figure CN104598699AD00081

系统运行控制模块,根据故障注入时间控制仿真模型的运行、暂停与重启。 System operation control module, controls the operation of the simulation model, according to the fault injection pause and the restart time.

[0085] 故障注入模块,在仿真模型暂停时,根据故障模型以及故障注入位置进行故障注入。 [0085] The fault injection module pause when a simulation model, according to the injection position fault injection and fault fault model. 其实现如步骤四所示。 Its implementation as shown in step IV.

[0086] 系统运行分析模块,将系统运行结果与未故障注入系统运行结果对比,输出比较结果与故障信息 [0086] operating system analysis module, and the operation results of the system is not fault injection operation comparison result, it outputs a comparison result to the fault information system

[0087] 步骤六:大规模统计实验 [0087] Step Six: large-scale statistical test

[0088] 基于已有仿真故障测试平台,采用分层抽样策略进行统计实验。 [0088] Based on the existing fault simulation test platform, stratified sampling strategy for statistical experiment. 分层策略是指,以电路系统内部模块数量为分层数,以各模块作为总体分层,层内样本数量为各模块故障注入点总数的10倍量。 Hierarchical policy refers to the internal circuitry of the number of layers the number of modules, each module as a whole to a layered, the inner layer is the number of samples is 10 times the total amount of the modules are faulty injection point. 并使用4X4矩阵乘法,背包问题以及快速排序3个测试程序,作为系统不同负载。 And use the 4X4 matrix multiplication, knapsack problem, and quick sort three test procedures, load a different system. 在此基础上,通过windows bat脚本语言调用已有仿真故障测试平台,进行共计约30万次的仿真实验,并记录故障信息。 On this basis, through the windows bat script language invoked existing fault simulation test platform for a total of simulation experiments about 30 million times, and record the fault information.

[0089] 步骤七:软错误敏感度计算 [0089] Step 7: soft error sensitivity calculation

[0090] 通过Synopsys Design Compiler设计工具,对测试电路进行综合,得到测试电路内部各模块的电路面积,并在此基础上计算各模块所占电路总面积的比例因子Θ i;根据步骤六中大规模统计实验的故障信息数据,得到各模块引起仿真模型功能错误的故障注入数占该模块总故障注入数的比值ΛΤ" / 结合计算得到的面积比例因子与故障比值,根据软错误敏感度计算公式^:= (ΛΤ" / 得到该模块的软错误敏感度。 [0090], the test circuit design tools by Synopsys Design Compiler synthesis, to give a test circuit area of ​​the internal circuitry of each module, each module and calculating the total area occupied by the scale factor of the circuit on the basis of Θ i; Sixth step The large fault information data statistical experimental scale to give the function of each module due to the simulation model number of error fault injection is injected into the total number of module failure ratio ΛΤ "/ binding factor failure area ratio calculated ratio, calculated according to a soft error sensitivity ^: = (ΛΤ "/ get soft error sensitivity of the module.

[0091] 综上所述,本发明一种面向SystemC电路模型的软错误敏感度分析方法,通过对复杂电路系统的SystemC建模和仿真,对软错误故障的分析建模,对故障注入点的全面考虑,并将故障注入电路仿真模型中,分析和记录故障对系统运行的影响,并在此基础上进行大规模重复统计实验,从而得到电路软错误敏感度。 [0091] In summary, the present invention provides a method for soft error sensitivity analysis SystemC circuit model by SystemC modeling and simulation of complex circuitry, analytical modeling of soft error failure, fault injection point All things considered, and the effects of the injection circuit simulation model, analyze and record the fault of the system operation failure, and repeated large-scale statistical experiments on this basis, resulting in a soft error sensitivity of the circuit.

[0092] 与现有技术相比,本发明具有如下优点: [0092] Compared with the prior art, the present invention has the following advantages:

[0093] 1.本发明面向SystemC电路设计。 [0093] 1. The present invention is directed to circuit design SystemC. 在大规模复杂电路设计中,SystemC语言由于其优良的软硬件协同开发能力,被广泛应用于系统建模与仿真验证中。 In large and complex circuit design, SystemC language due to its excellent capability of hardware and software co-development, are widely used in the modeling and simulation. 本发明针对SystemC 电路设计,对电路可靠性设计与分析具有重要的指导意义。 The present invention is directed to SystemC circuit design has important significance reliability circuit design and analysis right.

[0094] 2.本发明具有更高的评估精度:将电路面积影响因素引入软错误敏感度评估指标,使得分析结果更加符合软错误在实际电路中的发生情况;全面考虑故障注入点选取,以模拟绝大多数软错误现象,提高软错误模拟覆盖度。 [0094] 2. The present invention has higher estimation accuracy: introducing factors will influence the circuit area of ​​the soft error sensitivity evaluation index, such that results more in line with the occurrence of a soft error in the actual circuit; fault injection point extracting full consideration to The vast majority of soft error simulation, and enhanced soft error simulation coverage.

[0095] 上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。 [0095] The above-described embodiments are only illustrative of the principles and effect of the present invention, the present invention is not intended to be limiting. 任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修饰与改变。 Anyone skilled in the art may be made without departing from the spirit and scope of the present invention, the above-described embodiments can be modified and changed. 因此, 本发明的权利保护范围,应如权利要求书所列。 Accordingly, the scope of rights of the present invention, as listed in a claim should book.

Claims (10)

  1. 1. 一种面向SystemC电路模型的软错误敏感度分析方法,包括如下步骤: 步骤一,对测试电路进行SystemC建模; 步骤二,验证SystemC仿真模型的功能正确性; 步骤=,选取仿真模型故障注入点; 步骤四,在SystemC仿真模型运行过程中,对所选取的故障注入点进行随机的信号位翻转,W模拟软错误故障,实现故障注入; 步骤五,结合测试电路SystemC仿真模型、故障注入点的选取化及故障注入实现,构建仿真故障测试平台; 步骤六,基于仿真故障测试平台进行统计实验; 步骤走,将面积因子引入软错误敏感度指标,计算获得电路的软错误敏感度。 Soft error sensitivity analysis circuit 1. A method for SystemC model, comprising the following steps: Step a, the test circuit SystemC model; two step, verification of the correctness of the simulation model SystemC; step = select Fault Simulation Model injection point; step four, the process simulation model running in SystemC, for the selected fault injection point of random signal bit flip, W simulated soft error failure to achieve fault injection; step 5 binding SystemC simulation model test circuit fault injection and selection of the injection point to achieve fault, fault simulation test build platform; step 6 experiments based on statistical simulation fault test platform; step down, the area of ​​the soft error sensitivity index factor is introduced, the sensitivity of the soft error calculation circuit is obtained.
  2. 2. 如权利要求1所述的一种面向SystemC电路模型的软错误敏感度分析方法,其特征在于;步骤一中,根据标准SystemC语言标准与参考手册W及测试电路实现细节对测试电路进行SystemC建模。 As claimed in one of the soft error sensitivity analysis is a method for the circuit model SystemC claims, characterized in that; step a, the implementation details and Reference and test circuit according to a standard W SystemC language standard test circuit SystemC modeling.
  3. 3. 如权利要求1所述的一种面向SystemC电路模型的软错误敏感度分析方法,其特征在于;步骤二中,采用自底向上的验证策略,使用Verilog/SystemC混合仿真的验证方法, 对电路各模块逐个进行功能验证。 As claimed in one of the soft error sensitivity analysis is a method for the circuit model SystemC claims, characterized in that; step two, a bottom-up authentication policy using Verilog / SystemC hybrid simulation method of verification of each circuit module individually for functional verification.
  4. 4. 如权利要求3所述的一种面向SystemC电路模型的软错误敏感度分析方法,其特征在于,步骤二进一步包括: 使用待验证SystemC模块替换原电路设计中对应模块,W组成混合系统; W原电路设计作为对照系统,使用脚本语言实现不同测试负载的自动加载与系统运行; 对相应测试模块的输出端口数据进行周期记录; 使用脚本实现混合系统与对照系统运行所产生的数据记录文件的自动化比较,如果相同则表示SystemC模块功能正确,否则需要对SystemC模型进行修改。 As claimed in one of the 3, soft error sensitivity analysis circuit model for SystemC claims, characterized in that the two further comprising the step of: using SystemC module to be verified replace the original circuit design corresponding to the module, W composed of a hybrid system; W original circuit design as a control system, using a script language different test loads automatically load and run the system; the output port data corresponding to the test module periodic record; implemented as scripts data recording file mixing system to control system operation the generated Compare automation, it means that if the same SystemC modules function correctly, or need to be modified SystemC models.
  5. 5. 如权利要求1所述的一种面向SystemC电路模型的软错误敏感度分析方法,其特征在于;步骤S中,分析SystemC仿真模型实现细节,选择电路内部模块输出端口信号W及模块内部所有控制、数据信号作为故障注入点。 5. one of the claim 1 for soft error sensitivity analysis SystemC circuit model, which is characterized in that; the step S, the analysis SystemC simulation model implementation details, the internal module select signal W output port and the internal circuits of all modules a control data signal as a fault injection point.
  6. 6. 如权利要求1所述的一种面向SystemC电路模型的软错误敏感度分析方法,其特征在于;步骤四中,征是,使用仿真命令法实现故障注入,使用C++语言,通过对仿真模型内部随机信号数据位进行翻转,实现故障注入。 6. The soft error sensitivity analysis method as claimed in claim 1, one of the faces of the circuit model SystemC, wherein; step four, characterized by, in order to achieve the simulation method using the fault injection, using the C ++ language, the simulation model by internal random bit signal data flip and fault injection.
  7. 7. 如权利要求6所述的一种面向SystemC电路模型的软错误敏感度分析方法,其特征在于;随机信号位的翻转包括单比特信号翻转W及多比特信号中某一随机位的翻转。 7. An oriented according to claim 6 SystemC soft error sensitivity analysis model circuit, characterized in that; inverted signal bits randomly flipping a random bit comprises a signal inversion W and single-bit multi-bit signal.
  8. 8. 如权利要求1所述的一种面向SystemC电路模型的软错误敏感度分析方法,其特征在于,步骤五进一步包括使用伪随机数生成函数产生故障注入时间与故障注入位置; 根据故障注入时间控制仿真模型的运行、暂停与重启; 在仿真模型暂停时,根据步骤四内容W及故障注入位置进行故障注入; 将系统运行结果与未故障注入系统运行结果对比,输出比较结果与故障信息。 Soft error sensitivity analysis 8. The method of claim 1, wherein one of said circuit model for SystemC, wherein further comprising the step of generating five fault injection and fault injection time position using the pseudo-random number generation function; injection time according to the fault simulation model operation control, and restart the paused; pause when the simulation model, the injection position according to step four fault injection and fault content W; and the operation results of the system is not fault injection system running comparison result, outputs a comparison result and fault information.
  9. 9. 如权利要求1所述的一种面向SystemC电路模型的软错误敏感度分析方法,其特征在于;步骤六中,使用分层抽样策略进行统计实验,W电路模块个数作为分层数,w 10倍模块故障注入点数作为层内样子数,针对电路各模块,基于仿真故障测试平台进行统计实验。 9. The one claim 1 for soft error sensitivity analysis SystemC circuit model, which is characterized in that; Sixth step, using stratified sampling statistical experimental strategy, the number of W circuit module as the number of layers, w 10 times the number of modules as fault injection points like inner layer, for each circuit block, based on statistical simulation experiments fault test internet.
  10. 10.如权利要求1所述的一种面向SystemC电路模型的软错误敏感度分析方法,其特征在于;步骤走中,通过分析软件综合得到测试电路内部各模块的电路面积,从而得到各模块所占电路总面积的比例因子0 根据大规模统计实现记录数据,得到引起仿真模型功能错误的故障注入数占模块总故障注入数的比值,结合面积比例因子与故障比值, 根据软错误敏感度计算公式Sirs, =(w/""" /wr"')x6得到模块的软错误敏感度。 10. one of the soft error sensitivity analysis is a method for the circuit model SystemC claim, wherein; step down, the integrated circuit area to obtain internal test circuit modules by software, whereby each module the total area of ​​the circuit scale according to the scale factor to achieve statistical records 0 data obtained function model errors causing simulation of the total number of failures number of failures injection ratio of injection modules, and fault factor binding area ratio ratio is calculated based on the soft error sensitivity Sirs, = (w / "" "/ wr" ') x6 obtained a soft error sensitivity module.
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