CN112416760B - Module packaging method and device for universal test platform TestBench - Google Patents
Module packaging method and device for universal test platform TestBench Download PDFInfo
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- G06F11/3684—Test management for test design, e.g. generating new test cases
Abstract
The invention relates to a module packaging method and device of a universal test platform TestBench, wherein the method comprises the following steps: acquiring a first Task module to be repackaged; the internal structure of the first Task Module is not changed, and the first Task Module is packaged into a bottom layer of a new Module in a Module file mode according to input and output signals of the first Task Module and set starting and stopping signals; and setting a top layer Module on the top layer of the new Module, wherein the top layer Module is used for realizing communication between the outside of the new Module and the bottom layer, and calling the first Task Module in a mode of modularized calling. The method and the device can effectively call the output excitation of the Task code generation interface through the input signal in the top file, avoid the heavy workload caused by modifying the mature module code in the Task, and solve the problems of less time sequence conflict between the bottom excitation and the top excitation, and the like.
Description
Technical Field
The invention belongs to the technical field of FPGA (field programmable gate array) testing, and particularly relates to a module packaging method and device for a universal test platform TestBench.
Background
In the full-flow FPGA software evaluation project (comprising static test and dynamic test), the workload proportion occupied by the dynamic test is far greater than that of the static test, and one of the most of the workload in the dynamic test is to design, build and debug a test platform TestBench. The common interfaces such as DSP, temperature measurement, serial ports, 1553B, flash and the like are written into a universal interface library, so that the efficiency of constructing a test platform is improved.
The test platform TestBench interface library comprises two package types, one is in a Module package form and the other is in a Task package form. When the same interface appears in one project for many times, the Module packaging form does not need to modify the mature interface main body function code; the Task package requires modification of the mature interface body function code. If simple Task packaging is changed into Module packaging with input and output, the Task Module can only be called from the bottom file to generate excitation, so that the problems of uncoordinated time sequence, even time sequence conflict and the like of bottom excitation and top excitation are easily caused, the time for building a test platform is prolonged, and the efficiency for building the test platform is reduced.
Disclosure of Invention
In view of the above analysis, the invention aims to disclose a Module packaging method and device for a universal test platform TestBench, which avoid the problem caused by changing Task packaging into Module packaging.
The invention discloses a module packaging method of a universal test platform TestBench, which comprises the following steps:
acquiring a first Task module to be repackaged;
the internal structure of the first Task Module is not changed, and the first Task Module is packaged into a bottom layer of a new Module in a Module file mode according to input and output signals of the first Task Module and set starting and stopping signals;
and setting a top layer Module on the top layer of the new Module, wherein the top layer Module is used for realizing communication between the outside of the new Module and the bottom layer, and calling the first Task Module in a mode of modularized calling.
Further, a first interaction module and a response calling module are also packaged in the bottom layer of the new module;
the first interaction Module adds input, output, starting and ending signals to the first Task Module, and encapsulates the added signals into a Module file form for top-level calling;
the response calling module executes a first Task module by transmitting the input signal for a single time according to the starting signal, and the mark ending signal is valid after the execution of the first Task module is ended; and the output signal of the first Task module is output to the first interaction module through the response calling module or directly output to the first interaction module.
Further, in the executing process of the first Task module, that is, before the ending signal flag is valid, the response calling module does not transmit the input signal any more to repeatedly execute the first Task module.
Further, the first interaction Module mainly includes two parts, one part is used for setting time units and precision values, the other part is used for establishing a Module file interacted with the top layer, and the Module file defines an input port, an input starting port, an output ending port, a wire definition output signal, a wire definition output ending signal, an REG definition bottom layer receiving signal and an invalid value of 0, an assignment connection output result and an assignment connection ending signal.
Further, the execution method of the response calling module comprises the following steps:
1) Continuously judging whether the rising edge of the starting signal arrives or not;
2) When the rising edge of the starting signal comes, the ending signal is endowed with '1', and the ending signal is marked invalid;
3) Continuously judging the rising edge in the process of giving a '1' to the end signal;
4) After the rising edge of the ending signal comes, transmitting an input signal to execute a first Task module;
5) After the first Task module executes once, the end signal is assigned 0, and the end signal is marked as valid.
Further, in the response calling module, waiting for a rising edge of a starting signal through an always block; ending the invalid assignment of the signal, wherein the value is 0-1; the first Task module is executed by transmitting an input signal through the rising edge of the waiting ending signal of the always block; and after execution, effectively assigning a value to the end signal.
Further, in the top layer module of the new module, a second Task module and a second interaction module are included;
in the second Task module, an input signal and an output signal of the first Task module are packaged into the second Task module by using a calling mode of the first Task module, a starting signal is output, and the input signal, the output signal and a response ending signal are transmitted to the second interaction module;
in the second interactive Module, a start signal, an input signal, an output signal and a response end signal are connected to the first interactive Module in a modularized manner.
Further, a Task file is established in the second Task module, input signals of the first Task module are defined, and a starting signal of the first Task module is enabled to be 1, so that the starting signal is enabled to be effective; transmitting the input signal of the first Task module to the second interaction module; waiting for the falling edge of the end signal fed back by the bottom layer of the new module; when the falling edge of the end signal arrives, the start signal is set to 0, and the start signal is cleared.
Further, the second interaction module includes a definition portion and an instantiation portion;
the definition part comprises REG definition start signals and assigns invalid '0'; REG defines the input signal and assigns an initial value; wire definition end signal;
the instantiation part instantiates signals connected with the second Task Module into a Module file form, and specifically comprises input instantiation, start signal instantiation, output signal instantiation, end signal instantiation and input signal instantiation definition.
The embodiment also discloses a module packaging device based on the module packaging method of the universal test platform TestBench,
the system comprises a top layer test excitation main flow module, a top layer call starting module and a bottom layer general encapsulation module which are connected in sequence;
the bottom layer general encapsulation Module is used for encapsulating the first Task Module into a bottom layer of a new Module in a Module file mode according to input and output signals of the first Task Module and set starting and stopping signals without changing the internal structure of the first Task Module to be encapsulated again;
the top layer calling starting Module is connected between the top layer test excitation main flow Module and the bottom layer general packaging Module and is used for setting a top layer test Module file to realize communication between the top layer test excitation main flow Module and the bottom layer general packaging Module, and a first Task Module is called in a Module instantiation calling mode;
the top layer test excitation main flow module is used for transmitting an input signal for calling the first Task module to the top layer call starting module and receiving an output result fed back after the first Task module is called from the top layer call starting module.
The invention can realize at least one of the following beneficial effects:
by adopting the technical test, the invention can effectively call the output excitation of the Task code generation interface through the input signal in the top file, thereby avoiding the problems of heavy workload caused by modifying the mature module code in the Task, less time sequence conflict between the bottom excitation and the top excitation, and the like;
the starting module is called through the top layer, the starting and the completion of interface excitation are controlled, the interface excitation output is completed through the bottom layer universal packaging module and the top layer module, and the generalized module packaging method is adopted, so that the code of a mature module in the Task is prevented from being modified, and the aim of improving the efficiency of building the test platform is achieved.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, like reference numerals being used to refer to like parts throughout the several views.
FIG. 1 is a flow chart of a module packaging method in a first embodiment;
fig. 2 is a schematic diagram of the principle of cross-linking of constituent connecting signals of the device in the second embodiment;
FIG. 3 is a diagram showing an example of the implementation of Verilog voice in the top-level excitation main flow module in the second embodiment;
FIG. 4 is a diagram showing an example of the implementation of Verilog voice of the second Task module in the second embodiment;
FIG. 5 is a diagram showing an example of a Verilog voice implementation of the second interactive module in the second embodiment;
FIG. 6 is a diagram showing an example of the implementation of Verilog voice of the first interactive module in the second embodiment;
fig. 7 is a diagram of a Verilog voice implementation example of the response invoking module in the second embodiment.
Detailed Description
Preferred embodiments of the present invention are described in detail below with reference to the attached drawing figures, which form a part of the present application and, together with the embodiments of the present invention, serve to explain the principles of the invention.
Example 1
The embodiment discloses a module packaging method of a universal test platform TestBench, as shown in fig. 1, comprising the following steps:
step S1, acquiring a first Task module to be repackaged;
the first Task module is a verified mature Verilog code which can realize specific functions, and the Task code does not need to be changed in the process of constructing a test platform TestBench.
S2, the internal structure of the first Task Module is not changed, and the first Task Module is packaged into a bottom layer of a new Module in a mode of a Module file according to input and output signals of the first Task Module and set starting and stopping signals;
and S3, setting a top layer Module on the top layer of the new Module, wherein the top layer Module is used for realizing communication between the outside of the new Module and the bottom layer, and calling the first Task Module in a mode of modularized calling.
Based on the Module packaging method, when the test platform TestBench is built, any section of code of a Module file at the bottom layer of a new Module packaged by the mature first Task Module is not required to be changed, only the Module file at the top layer of the Module is required to be defined, input signals and output results to be transmitted can be defined according to a general packaging control method, and the mature Task Module can be called in the top-layer test excitation main flow Module, so that the code changing scale of directly calling the Task Module is effectively reduced, the calling difficulty of the mature TSK Module is reduced, only the input and output after packaging is required to be understood during application, the overall output quantity hidden in the mature Task Module is not required to be understood, the overall difficulty of building the test platform is further reduced, and the efficiency of building the test platform is improved.
Specifically, a first interaction module and a response calling module are also packaged in the bottom layer of the new module;
the first interaction Module is used for packaging the first Task Module into a Module package, specifically, in the first interaction Module, input, output, start and end signals are added to the first Task Module, and the added signals are packaged into a Module file form for top-level calling;
specifically, the first interaction Module includes two parts, one part is used for setting a time unit and an accuracy value, and the other part is used for establishing a Module file for interacting with the top layer, defining an input port, defining an input starting port, defining an output ending port, wire definition output signals, wire definition output ending signals, REG definition bottom layer receiving signals and invalidating values of 0, an assignment connection output result and an assignment connection ending signal.
The response calling module is used for calling a first Task module at the bottom layer, the first Task module is executed by transmitting the input signal once according to the starting signal in the response calling module, and a mark ending signal is valid after the execution of the first Task module is ended; and the output signal of the first Task module is output to the first interaction module through the response calling module or is directly output to the first interaction module through the direct connection between the first Task module and the first interaction module.
And in the execution process of the first Task module, namely before the ending signal mark is valid, the input signal is not transmitted any more to repeatedly execute the first Task module.
Specifically, the execution method of the response calling module comprises the following steps:
1) Continuously judging whether the rising edge of the starting signal arrives or not;
2) When the rising edge of the starting signal comes, the ending signal is endowed with '1', and the ending signal is marked invalid;
3) Continuously judging the rising edge in the process of giving a '1' to the end signal;
4) After the rising edge of the ending signal comes, transmitting an input signal to execute a first Task module;
5) After the first Task module executes once, the end signal is assigned 0, and the end signal is marked as valid.
More specifically, the main components of the response calling module include: waiting for a start signal rising edge by an always block; ending the invalid assignment of the signal, wherein the value is 0-1; the first Task module is executed by transmitting an input signal through the rising edge of the waiting ending signal of the always block; and after execution, effectively assigning a value to the end signal.
Specifically, in the top layer setting of the new module, a second Task module and a second interaction module are set;
in the second Task module, an input signal and an output signal of the first Task module are packaged into the second Task module by using a calling mode of the first Task module, a starting signal is output, and the input signal, the output signal and a response ending signal are transmitted to the second interaction module;
specifically, a Task file is built in the second Task module, input signals of the first Task module are defined, and a starting signal of the first Task module is enabled to be 1, so that the starting signal is enabled to be effective; transmitting the input signal of the first Task module to the second interaction module; waiting for the falling edge of the end signal fed back by the bottom layer of the new module; when the falling edge of the end signal arrives, the start signal is set to 0, and the start signal is cleared.
In the second interactive Module, a start signal, an input signal, an output signal and a response end signal are connected to the first interactive Module in a modularized manner.
In particular, the second interactive module mainly comprises a definition part and an instantiation part,
the definition part includes REG definition enable signal and assigns invalid '0'; REG defines the input signal and assigns an initial value; wire definition end signal;
the instantiation part instantiates signals connected with the second Task Module into a Module file form, and specifically comprises input instantiation, start signal instantiation, output signal instantiation, end signal instantiation and input signal instantiation definition.
And through instantiation of the second interaction module, the second interaction module and the first interaction module are communicated.
Specifically, the procedure of calling the first Task Module newly packaged into the Module is as follows:
1) Through top-layer excitation, a Task calling mode is adopted to call a second Task module, and an input signal is transmitted into the second Task module;
2) Generating a starting signal in the second Task module, responding to the ending signal, and connecting the starting signal with the input signal to be transmitted into the second interaction module;
3) In the second interaction Module, the starting signal and the input signal are transmitted into the first interaction Module through Module instantiation;
4) In the first interaction module, connecting a starting signal and an input signal with an incoming response calling module;
5) In the response calling module, the first Task module is called in a Task calling mode in response to the starting signal, an input signal is transmitted into the first Task, and after the first Task module is executed, an ending signal is generated.
6) In the first interaction module and the second interaction module, the end signal and the output data are transmitted into the second Task module in an exemplified and connected signal mode, and the end signal output data are fed back out through the second Task module.
Example two
The embodiment discloses a module packaging device of a universal test platform TestBench, which comprises a top layer test excitation main flow module, a top layer call starting module and a bottom layer universal packaging module which are connected in sequence as shown in fig. 2;
the bottom layer general encapsulation Module is used for encapsulating the first Task Module into a bottom layer of a new Module in a Module file mode according to input and output signals of the first Task Module and set starting and stopping signals without changing the internal structure of the first Task Module to be encapsulated again;
the top layer calling starting Module is connected between the top layer test excitation main flow Module and the bottom layer general packaging Module and is used for setting a top layer test Module file to realize communication between the top layer test excitation main flow Module and the bottom layer general packaging Module, and a first Task Module is called in a Module instantiation calling mode;
the top layer test excitation main flow module is used for transmitting an input signal for calling the first Task module to the top layer call starting module and receiving an output result fed back after the first Task module is called from the top layer call starting module.
Specifically, in the top-level test excitation main flow module, an input signal is transmitted into the top-level call starting module in a Task call mode; the top layer calling starting Module generates a starting signal according to the input signal, responds to an ending signal, and transmits the starting signal and the input signal to the bottom layer universal packaging Module after performing Module instantiation, so that the first Task Module is called in response to the starting signal; after the execution of the first Task module is completed, an output signal and an end signal are generated, and the top-layer calling starting module is connected with the output signal to the top-layer excitation module in a signal connection mode.
Specifically, the bottom layer general packaging module comprises a first interaction module and a response calling module;
the first interaction Module is used for packaging the first Task Module into a Module package;
specifically, in the first interaction Module, input, output, start and end signals are added to the first Task Module, and the added signals are packaged into a Module file form for top-level calling;
more specifically, the first interaction Module mainly includes two parts, one part is for setting a time unit and an accuracy value, and the other part is for establishing a Module file for interacting with the top layer, defining an input port, defining an input start port, defining an output end port, wire definition output signals, wire definition output end signals, REG definition bottom layer receiving signals and invalidating values of 0, an assignment connection output result and an assignment connection end signal.
The response calling module is used for calling a first Task module at the bottom layer, the first Task module is executed by transmitting the input signal once according to the starting signal in the response calling module, and a mark ending signal is valid after the execution of the first Task module is ended; and in the execution process of the first Task module, namely before the ending signal mark is valid, the input signal is not transmitted any more to repeatedly execute the first Task module.
Specifically, the execution method of the response calling module comprises the following steps:
1) Continuously judging whether the rising edge of the starting signal arrives or not;
2) When the rising edge of the starting signal comes, the ending signal is endowed with '1', and the ending signal is marked invalid;
3) Continuously judging the rising edge in the process of giving a '1' to the end signal;
4) After the rising edge of the ending signal comes, transmitting an input signal to execute a first Task module;
5) After the first Task module executes once, the end signal is assigned 0, and the end signal is marked as valid.
More specifically, the main components of the response calling module include: waiting for a start signal rising edge by an always block; ending the invalid assignment of the signal, wherein the value is 0-1; the first Task module is executed by transmitting an input signal through the rising edge of the waiting ending signal of the always block; and after execution, effectively assigning a value to the end signal.
Specifically, the top layer calling starting module comprises a second Task module and a second interaction module;
in the second Task module, an input signal and an output signal of the first Task module are packaged into the second Task module by using a calling mode of the first Task module, a starting signal is output, and the input signal, the output signal and a response ending signal are transmitted to the second interaction module;
specifically, a Task file is built in the second Task module, input signals of the first Task module are defined, and a starting signal of the first Task module is enabled to be 1, so that the starting signal is enabled to be effective; transmitting the input signal of the first Task module to the second interaction module; waiting for the falling edge of the end signal fed back by the bottom layer of the new module; when the falling edge of the end signal arrives, the start signal is set to 0, and the start signal is cleared.
In the second interactive Module, a start signal, an input signal, an output signal and a response end signal are connected to the first interactive Module in a modularized manner.
The specific second interactive module mainly comprises a definition part and an instantiation part,
the definition part includes REG definition enable signal and assigns invalid '0'; REG defines the input signal and assigns an initial value; wire definition end signal;
the instantiation part instantiates signals connected with the second Task Module into a Module file form, and specifically comprises input instantiation, start signal instantiation, output signal instantiation, end signal instantiation and input signal instantiation definition.
And through instantiation of the second interaction module, the second interaction module and the first interaction module are communicated.
The specific process of calling the first Task Module newly packaged into the Module package is as follows:
based on the Module packaging method, when the test platform TestBench is built, any section of code of a Module file at the bottom layer of a new Module packaged by the mature first Task Module is not required to be changed, only the Module file at the top layer of the Module is required, input signals and output results to be transmitted are defined according to a general packaging control method, and the mature Task Module can be called in the top-layer test excitation main flow Module, so that the code changing scale of directly calling the Task Module is effectively reduced, the calling difficulty of the mature TSK Module is reduced, only the input power transmission after packaging is required to be understood during application, the hidden global output quantity in the mature Task Module is not required to be understood, the overall difficulty of building the test platform is further reduced, and the efficiency of building the test platform is improved.
All modules in the device disclosed in the embodiment can be realized on the FPGA through Verilog voice.
In particular, the method comprises the steps of,
FIG. 3 shows an example of a Verilog voice implementation of the top-level incentive main flow module;
FIG. 4 shows an example of a Verilog voice implementation of the second Task module;
FIG. 5 shows an example of a Verilog voice implementation of the second interactive module;
FIG. 6 shows an example of a Verilog voice implementation of the first interactive module;
an example of a Verilog voice implementation of the response invocation module is shown in fig. 7.
The Verilog voice implementation example of each module is just an example of implementation of each module in this embodiment, and other ways of implementing the functions of each module in this embodiment on an FPGA chip are all within the scope of the present invention.
The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention.
Claims (10)
1. The module packaging method of the universal test platform TestBench is characterized by comprising the following steps of:
acquiring a first Task module to be repackaged;
the internal structure of the first Task Module is not changed, and the first Task Module is packaged into a bottom layer of a new Module in a Module file mode according to input and output signals of the first Task Module and set starting and stopping signals;
and setting a top layer Module on the top layer of the new Module, wherein the top layer Module is used for realizing communication between the outside of the new Module and the bottom layer, and calling the first Task Module in a mode of modularized calling.
2. The module packaging method according to claim 1, wherein a first interaction module and a response calling module are further packaged in a bottom layer of the new module;
the first interaction Module adds input, output, starting and ending signals to the first Task Module, and encapsulates the added signals into a Module file form for top-level calling;
the response calling module executes a first Task module by transmitting the input signal for a single time according to the starting signal, and the mark ending signal is valid after the execution of the first Task module is ended; and the output signal of the first Task module is output to the first interaction module through the response calling module or directly output to the first interaction module.
3. The module packaging method according to claim 2, wherein the response calling module repeatedly executes the first Task module without transmitting the input signal before the end signal flag is valid during the execution of the first Task module.
4. The Module packaging method according to claim 2, wherein the first interactive Module mainly comprises two parts, one part is used for setting time units and precision values, the other part is used for establishing a Module file for interacting with a top layer, and the Module file defines input ports, defines input start ports, defines output end ports, wire definition output signals, wire definition output end signals, REG defines bottom layer receiving signals and has invalid values of 0, an assignment connection output result and an assignment connection end signal.
5. The method of packaging a module of claim 2,
the execution method of the response calling module comprises the following steps:
1) Continuously judging whether the rising edge of the starting signal arrives or not;
2) When the rising edge of the starting signal comes, the ending signal is endowed with '1', and the ending signal is marked invalid;
3) Continuously judging the rising edge in the process of giving a '1' to the end signal;
4) After the rising edge of the ending signal comes, transmitting an input signal to execute a first Task module;
5) After the first Task module executes once, the end signal is assigned 0, and the end signal is marked as valid.
6. The method of packaging a module of claim 5,
in the response calling module, waiting for a rising edge of a starting signal through an always block; ending the invalid assignment of the signal, wherein the value is 0-1; the first Task module is executed by transmitting an input signal through the rising edge of the waiting ending signal of the always block; and after execution, effectively assigning a value to the end signal.
7. The module packaging method according to claim 2, characterized in that a second Task module and a second interaction module are included in a top module of the new module;
in the second Task module, an input signal and an output signal of the first Task module are packaged into the second Task module by using a calling mode of the first Task module, a starting signal is output, and the input signal, the output signal and a response ending signal are transmitted to the second interaction module;
in the second interactive Module, a start signal, an input signal, an output signal and a response end signal are connected to the first interactive Module in a modularized manner.
8. The method of claim 7, wherein a Task file is created in the second Task module, and a first Task module input signal is defined, so that a first Task module start signal is given a "1", and the start signal is enabled; transmitting the input signal of the first Task module to the second interaction module; waiting for the falling edge of the end signal fed back by the bottom layer of the new module; when the falling edge of the end signal arrives, the start signal is set to 0, and the start signal is cleared.
9. The module packaging method of claim 7, wherein the second interactive module comprises a definition portion and an instantiation portion;
the definition part comprises REG definition start signals and assigns invalid '0'; REG defines the input signal and assigns an initial value; wire definition end signal;
the instantiation part instantiates signals connected with the second Task Module into a Module file form, and specifically comprises input instantiation, start signal instantiation, output signal instantiation, end signal instantiation and input signal instantiation definition.
10. A module packaging apparatus based on the module packaging method of the universal test platform TestBench according to claim 1-9, characterized in that,
the system comprises a top layer test excitation main flow module, a top layer call starting module and a bottom layer general encapsulation module which are connected in sequence;
the bottom layer general encapsulation Module is used for encapsulating the first Task Module into a bottom layer of a new Module in a Module file mode according to input and output signals of the first Task Module and set starting and stopping signals without changing the internal structure of the first Task Module to be encapsulated again;
the top layer calling starting Module is connected between the top layer test excitation main flow Module and the bottom layer general packaging Module and is used for setting a top layer test Module file to realize communication between the top layer test excitation main flow Module and the bottom layer general packaging Module, and a first Task Module is called in a Module instantiation calling mode;
the top layer test excitation main flow module is used for transmitting an input signal for calling the first Task module to the top layer call starting module and receiving an output result fed back after the first Task module is called from the top layer call starting module.
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