CN101059773A - Bus model-based embedded system emulated platform - Google Patents
Bus model-based embedded system emulated platform Download PDFInfo
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Abstract
The invention relates to an embedded system simulate platform based on bus model, which leads in the embedded system flexible bus design theory, to realize the uniformity of various embedded system bottom structure, and use a system model language SystemC to build a processor host simulate model and an expansion interface board simulate model. The processor host simulate model comprises an embedded processor function model, an interface bus mission model or a SOC (on-chip system) function model, and an on-chip mission model. The invention uses software/hardware cooperate design and simulation integrated environment to realize the development of embedded system simulation model, and uses a real-time parallel simulation console to realize the parallel execution and detection of embedded system simulation model.
Description
(1) technical field:
The present invention relates to a kind of platform of realizing on multi-purpose computer that embedded computer system is carried out emulation, particularly a kind of complicated embedded system emulation platform that utilizes the embedded computer bus model to set up belongs to field of computer technology.
(2) background technology:
Embedded system is defined as " being embedded into the dedicated computer system in the object system "." embeddability ", " specificity " are three fundamentals of embedded system with " computer system ".Current, along with directions such as instrument system is integrated to function, miniature portable develop, embedded system has been goed deep into defence and military and each corner of civil electronic system.
Follow embedded system to be applied in expansion on the range and the excavation on the degree of depth, the task that people give embedded system is heavy day by day, and algorithm is complicated more, and reliability requirement is more and more higher, and the corresponding construction cycle is shorter and shorter.System emulation the early stage is carried out in design have been become and has evaded development risk, accelerates the important channel of research and development process.
But the diversity of object system makes embedded system present the isomerization characteristics, and its System Framework, interface specification, development mode all have uncertainty, and above factor causes numerous embedded system emulation to be in the following state of the art:
1) exploitation of embedded system mainly launches around embedded processor, and corresponding emulation tool, simulated environment all provide by embedded processor manufacturer is supporting.The emulation support that the design of embedded processor minimum system can improve, in a single day and expanded a plurality of interface boards, the dynamics that system-level emulation is supported just reduces rapidly.
2) based on the analogue system of PC owing to lack effective description means to hardware model, simulation work is confined to soft tasks such as proof of algorithm, effect demonstration, does not really bear the emulation mission that system architecture demonstration, interface realize reference.
3) analogue system is in the auxiliary products status usually, has both qualitative and specificity, is difficult to adapt to the needs that simulation object changes (especially architectural variations).
(3) summary of the invention:
A kind of embedded system emulation platform based on bus model of the present invention its objective is: for design, emulation, the checking of complicated embedded system provides technical support.
A kind of embedded system emulation platform of the present invention based on bus model, its technical scheme is: by introducing embedded system flexible bus 5, realize the unification of various embedded system bottom architecture, utilize system modelling language (SystemC) to set up processor main frame realistic model on this basis and extend out interface board realistic model 13; Wherein, processor main frame realistic model comprises that embedded processor functional mode 1 and interface bus transaction model 3 or SOC{SOC thereof are the abbreviations of System On Chip (SOC (system on a chip)) } functional mode 2 and on-chip bus transaction model 4 thereof; Exploitation by software/hardware collaborative design and emulation the integration environment 14 realization embedded system realistic models realizes the concurrent execution and the operation monitoring of embedded system realistic models by Real-time and Concurrent simulation console 15.
The system architecture of this emulation platform is by embedded processor functional mode 1 and interface bus transaction model 3 (or SOC functional mode 2 and on-chip bus transaction model 4 thereof), flexible bus 5, bus topology database 9, STD bus realistic model 10, extend out interface board functional entity 12 and extend out interface board realistic model more than 13 parts and form;
This flexible bus 5 is divided into the three-layer weave framework: bus adaptable interface 6, middle layer 7 and Standard bus interface 8; The each several part annexation is: embedded processor functional mode 1 (or SOC functional mode 2) is connected to bus adaptable interface 6 by interface bus transaction model 3 (or on-chip bus transaction model 4), bus adaptable interface 6 connects middle layer 7 and bus topology database 9 respectively, and middle layer 7 is connected with Standard bus interface 8; Standard bus interface 8 is connected to STD bus realistic model 10, extends out interface board functional entity 12 and is connected with Standard bus interface 8, extends out interface board realistic model 13 and is connected with STD bus realistic model 10;
This emulation platform is by software/hardware collaborative design and emulation the integration environment 14 and Real-time and Concurrent simulation console 15 collaborative realizations; This this software/hardware collaborative design and emulation the integration environment 14 include: bus topology database 9, driving data storehouse 16, model database 17, explorer 18, control desk run time version compiler 19, test file 20 and simulation report 21; This Real-time and Concurrent simulation console 15 includes: dispatch principal function 22, test load module 23, monitoring output module 24, SystemC simulation kernel and class libraries 25, STD bus realistic model 10 and extend out interface board realistic model 13; The each several part annexation is: bus topology database 9, driving data storehouse 16, model database 17 are connected to explorer 18, and explorer 18 is connected to control desk run time version compiler 19; Control desk run time version compiler 19 is connected to Real-time and Concurrent simulation console 15; Scheduling principal function 22 is connected with test load module 23, monitoring output module 24, SystemC simulation kernel and class libraries 25; Test file 20 output terminals are connected with test load module 23 input ends; Test load module 23 output terminals are connected with SystemC simulation kernel and class libraries 25 input ends; SystemC simulation kernel and class libraries 25 output terminals are connected with monitoring output module 24 input ends, and the input end of monitoring output module 24 output terminals and simulation report 21 is connected; SystemC simulation kernel and class libraries 25 are connected with STD bus realistic model 10;
System simulation platform is worked as follows:
Step 1: extend out interface board realistic model 13 with SystemC foundation, deposit model database 17 in; Set up the bus message list and the adaptive list of embedded processor interface bus (or SOC on-chip bus), deposit bus topology database 9 in; Set up embedded processor interface bus transaction model 3 (or SOC on-chip bus transaction model 4), deposit driving data storehouse 16 in;
Step 2: explorer 18 calls bus driver information from driving data storehouse 16, generates the bus driver file;
Step 3: 14 pairs of bus driver files of software/hardware collaborative design and emulation the integration environment carry out parameter resolves, and the result deposits test file 20 in;
Step 4: explorer 18 calls the model formulation file that extends out interface board realistic model 13 from model bank 17, and the calling interface bus message imports control desk run time version compiler 19 from bus topology database 9;
Step 5: control desk run time version compiler 19 connects scheduling principal function 22, test load module 23, monitoring output module 24, SystemC simulation kernel and class libraries 25, STD bus realistic model 10 and extends out interface board realistic model 13 statement file and interface bus information, and compiling generates Real-time and Concurrent simulation console 15;
Step 6: software/hardware collaborative design and emulation the integration environment 14 call 15 operations of Real-time and Concurrent simulation console, under the high frequency clock scheduling, and the bus driver signal of test load module 23 acceptance test files 20 inputs, the concurrent work of scheduling simulation system;
Step 7: monitoring output module 24 outputs to simulation report 21 with operation result, simultaneously the signal work wave is outputed to ModelSim SE wave display environment;
Step 8: carry out the simulation result analysis-by-synthesis in conjunction with simulation report 21 and signal waveform, satisfy then output model of system design index, do not satisfy and then carry out model modification, return execution in step 1.
A kind of embedded system emulation platform based on bus model of the present invention has following good effect and advantage:
1. emulation wide coverage can provide and stride level emulation from many plates system to gate level.
2. adopt the emulation mechanisms towards implementation model, have the hardware concurrent characteristic, modeling code portable is used for code.
3. emulation is supported nanosecond emulation in every possible way.
4. platform system structure is open, and function is cut out, expanded conveniently, has certain pervasive versatility.
(4) description of drawings:
Fig. 1 is the embedded system emulation platform system architecture diagram that the present invention is based on bus model.
Fig. 2 is that the embedded system emulation platform that the present invention is based on bus model is realized block diagram.
Fig. 3 is the embedded system emulation platform workflow diagram that the present invention is based on bus model.
Fig. 4 is the embedded system emulation platform explorer composition frame chart that the present invention is based on bus model.
Fig. 5 is the bus message list of Standard bus interface 8 of the present invention.
Number in the figure is as follows:
1 embeds processing capacity model 2SOC functional mode 3 interface bus transaction model
4 on-chip bus transaction model, 5 flexible bus, 6 bus adaptable interfaces
7 bus middle layers, 8 Standard bus interface, 9 bus topology databases
10 STD bus realistic models, 11 interfaces 1 12 extend out the interface board functional entity
13 extend out 14 software/hardware collaborative designs of interface board realistic model and emulation the integration environment
15 Real-time and Concurrent simulation consoles, 16 driving data storehouses, 17 model databases
18 explorers, 19 control desk run time version compilers, 20 test files
21 simulation reports, 22 scheduling principal functions, 23 test load modules
24 monitoring output module 25SystemC simulation kernel and class libraries
(5) embodiment:
A kind of embedded system emulation platform based on bus model of the present invention is further described the present invention below in conjunction with accompanying drawing and embodiment.
See also Figure 1 and Figure 2, its technical scheme is: by introducing embedded system flexible bus 5, realize the unification of various embedded system bottom architecture, utilize system modelling language (SystemC) design processor main frame realistic model to comprise embedded processor functional mode 1 and interface bus transaction model 3 thereof or (SOC functional mode 2 and on-chip bus transaction model 4 thereof) on this basis and extend out interface board realistic model 13.Realize the exploitation of embedded system realistic model by setting up software/hardware collaborative design and emulation the integration environment 14, realize the concurrent execution and the operation monitoring of embedded system realistic model by Real-time and Concurrent simulation console 15.
The system architecture of this emulation platform by embedded processor functional mode 1 and interface bus transaction model 3 (or SOC functional mode 2 and on-chip bus transaction model 4 thereof), flexible bus 5, bus topology database 9, STD bus realistic model 10, extend out interface board functional entity 12 and extend out interface board realistic model more than 13 parts and form.Flexible bus 5 is divided into the three-layer weave framework: bus adaptable interface 6, middle layer 7 and Standard bus interface 8.The each several part annexation is: embedded processor functional mode 1 (or SOC functional mode 2) is connected to bus adaptable interface 6 by interface bus transaction model 3 (or on-chip bus transaction model 4), bus adaptable interface 6 connects middle layer 7 and bus topology database 9 respectively, and middle layer 7 is connected with Standard bus interface 8.Standard bus interface 8 is connected to STD bus realistic model 10, extends out interface board functional entity 12 and is connected with Standard bus interface 8, extends out interface board realistic model 13 and is connected with STD bus realistic model 10.
Embedded processor functional mode 1 (or SOC functional mode 2) is based on the embedded processor functional mode (or integrated CPU, storer, IP kernel are in SOC (system on a chip) functional mode of one chip) of X86CPU, DSP, ARM, 51/96 single-chip microcomputer.Interface bus transaction model 3 (or on-chip bus transaction model 4) is under the jurisdiction of the above-mentioned functions model.
Embedded system flexible bus 5 is a research object with system bus (bus between the integrated circuit board), basic fundamental thought is that variety classes embedded processor (or SOC chip) peripheral bus is transformed into a Standard bus interface by bridged protocol, this Standard bus interface has defined the design specifications that extends out interface board, has guaranteed to have parts interchangeability and technology portability based on the various embedded system platforms of flexible bus.Flexible bus is divided into the three-layer weave framework: bus adaptable interface 6, middle layer 7 and Standard bus interface 8.
Bus adaptable interface 6 is application layers, by the bus topology information that bus topology database 9 provides, realizes the mapping of variety classes embedded processor peripheral bus to STD bus.The embedded system bus message is divided into address, data, control fundamental, and digital I/O, ADC interface, PWM interface, expansion such as communication interface key element.Bus topology database 9 comprises three kinds of lists: the bus message list of flush bonding processor interface bus, the bus message list of Standard bus interface 8 and adaptive list between the two.The bus message list column unanimity of the bus message list of flush bonding processor interface bus and Standard bus interface 8, comprise five of signal names, bit wide, attribute, position, remarks: signal name is 1-20 position English (containing numeral, a underscore) character string; Bit wide is the integer data; Attribute is IN, OUT, INOUT type codes (representing unidirectional input, unidirectional output, two-way input and output respectively); The position is the port numbers that is assigned to FPGA, the integer data.Remarks are the descriptive informations to signal, 1-256 position character string.
The bus message list of flush bonding processor interface bus is according to selecting for use the concrete situation of processor to determine, the bus message list sample of Standard bus interface 8 as shown in Figure 5:
Above-mentioned two kinds of lists carry out signal adaptation by adaptive list.Adaptive list is that of fitting relation describes set, fitting relation is divided into through-type and combined two kinds: straight-through adaptive the simple signal that transmits, for example the read signal of embedded processor and write signal can pass straight through to the S_RD and the S_WD signal of Standard bus interface 8, and essence is that a kind of position is adaptive.Making up a plurality of signals of adaptive needs cooperates, for example embedded processor is 32 bit data bus, and Standard bus interface definition is 16 bit data bus, and this moment, Standard bus interface should divide high 16 and low 16 to carry out two secondary data and read (or writing), and essence is a kind of protocol adaptation.
Three kinds of lists that bus adaptable interface 6 provides according to bus topology database 9 carry out location matches and agreement coupling with specific flush bonding processor interface bus, are configured to the Standard bus interface form of flexible bus.
Flexible bus STD bus model 10 is emulation extensions of flexible bus Standard bus interface 8, and signal definition is consistent with entity, and the bus behavior is described by system modelling language SystemC.
Based on bus model the embedded system emulation platform by software/hardware collaborative design and emulation the integration environment 14 and Real-time and Concurrent simulation console 15 collaborative realizations.Software/hardware collaborative design and emulation the integration environment 14 usefulness VC++6.0 write, adopt Microsoft Access software to set up bus topology database 9, driving data storehouse 16 and model database 17, under VC++, utilize connection and the visit of ADO (Active Database Object) realization to database, mainly finish the bus signals mapping, systemic-function is cut apart, mutual collaborative design, functions such as simulated program generation, be the upper development environment of emulation platform, comprise bus topology database 9, driving data storehouse 16, model database 17, explorer 18, control desk run time version compiler 19, test file 20 and simulation report 21; Real-time and Concurrent simulation console 15 is the Win32 ConsoleApplication executive routines under the VC++ environment, write realization with system modelling language SystemC 2.1, generate by upper development environment compiling, be the realization body of emulation platform, comprise scheduling principal function 22, test load module 23, monitoring output module 24, SystemC simulation kernel and class libraries 25, STD bus realistic model 10 and extend out interface board realistic model 13.The each several part annexation is: bus topology database 9, driving data storehouse 16, model database 17 are connected to explorer 18, and explorer 18 is connected to control desk run time version compiler 19.Control desk run time version compiler 19 is connected to Real-time and Concurrent simulation console 15.Scheduling principal function 22 is connected with test load module 23, monitoring output module 24, SystemC simulation kernel and class libraries 25.Test file 20 output terminals are connected with test load module 23 input ends.Test load module 23 output terminals are connected with SystemC simulation kernel and class libraries 25 input ends.SystemC simulation kernel and class libraries 25 output terminals are connected with monitoring output module 24 input ends, and the input end of monitoring output module 24 output terminals and simulation report 21 is connected.SystemC simulation kernel and class libraries 25 are connected with STD bus realistic model 10.
See also shown in Figure 3, should details are as follows based on the workflow of the embedded system emulation platform of bus model;
Step 1: extend out interface board realistic model 13 with SystemC foundation, deposit model database 17 in; Set up the bus message list and the adaptive list of embedded processor interface bus (or SOC on-chip bus), deposit bus topology database 9 in; Set up embedded processor interface bus transaction model 3 (or SOC on-chip bus transaction model 4), deposit driving data storehouse 16 in.
Extend out interface board model 13 except that the behavior of structure bus interface, comprise that also detail circuits realizes information.With the matrix switch board model is example, and it comprises circuit such as address decoding, the choosing of ranks sheet, Data Receiving, output driving describes, and with the circuit code equivalence of functional entity, the degree of refinement of model description depends on the design needs.
Embedded system main frame model adopts functional processor model 1+ bus transaction model 3 (or SOC functional mode 2+ on-chip bus transaction model 4) structure, carries out individual event by upper development environment and selects for use or make up and select for use.Embedded processor functional mode 1 (or SOC functional mode 2) adopts SystemC to make up component logic such as processor calculating, storage, scheduling, this model need to be applied to the situation of special concern processor behavior details, after the bus topology conversion, exist with the realistic model form that is articulated on the flexible bus STD bus.Because realize the details relative complex, the present invention does not deeply describe, use following alternative method and advocate:
From the embedded system principle of work, interface bus is the realization place of processor scheduling total system behavior, therefore agreement is come emulation processor scheduling behavior to interface bus injection instruction sequence chronologically, in other words, embedded processor functional mode 1 (or SOC functional mode 2) can be by interface bus transaction model 3 (or SOC on-chip bus transaction model 4) equivalent substitution.The interface bus transaction model is set up by upper development environment, particularly be parameters such as definition signal classification, signal changing value, signal duration as bus driver information, exist in the driving data storehouse 16.In the emulation platform use,, have the temporal constraint standard in addition, grasp the user is difficult because it is more abstract to drive writing of file.For this reason, design an explorer 18 and realize writing fast of bus driver, composition frame chart is seen Fig. 4.
Step 2: explorer 18 calls bus driver information from driving data storehouse 16, generates the bus driver file.Its form is exemplified below (expand number in the 2nd be signal duration, unit nanosecond):
main()
{
[task 1] bus address (0x320,20)
[task 2] total line traffic control (2,10)
[task 3] bus data (0,10)
[task 4] bus address (0x220,20)
[task 5] total line traffic control (2,10)
[task 6] bus data (0xff00,13)
……
}
Step 3: 14 pairs of bus driver files of software/hardware collaborative design and emulation the integration environment carry out parameter resolves, and the result deposits test file 20 in.Test file 20 is texts, and data are divided into groups by the function dependence, and each parameter group is by the ordering of emulation sequential relationship.Driving file with step 2 is an example, test file data layout following (B represents scale-of-two, and D represents the decimal system):
B D B D B D
1100100000 20 10 10 0 10
1000100000 20 10 10 1111111100000000 13
……
Step 4: explorer 18 calls the model formulation file that extends out interface board realistic model 13 from model bank 17, and the calling interface bus message imports control desk run time version compiler 19 from bus topology database 9.
Step 5: control desk run time version compiler 19 calls the VC++ compiler, connect scheduling principal function 22, test load module 23, monitoring output module 24, SystemC simulation kernel and class libraries 25, STD bus realistic model 10 and extend out interface board realistic model 13 statement file and interface bus information, compiling generates Real-time and Concurrent simulation console 15.
Step 6: software/hardware collaborative design and emulation the integration environment 14 call 15 operations of Real-time and Concurrent simulation console, under the high frequency clock scheduling, by emulation beat demand, test load module 23 is the cycle with the reference clock saltus step, operational testing file 20 pointers, input parameter in groups, Real-time and Concurrent simulation console 15 each module are pressed the concurrent work of clock beat.
Step 7: 24 high frequency clocks with nanosecond of monitoring module are trigger condition along saltus step, the variation of responsive policing port or signal, realistic model change information and time of origin are outputed to simulation report 21, simultaneously the signal work wave is outputed to ModelSim SE wave display environment.
Step 8: carry out the simulation result analysis-by-synthesis in conjunction with simulation report 21 and signal waveform, satisfy then output model of system design index, do not satisfy and then carry out model modification, return execution in step 1.
Claims (4)
1. embedded system emulation platform based on bus model, it is characterized in that: by introducing embedded system flexible bus (5), realize the unification of various embedded system bottom architecture, utilize system modelling language SystemC to set up processor main frame realistic model on this basis and extend out interface board realistic model (13); This processor main frame realistic model comprises embedded processor functional mode (1) and interface bus transaction model (3) or SOC functional mode (2) and on-chip bus transaction model (4) thereof; Exploitation by software/hardware collaborative design and emulation the integration environment (14) realization embedded system realistic model realizes the concurrent execution and the operation monitoring of embedded system realistic model by Real-time and Concurrent simulation console (15).
2. a kind of embedded system emulation platform based on bus model according to claim 1 is characterized in that: the system architecture of described emulation platform by embedded processor functional mode (1) and interface bus transaction model 3 or SOC functional mode (2) and on-chip bus transaction model (4), flexible bus (5), bus topology database (9), STD bus realistic model (10), extend out interface board functional entity (12) and extend out several parts of interface board realistic model (13) and form;
This flexible bus (5) is divided into the three-layer weave framework: bus adaptable interface (6), middle layer (7) and Standard bus interface (8); The each several part annexation is: embedded processor functional mode (1) or SOC functional mode (2) are connected to bus adaptable interface (6) by interface bus transaction model (3) or on-chip bus transaction model (4), bus adaptable interface (6) connects middle layer (7) and bus topology database (9) respectively, and middle layer (7) are connected with Standard bus interface (8); Standard bus interface (8) is connected to STD bus realistic model (10), extends out interface board functional entity (12) and is connected with Standard bus interface (8), extends out interface board realistic model (13) and is connected with STD bus realistic model (10).
3. a kind of embedded system emulation platform based on bus model according to claim 1 is characterized in that: described emulation platform is by software/hardware collaborative design and emulation the integration environment (14) and the collaborative realization of Real-time and Concurrent simulation console (15); Software/hardware collaborative design and emulation the integration environment (14) comprise bus topology database (9), driving data storehouse (16), model database (17), explorer (18), control desk run time version compiler (19), test file (20) and simulation report (21); Real-time and Concurrent simulation console (15) comprises scheduling principal function (22), test load module (23), monitoring output module (24), SystemC simulation kernel and class libraries (25), STD bus realistic model (10) and extends out interface board realistic model (13); The each several part annexation is: bus topology database (9), driving data storehouse (16), model database (17) are connected to explorer (18), and explorer (18) is connected to control desk run time version compiler (19); Control desk run time version compiler (19) is connected to Real-time and Concurrent simulation console (15); Scheduling principal function (22) is connected with test load module (23), monitoring output module (24), SystemC simulation kernel and class libraries (25); Test file (20) output terminal is connected with test load module (23) input end; Test load module (23) output terminal is connected with SystemC simulation kernel and class libraries (25) input end; SystemC simulation kernel and class libraries (25) output terminal is connected with monitoring output module (24) input end, and the input end of monitoring output module (24) output terminal and simulation report (21) is connected; SystemC simulation kernel and class libraries (25) are connected with STD bus realistic model (10).
4. a kind of embedded system emulation platform according to claim 1 based on bus model, it is characterized in that: described emulation platform is worked as follows:
Step 1: extend out interface board realistic model (13) with SystemC foundation, deposit model database (17) in; Set up embedded processor interface bus or SOC on-chip bus) bus message list and adaptive list, deposit bus topology database (9) in; Set up embedded processor interface bus transaction model (3) or SOC on-chip bus transaction model (4), deposit driving data storehouse (16) in;
Step 2: explorer (18) calls bus driver information from driving data storehouse (16), generates the bus driver file;
Step 3: software/hardware collaborative design and emulation the integration environment (14) carry out parameter to the bus driver file resolves, and the result deposits test file 20 in;
Step 4: explorer (18) calls the model formulation file that extends out interface board realistic model (13) from model bank (17), and the calling interface bus message imports control desk run time version compiler (19) from bus topology database (9);
Step 5: control desk run time version compiler (19) connects scheduling principal function (22), test load module (23), monitoring output module (24), SystemC simulation kernel and class libraries (25), STD bus realistic model (10) and extends out interface board realistic model (13) statement file and interface bus information, and compiling generates Real-time and Concurrent simulation console (15);
Step 6: software/hardware collaborative design and emulation the integration environment (14) call Real-time and Concurrent simulation console (15) operation, under the high frequency clock scheduling, the bus driver signal of test load module (23) acceptance test file (20) input, the concurrent work of scheduling simulation system;
Step 7: monitoring output module (24) outputs to simulation report (21) with operation result, simultaneously the signal work wave is outputed to display environment;
Step 8: carry out the simulation result analysis-by-synthesis in conjunction with simulation report (21) and signal waveform, satisfy then output model of system design index, do not satisfy and then carry out model modification, return execution in step (1).
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| CN103293964B (en) * | 2013-03-22 | 2016-06-22 | 中国航空工业集团公司沈阳飞机设计研究所 | A kind of dynamo-electric non-bus, the simulation excitation of bus signals and integrated test facility |
| CN103293964A (en) * | 2013-03-22 | 2013-09-11 | 中国航空工业集团公司沈阳飞机设计研究所 | Simulation excitation and comprehensive testing method for electromechanical non-bus signals and bus signals |
| CN104932905A (en) * | 2015-07-14 | 2015-09-23 | 北京神舟航天软件技术有限公司 | Automatic code generation method from AADL to C language |
| CN106154865B (en) * | 2016-07-01 | 2019-08-06 | 中国汽车技术研究中心 | A kind of vehicle bus simulation model self-generating method and system |
| CN106154865A (en) * | 2016-07-01 | 2016-11-23 | 中国汽车技术研究中心 | A kind of vehicle bus phantom self-generating method and system |
| CN106354515B (en) * | 2016-09-26 | 2019-11-01 | 杭州杉石科技有限公司 | SystemC code generating system based on model |
| CN106354515A (en) * | 2016-09-26 | 2017-01-25 | 杭州杉石科技有限公司 | SystemC code generation system based on model |
| CN108255724A (en) * | 2018-01-17 | 2018-07-06 | 北京网信云服信息科技有限公司 | A kind of test method and system of affairs participant |
| CN110134561A (en) * | 2019-05-20 | 2019-08-16 | 北京嘉楠捷思信息技术有限公司 | Method and device for outputting debugging information in software and hardware collaborative verification |
| CN110134561B (en) * | 2019-05-20 | 2023-07-14 | 嘉楠明芯(北京)科技有限公司 | Method and device for outputting debugging information in software and hardware collaborative verification |
| CN111161524A (en) * | 2019-12-11 | 2020-05-15 | 北京东方计量测试研究所 | Testing device |
| CN112989740A (en) * | 2021-04-23 | 2021-06-18 | 北京欣博电子科技有限公司 | Simulation method and device, computer equipment and storage medium |
| CN113779791A (en) * | 2021-09-08 | 2021-12-10 | 广东博智林机器人有限公司 | Simulation system, method and device and electronic equipment |
| CN113779791B (en) * | 2021-09-08 | 2024-02-06 | 广东博智林机器人有限公司 | Simulation system, simulation method, simulation device and electronic equipment |
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