CN1482661A - Emulate testing system and testing method for universal digital circuit - Google Patents
Emulate testing system and testing method for universal digital circuit Download PDFInfo
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- CN1482661A CN1482661A CNA021430179A CN02143017A CN1482661A CN 1482661 A CN1482661 A CN 1482661A CN A021430179 A CNA021430179 A CN A021430179A CN 02143017 A CN02143017 A CN 02143017A CN 1482661 A CN1482661 A CN 1482661A
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Abstract
The invention discloses a general purpose digital circuit simulated test system and test method thereof, wherein the system comprises a data source for generating test excitation data, a bus functional module BFM for mapping the excitation data into time sequence in accordance with the bus standard, and at least a two-way measurement unit, while the corresponding method comprises sending the time sequence of the excitation data to the test design, and performing two-way test in parallel, thus enhancing the versatility of the simulation test and improving the code multiplexing ratio and expandability.
Description
Technical field
The present invention relates to the emulation testing of general digital circuit design.
Background technology
Usually, the design of integrated circuit is that the logic demand that will will finish is mapped to the required file of some productions, as net table, domain etc., emulation testing to design is before producing, utilize computer that the output of design phase is checked, promptly utilize EDA (Electronic DesignAutomatic) tool software analog integrated circuit to produce the operating position of back on the side circuit plate, can reduce production risk effectively like this.In the design of ASIC (application-specific integrated circuit (ASIC) Application Specific Integrated Circuit) and FPGA (field programmable logic array Field Programmable Gate Array), emulation testing has become the bottleneck problem of whole design at present.Emulation testing workload proportion generally meets or exceeds 70% in the ASIC of complexity and FPGA project, and along with the increase of design scale, the scale of testing authentication increases with square multiplying power.
The method of Design of Digital Circuit emulation testing is at first to want the form of the feature list of clear and definite design DUT to be measured (Design Under Test), data flow that it is supported and the sequential of DUT outside port in the prior art.Make up the excited data of test usefulness then according to the form of data flow; This excited data is carried out the outcome expectancy of circuit output according to the DUT feature list; Simultaneously excited data is introduced DUT according to the port sequential from the end of going into of DUT data flow, gather the end that of DUT data flow at last, will export the result and expected results compares, thereby reach the purpose of testing authentication.Figure 1 shows that the structural principle of the Design of Digital Circuit emulation test system that adopts said method, excited data advances DUT through bus functional model 1 input; Simultaneously excited data is carried out algorithm process according to the function of DUT, obtain the output expection of DUT; Bus functional model 2 is gathered the output of DUT, and gives comparison module relatively with the output result of DUT.
The shortcoming that above-mentioned prior art exists is:
One, in the test code, processing module and excited data module correlation are strong.If the excited data module needs change, then processing module must be done corresponding change, otherwise test macro can't continue operation.
Two, the poor expandability of whole test environment.The test code that carries out module testing can't be directly multiplexing in chip testing; The code that carries out chip testing can't be directly multiplexing in system testing; The code of native system test can't be directly multiplexing in another system testing.
Three, in the existing method of testing, test code and DUT are an integral body, and both constitute the simulated environment that can move jointly, have broken away from physical circuit, and test environment can't independent operating.So, the debugging difficult point of the debugging of test code itself and DUT all concentrates on the uniting and adjustment stage in design later stage, bring very big risk for whole design, and design scale is big more, and risk is then big more.
Summary of the invention
The objective of the invention is to deficiency, provide a kind of highly versatile, rate of code reuse and extensibility high general digital circuit emulation test system and method for testing at the prior art existence.
For achieving the above object, the technical solution used in the present invention is: a kind of general digital circuit emulation test system, this system is by the data source that is used to produce test stimulus data, form bus functionality module BFM and at least one double-channel testing unit that excited data is mapped as sequential by bus standard, described double-channel testing unit is by being designed into end and going out to hold the measurement circuit of setting out on a journey that is connected to constitute with following drive test examination circuit with to be measured respectively, wherein
The composition of measurement circuit of setting out on a journey is: go into to hold the bus monitor module with what the signal sequence of bus was mapped as unit data, according to the unit data of going into to hold the output of bus monitor module design to be measured is carried out algorithm simulating to obtain exporting the processing unit of expected data, to exporting the memory cell that expected data is stored, go out to hold the bus monitor module with what the bus signals sequential of designing end to be measured was mapped as unit data, the comparing unit that the expected data of memory cell and the unit data that goes out to hold the bus monitor module are compared;
The composition of following drive test examination circuit is: go into to hold the bus monitor module with what the signal sequence of bus was mapped as unit data, according to the unit data of going into to hold the output of bus monitor module design to be measured is carried out algorithm simulating to obtain exporting the processing unit of expected data, to exporting the memory cell that expected data is stored, the expected data of memory cell is selected the scheduling unit of output, the dateout of scheduling unit is mapped as signal sequence and deliver to be measured design the end bus go out to hold the bus functionality module.
The method of testing of above-mentioned emulation test system is: at first produce test stimulus data by data source, by bus standard excited data is mapped as sequential by bus functionality module BFM again, then this sequential is carried out set out on a journey test and the following drive test examination parallel with design to be measured;
The described test of setting out on a journey comprises the steps:
A1, be mapped as unit data by the signal sequence of going into to hold the bus monitor module with bus;
A2, treated unit carry out algorithm simulating to obtain exporting expected data according to the unit data of going into to hold the output of bus monitor module to design to be measured;
A3, will export the expectation storage in memory cell;
A4, the unit data that the expected data of memory cell and the bus signals sequential that goes out to hold the bus monitor module will to be measuredly design end is shone upon by comparing unit compare;
The examination of described drive test down comprises the steps:
B1, be mapped as unit data by the signal sequence of going into to hold the bus monitor module with bus;
B2, treated unit carry out algorithm simulating to obtain exporting expected data according to the unit data of going into to hold the output of bus monitor module to design to be measured;
B3, will export the expectation storage in memory cell;
B4, the expected data of memory cell is selected output by scheduling unit; B5, be mapped as signal sequence and deliver to the end bus of designing to be measured by the dateout that goes out to hold the bus functionality module with scheduling unit.
Adopt the present invention program, can bring following advantage:
1, can make unit testing, integration testing, chip testing and system testing have unified test structure, the test code of being convenient between the different stage is shared, and accelerates testing progress, reduces the test risk.
2, make the correlation between each module of test code reduce, all data all by the bus read-write, are isolated mutually, the person of the going into division of labor when being convenient to large scale test and code uniting and adjustment, maintenance;
3, bus monitor module and bus functionality module are carried out content inverse process and inspection mutually each other, improve the stability of code;
4, owing to adopt two-channel structure, test code can break away from design to be measured, independent operating, and it is stable to be convenient to test code.
Description of drawings
Fig. 1 is a Design of Digital Circuit emulation test system structure principle chart in the prior art;
Fig. 2 is an emulation test system structure principle chart of the present invention;
Fig. 3 is the two-stage test system structure figure in the concrete enforcement of the present invention.
Embodiment
Below in conjunction with accompanying drawing the present invention program is described further.
With reference to Fig. 2, general digital circuit emulation test system of the present invention is by the data source that is used to produce test stimulus data, form bus functionality module BFM1 and at least one double-channel testing unit that excited data is mapped as sequential by bus standard, described double-channel testing unit is by being designed into end and going out to hold the measurement circuit of setting out on a journey that is connected to constitute with following drive test examination circuit with to be measured respectively, wherein
The composition of measurement circuit of setting out on a journey is: go into to hold bus monitor module BMM1 with what the signal sequence of bus was mapped as unit data, according to the unit data of going into to hold the output of bus monitor module design to be measured is carried out algorithm simulating to obtain exporting the processing unit of expected data, to exporting the memory cell that expected data is stored, go out to hold bus monitor module BMM2 with what the bus signals sequential of designing end to be measured was mapped as unit data, the comparing unit that the expected data of memory cell and the unit data that goes out to hold the bus monitor module are compared;
The composition of following drive test examination circuit is: go into to hold bus monitor module BMM1 with what the signal sequence of bus was mapped as unit data, according to the unit data of going into to hold the output of bus monitor module design to be measured is carried out algorithm simulating to obtain exporting the processing unit of expected data, to exporting the memory cell that expected data is stored, the expected data of memory cell is selected the scheduling unit of output, the dateout of scheduling unit is mapped as signal sequence and deliver to be measured design the end bus go out to hold bus functionality module BFM2.
The method of testing of above-mentioned emulation test system is: at first produce test stimulus data by data source, by bus standard excited data is mapped as sequential by bus functionality module BFM again, then this sequential is carried out set out on a journey test and the following drive test examination parallel with design to be measured;
The described test of setting out on a journey comprises the steps:
A1, be mapped as unit data by the signal sequence of going into to hold the bus monitor module with bus;
A2, treated unit carry out algorithm simulating to obtain exporting expected data according to the unit data of going into to hold the output of bus monitor module to design to be measured;
A3, will export the expectation storage in memory cell;
A4, the unit data that the expected data of memory cell and the bus signals sequential that goes out to hold the bus monitor module will to be measuredly design end is shone upon by comparing unit compare;
The examination of described drive test down comprises the steps:
B1, be mapped as unit data by the signal sequence of going into to hold the bus monitor module with bus;
B2, treated unit carry out algorithm simulating to obtain exporting expected data according to the unit data of going into to hold the output of bus monitor module to design to be measured;
B3, will export the expectation storage in memory cell;
B4, the expected data of memory cell is selected output by scheduling unit;
B5, be mapped as signal sequence and deliver to the end bus of designing to be measured by the dateout that goes out to hold the bus functionality module with scheduling unit.
Figure 3 shows that the two-stage emulation test system that comprises two double-channel testing unit.In the circuit design of reality, a system often is made up of a plurality of chips, and a chip may be made up of a plurality of modules again.So, complete emulation testing should comprise unit testing, integration testing, chip testing, system testing.Unit testing is a module testing; Integration testing is the joint test between the correlation module; Chip testing is the joint test to all modules in the chip; System testing is the joint test of all chips.
In the circuit design of reality, the scale between each chip, between each module is widely different sometimes.So the design deadline of module and chip has nothing in common with each other.Such as, certain system is made up of DUT_U1 and two design parts to be measured of DUT_U2.The flow direction of packet is: processing finishes in DUT_U1 earlier, by DUT_U1 result is exported to DUT_U2, the design of DUT_U2 may be finished prior to DUT_U1 in the real work, at this class situation, can adopt the emulation test system of Fig. 3, this system comprises two double-channel testing unit, with the output of DUT_U1 in the higher level's double-channel testing unit input as DUT_U2 in the subordinate double-channel testing unit.Just the BMM2 that goes out to hold of higher level DUT is the BMM2 that the DUT of subordinate goes into end just.Because the present invention has adopted the test cell of two-channel structure, making is not having under the situation of DUT_U1, but higher level's test cell independent operating still, and cooperate the test of finishing DUT_U2, effectively reduce the excessive risk of joint test.In two-channel structure, check mutually between the two-way, also be convenient to the stable and maintenance of test code.
The rest may be inferred, by the combination of a plurality of double-channel testings unit, can carry out various unit testings, integration testing, chip testing and system testing, and the extensibility of rate of code reuse and test macro improves greatly.
Claims (2)
1, a kind of general digital circuit emulation test system, it is characterized in that: this system is by the data source that is used to produce test stimulus data, form bus functionality module BFM and at least one double-channel testing unit that excited data is mapped as sequential by bus standard, described double-channel testing unit is by being designed into end and going out to hold the measurement circuit of setting out on a journey that is connected to constitute with following drive test examination circuit with to be measured respectively, wherein
The composition of measurement circuit of setting out on a journey is: go into to hold the bus monitor module with what the signal sequence of bus was mapped as unit data, according to the unit data of going into to hold the output of bus monitor module design to be measured is carried out algorithm simulating to obtain exporting the processing unit of expected data, to exporting the memory cell that expected data is stored, go out to hold the bus monitor module with what the bus signals sequential of designing end to be measured was mapped as unit data, the comparing unit that the expected data of memory cell and the unit data that goes out to hold the bus monitor module are compared;
The composition of following drive test examination circuit is: go into to hold the bus monitor module with what the signal sequence of bus was mapped as unit data, according to the unit data of going into to hold the output of bus monitor module design to be measured is carried out algorithm simulating to obtain exporting the processing unit of expected data, to exporting the memory cell that expected data is stored, the expected data of memory cell is selected the scheduling unit of output, the dateout of scheduling unit is mapped as signal sequence and deliver to be measured design the end bus go out to hold the bus functionality module.
2, a kind of general digital circuit emulation test method, it is characterized in that: at first produce test stimulus data by data source, by bus standard excited data is mapped as sequential by bus functionality module BFM again, then this sequential is carried out set out on a journey test and the following drive test examination parallel with design to be measured;
The described test of setting out on a journey comprises the steps:
A1, be mapped as unit data by the signal sequence of going into to hold the bus monitor module with bus;
A2, treated unit carry out algorithm simulating to obtain exporting expected data according to the unit data of going into to hold the output of bus monitor module to design to be measured;
A3, will export the expectation storage in memory cell;
A4, the unit data that the expected data of memory cell and the bus signals sequential that goes out to hold the bus monitor module will to be measuredly design end is shone upon by comparing unit compare;
The examination of described drive test down comprises the steps:
B1, be mapped as unit data by the signal sequence of going into to hold the bus monitor module with bus;
B2, treated unit carry out algorithm simulating to obtain exporting expected data according to the unit data of going into to hold the output of bus monitor module to design to be measured;
B3, will export the expectation storage in memory cell;
B4, the expected data of memory cell is selected output by scheduling unit;
B5, be mapped as signal sequence and deliver to the end bus of designing to be measured by the dateout that goes out to hold the bus functionality module with scheduling unit.
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| CN 02143017 CN1235278C (en) | 2002-09-11 | 2002-09-11 | Emulate testing system and testing method for universal digital circuit |
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| CN 02143017 CN1235278C (en) | 2002-09-11 | 2002-09-11 | Emulate testing system and testing method for universal digital circuit |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1332537C (en) * | 2004-09-14 | 2007-08-15 | 华为技术有限公司 | Device and its method for monitoring excited message |
| CN100337212C (en) * | 2004-07-22 | 2007-09-12 | 华为技术有限公司 | Logic verification system and method |
| CN100349416C (en) * | 2004-12-01 | 2007-11-14 | 华为技术有限公司 | Method and device for controlling excited data flow, and excited message producer |
| CN100383798C (en) * | 2005-09-07 | 2008-04-23 | 深圳市海思半导体有限公司 | Stimulating platform and method for random storage package file |
| CN100399341C (en) * | 2006-03-31 | 2008-07-02 | 电子科技大学 | Software and hardware synergistic simulation/ validation system and vector mode simulation/ validation method |
| CN100440812C (en) * | 2004-04-23 | 2008-12-03 | 华为技术有限公司 | Apparatus and method for implementing excitation message and method for testing digital circuit logical simulation |
| CN100535868C (en) * | 2005-12-28 | 2009-09-02 | 中国科学院微电子研究所 | Real-time simulation development system and method therefor |
| CN102087678A (en) * | 2011-01-07 | 2011-06-08 | 清华大学 | Circuit simulation method for realizing parallel computation through time domain division |
| CN101739473B (en) * | 2008-10-22 | 2011-11-09 | 盛群半导体股份有限公司 | Circuit emulator |
| CN103020367A (en) * | 2012-12-20 | 2013-04-03 | 上海高清数字科技产业有限公司 | Tester of demultiplexer and test method of the demultiplexer |
| CN107885181A (en) * | 2016-09-30 | 2018-04-06 | 上海复旦微电子集团股份有限公司 | The test system of DSP unit in field programmable gate array chip |
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| CN100370466C (en) * | 2006-03-01 | 2008-02-20 | 华为技术有限公司 | Simulation method and system for logic circuit |
| CN100428252C (en) * | 2006-09-14 | 2008-10-22 | 华为技术有限公司 | System and method for testing and measuring percentage of coverage of function |
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2002
- 2002-09-11 CN CN 02143017 patent/CN1235278C/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100440812C (en) * | 2004-04-23 | 2008-12-03 | 华为技术有限公司 | Apparatus and method for implementing excitation message and method for testing digital circuit logical simulation |
| CN100337212C (en) * | 2004-07-22 | 2007-09-12 | 华为技术有限公司 | Logic verification system and method |
| CN1332537C (en) * | 2004-09-14 | 2007-08-15 | 华为技术有限公司 | Device and its method for monitoring excited message |
| CN100349416C (en) * | 2004-12-01 | 2007-11-14 | 华为技术有限公司 | Method and device for controlling excited data flow, and excited message producer |
| CN100383798C (en) * | 2005-09-07 | 2008-04-23 | 深圳市海思半导体有限公司 | Stimulating platform and method for random storage package file |
| CN100535868C (en) * | 2005-12-28 | 2009-09-02 | 中国科学院微电子研究所 | Real-time simulation development system and method therefor |
| CN100399341C (en) * | 2006-03-31 | 2008-07-02 | 电子科技大学 | Software and hardware synergistic simulation/ validation system and vector mode simulation/ validation method |
| CN101739473B (en) * | 2008-10-22 | 2011-11-09 | 盛群半导体股份有限公司 | Circuit emulator |
| CN102087678A (en) * | 2011-01-07 | 2011-06-08 | 清华大学 | Circuit simulation method for realizing parallel computation through time domain division |
| CN103020367A (en) * | 2012-12-20 | 2013-04-03 | 上海高清数字科技产业有限公司 | Tester of demultiplexer and test method of the demultiplexer |
| CN103020367B (en) * | 2012-12-20 | 2016-01-20 | 上海高清数字科技产业有限公司 | A kind of verifier of demodulation multiplexer and the method for inspection thereof |
| CN107885181A (en) * | 2016-09-30 | 2018-04-06 | 上海复旦微电子集团股份有限公司 | The test system of DSP unit in field programmable gate array chip |
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