CN100535868C - Real-time simulation development system and method therefor - Google Patents
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Abstract
The invention relates to super large scale integrated circuit. Particularly a timely simulation development system. The simulation verification development starts with deciding the computation and actual running index of the designed hardware module, calling algorithm simulation base to realize algorithm function simulation, generating wanted stimulating signal from the software system, based on which to control the hardware system entering into computation status, with the data flow generating module generating timely data flow signal, the data handling module capturing module coordination and returns by the signal capturing module to the software system, which is used for signal after treatment and analysis based on the computation result of the hardware. The system and method mainly faces high capacity radar, phono-telemeter, military software wireless cable timely signal handling, for RTSP hardware installation and RTSP chip simulation verification for the design of relevant fields.
Description
Technical field
The present invention relates to the real time digital signal Treatment Design technical field of VLSI (very large scale integrated circuit) (VLSI), Department of Electronics's irrespective of size (ESL).Particularly a kind of real-time simulation development system and method thereof.
Background technology
Usually, the RTSP hardware unit that is applied to fields such as high-end radar, sonar, software radio (SDR), digital image processing is compared with the universal signal treating apparatus of Industry Control, consumer electronics field, has following remarkable difference: dynamic range index height, the data bit format change is bigger: the fixed point of existing standard, floating-point also has other off-gauge fixed point and block floating point; Computing index height needs the hardware handles device to handle in real time data stream usually; Data throughput index height needs very big bit wide to realize the dynamic range that it is higher usually; Real-time operation causes the real time data amount of input and output big, thereby requires hardware unit that the real-time Data Transmission ability of big bandwidth can be provided.As the RTSP chip of RTSP core component, must have the characteristics of above 3 aspects simultaneously.The simulating, verifying of RTSP hardware unit and high-performance RTSP chip is the Important Project technological challenge that RTS research staff faced always.
It is grade simulated that the main means that can realize the scheme evaluation of RTSP hardware unit and RTSP chip and fast exploitation at present comprise that instruments such as utilizing system level signals simulation software: Matlab, SPW, SystemView, Cocentric carries out system algorithm; Utilize high performance signal to handle integrated circuit board structure real system and finish scheme evaluation and exploitation fast; Utilize the high-speed hardware emulation accelerator Xtreme-I of devices at full hardware emulator such as Verisity (existing) by Cadence corporate buyout.
The advantage of simulation software is that algorithm simulating is convenient, powerful, but lacks corresponding hardware co-verification ability, and the data bit format change that exists in the design of actual hardware device also lacks flexibly in simulation software to be supported; Can make up the hardware unit of comparatively perfect simulation, digital signal processing link with the high-performance integrated circuit board, realize the exploitation of rapid system level, but indifferent to the simulating, verifying of High Performance DSP processor.Advantage with the devices at full hardware emulator is that simulation velocity is fast, and precision is higher, but that shortcoming is with the co-verification interface of algorithm level is dumb, lacks the ability of system-level co-verification.Devices at full hardware emulator, high performance signal with high target handled integrated circuit board, the signal processing software price is all very expensive.
Summary of the invention
Fundamental purpose of the present invention is that the simulating, verifying for high-performance RTSP hardware unit and RTSP chip provides a development system and method, utilize this system and method for designing, can carry out scheme evaluation and exploitation fast with lower Costco Wholesale realization high-performance RTSP hardware unit and RTSP chip design exploitation.
High performance signal processing hardware device algorithm complexity, the form that the present invention is directed to radar, sonar, SDR is changeable, data transmission throughput height, the intensive characteristics of bringing the simulating, verifying complexity of computing, has designed a software and hardware co-emulation verification system that is made of software module and hardware unit and based on the simulating, verifying flow and method of this system.
Software module provides the software architecture of procedure, and the connection interface of procedure provides working method directly perceived and succinct for the user.Multiple exciting signal sources such as the normal signal with true pattern consistent with the hardware unit precision, radar signal are provided; The system architecture of behavioral scaling and the multi-level collaborative simulation of hardware level can make software module can carry out multi-level algorithm simulating.Signal Processing storehouse and realistic model all can be provided with the data layout of emulated data, thereby finish the accurate analog simulation to the actual hardware operational precision.
Hardware unit is divided by function, by live signal data stream generation device, and the RTSP arithmetic unit, live signal data stream acquisition equipment constitutes.Three kinds of hardware units are realized by Bussing connector.
Index request according to real time data stream, the speed buffering circuit restructural of live signal data stream generation device, live signal data stream acquisition equipment is different circuit structure, real time data stream less than 4096 conditions under, utilize two-port RAM to constitute impact damper; Real time data stream greater than 4096 situations under, then utilize two-port RAM or DDRSDRAM to constitute the impact damper of 2048Mb amount of capacity.Thereby can produce high degree of parallelism, big bandwidth, jumbo real time data stream, reach the data transfer bandwidth corresponding to requirement required with the RTSP computing.
The software module of PC is sent steering order by the pci bus interface drive unit to Digital I pumping signal generating apparatus and Digital I pumping signal acquisition equipment, make each hardware unit enter the initial launch state, and make live signal data stream generation device store the pumping signal that receives into Ddrsdram, realize that the Real-time and Dynamic of data pumping signal generates.Simultaneously, live signal data stream acquisition equipment can and send back software service by the high-speed PCI interface with the operation result captured in real time and analyzes and aftertreatment for software systems.Configurable pci interface logic is realized the data communication of hardware system and software systems, and the resulting operation result of hardware unit is transmitted the part module that eases back, and makes things convenient for system to carry out co-verification.
The present invention is mainly towards the high-performance RTSP field of VLSI and radar, sonar, SDR, the real time signal processing of Military Software Radio (SDR), thus the simulating, verifying that can be used in RTSP hardware unit and RTSP chip provides better scheme evaluation and quick means and the method for developing for the association area designer.
In many-sided advantages such as performance, versatility, extended capability, costs, make it have good scientific research, engineering, economical and practical value.
Technical scheme
The true development system in a kind of real-time position, it is characterized in that: development system is made of software module and hardware unit, hardware unit comprises: Digital I pumping signal generating apparatus and coupled pci bus interface drive unit, calculation process plate Digital I operation result acquisition equipment and coupled pci bus interface drive unit, the calculation process plate is interconnected with digital I/O board pumping signal generating apparatus and digital I/O board operation result acquisition equipment respectively.
Software module comprises: algorithm simulating and signal post-processing device, hardware pumping signal generating apparatus and hardware operation result acquisition equipment, algorithm simulating and signal post-processing device are connected to hardware pumping signal generating apparatus and hardware operation result acquisition equipment, finish accurate emulation based on the bit emulator model, and the required pumping signal of generation hardware unit operation, hardware unit is finished the real-time simulation validation of signal processing algorithm under the control of software module.
The true development system in described real-time position, hardware unit adopts restructural and modular hardware structure.Hardware unit is by live signal data stream generation device, high-speed dsp arithmetic unit and live signal data stream acquisition equipment constitute, wherein live signal data stream generation device is made of Digital I pumping signal generating apparatus and pci bus interface drive unit, the high-speed dsp arithmetic unit is made of the calculation process plate, live signal data stream acquisition equipment is made of Digital I operation result acquisition equipment and pci bus drive unit, live signal data stream generation device, the interconnected of high-speed dsp arithmetic unit and live signal data stream acquisition equipment realizes that by Bussing connector hardware unit has reconfigurable hardware characteristics according to simulating, verifying and cost needs.
The true development system in described real-time position, the restructural characteristics of hardware unit are meant live signal data stream generation device and real time data stream acquisition equipment, has size according to real time data stream, be configured as the high-speed buffer structure of different buffer capacities, real time data stream less than 4096 conditions under, utilize two-port RAM to constitute impact damper; Real time data stream greater than 4096 situations under, then utilize two-port RAM or DDRSDRAM to constitute the impact damper of 2048Mb amount of capacity.
The true development system in described real-time position, system has the characteristics of software and hardware cooperating simulation checking, be that software module realizes the algorithm simulating based on the position true mode, the actual hardware of hardware unit implementation algorithm moves, and realizes that by the pci bus interface drive unit hardware service data is back to software module does the post analysis processing.
The present invention is applied in 4,500,000 hypervelocity dsp chip Speed emulation of Chinese Academy of Sciences Microelectronics Institute development and rapid prototype development system.Utilize that applied main algorithm FFT/IFFT, FIR in the radar signal processor that this system can finish the Speed chip, time domain are relevant, the pulse compression scheduling algorithm has carried out real-time simulation hardware, The actual running results shows that signal Processing software and hardware cooperating simulation development platform can be carried out the simulation analysis of a true pattern to multiple signal processing algorithm when this was true.Can carry out real-time Data Transmission and Data Receiving with the data bandwidth of 6.4Gbps.Can realize the core processing algorithm of typical radar signal processor is carried out real-time software and hardware cooperating simulation checking.
Description of drawings
Fig. 1 development system general frame figure.
The software module Organization Chart of Fig. 2 development system.
Fig. 3 algorithm level emulation synoptic diagram.
The structure composition diagram of Fig. 4 hardware unit.
Fig. 5 fast data buffer circuit structure diagram.
The high speed acquisition buffer circuit figure of Fig. 6 ping-pong structure.
Fig. 7 method step process flow diagram of the present invention.
Embodiment
The present invention is based on the system framework of Fig. 1 and operational mode and at the characteristics of high-performance RTSP simulating, verifying difficulty and the software and hardware system structure of particular design has well solved the technical barrier of aspects such as the high-speed computation processing, software and hardware cooperating simulation checking of the accurate emulation of algorithm, actual hardware, provide a kind of practicality and the engineering of software and hardware cooperating simulation checking efficiently solution.
Fig. 2 is the software module framework of development system, and software module provides a kind of procedure mode of operation of succinct practicality.The menu bar structure of module is top-down pattern, (pattern setting-operation setting-test and excitation-algorithm simulating-emulation drawing-co-verification-hardware debug-performance comparison-Performance Evaluation-run abort), corresponding actual software module workflow realizes the procedure operation control of system.Operation setting, algorithm simulating, emulation drawing realize the emulation to the behavioral scaling of specific algorithm, position true hardware map level emulation.
Fig. 3 is an algorithm level emulation synoptic diagram, and the algorithm simulating of system is made accurate assessment by multiple arithmetic accuracy form is set to each operating index of algorithm.Operation provides the consistent required excitation of operation to the test and excitation part with simulation hardware at algorithm simulating.Hardware debug is partly finished to the operation control of hardware unit and by pci interface and is realized passing mutually with the data of hardware unit.
Fig. 4 is the structure composition diagram of hardware unit, can see among the figure that hardware unit is made of following 3 parts: live signal data stream generation device, high-speed dsp arithmetic unit, live signal data stream acquisition equipment.The core circuit of live signal data stream generation device and live signal data stream acquisition equipment is the design of inner high speed data buffer circuit.
The High Performance DSP processing module need to be processed in real time to high-speed data-flow usually; Therefore need live signal data flow generation device and live signal data flow acquisition equipment that very high data throughput can be provided; Investigation to the high-speed dsp processor shows: the operating frequency of bus IO is usually operated at below the 100Mhz; In the present invention's design; The operating frequency of bus IO can be with the operating frequency work of the highest 100Mhz; The present invention can have 100 data passages to produce parallel data flow simultaneously; Thereby obtain the transient data stream of Gb/s
Can two kinds of methods be arranged for the DSP processor provides continuous Large Volume Data stream, the 1st, transient behavior produces the required data of computing, the 2nd, in advance the test data excitation is stored in the high-speed memory, when normally moving exciting signal source is loaded in the DSP processor module continuously.Hardware logic directly produces various pumping signal exploitation difficulties big limitation, more is to adopt the 2nd kind of method.The present invention utilizes the high speed DDR-SDRAM of MICRO company to finish the design of high speed data buffer in conjunction with the hardware logic of particular design, can provide memory capacity for the data I plate up to 256MB (2048Mb) capacity, its design maximum bandwidth is 128b*100M=12.8Gb, and can provide storage depth with the data bandwidth pattern of 128Mb is the storage depth of 16M.Can satisfy the demand of most High Performance DSP processor pair high-speed caches.
Fig. 5 is the fast data buffer circuit diagram, and it mainly is divided into real-time collection SampleIN, master control logic MainCtr, high-speed data storer Ddrsdram, dual-port impact damper Dpram.PCI logic module, high speed data transfer local side module, although DDR-SDRAM can provide very high data transmission throughput, but because it is a dynamic storage, need regularly memory cell to be refreshed, therefore, can not finish the transmission of Large Volume Data all the time with identical frequency of operation, and the data transmission of real time data stream must operate at all the time under the identical frequency of operation.In order to solve this contradiction, the present invention utilizes dual-ported memory and store control logic to make up high-speed real-time acquisition buffer device based on the table tennis principle.
Fig. 6 is the high-speed real-time collector circuit diagram of ping-pong structure.Utilize the collaborative work of double buffering and DDR-SDRAM effectively to realize the continuous transmission of high capacity real time data stream.When required fast data buffer district data volume is lower than at 4096, then hardware configuration reconstruct can be designed to only constitute the fast data buffer district to reach the purpose of saving cost by dual-port impact damper Dpram.
Live signal data stream generation module has identical hardware structure with live signal data stream trapping module, for versatility, the reduction design cost of realizing simplifying hardware design, improving module, all use identical hardware configuration to design with live signal data stream trapping module live signal data stream generation module, and realize the data capture function by the steering logic of revising the control hardware structure.
Signal processing apparatus is the calculation process part of hardware unit, from Fig. 5, can see that signal processing module provides abundant additional subsidiary function, bag expands ATX power interface, jtag interface, clocked logic, reseting logic, bus buffer, auxiliary steering logic etc.If device is that the DSP device is carried out simulating, verifying, bus provides 100 input channels and 100 output channels.By the inputoutput data passage, realize the interconnected of 3 sub-devices.
If desired the high performance signal computing module of signal processor is verified, can provide multiple signal processing module by this standard interface form, the signal Processing computing module that the Speed chip that utilizes Microelectronics Institute to design voluntarily at present constitutes can realize on the basis of simple programming that the high performance signal of FFT/IFFT, FIR, SLIP is handled the pre-service computing.Conveniently system-level user carries out the quick exploitation and the Performance Evaluation of signal Processing computing module fast.If the user needs more high performance ARRAY PROCESSING ability, can under the condition that does not change interface shape, the Speed chip cascade be handled.When other functional module of needs, then can use FPGA, general dsp, ASIC to constitute certain functional modules such as functions such as up-conversion, down coversion, modulation, codings.Thereby set up the various signal Processing computing modules storehouse of comparatively finishing.
Fig. 7 is as described below based on its job step of emulation verification method of this system,
Step 1, determine the algorithm and the operating index of design and simulation checking target, in the mode of operation setup menu bar of software module, determine the pattern (behavioral scaling emulation, the emulation of hardware map level) of simulating, verifying, and to the data layout in the simulation process, frequency of operation, sampling parameter such as count is done concrete setting, compares with traditional simulation software, and be one of remarkable advantage of having of platform based on the accurate emulation of actual hardware data bit form.
Step 2 is called the algorithm simulating storehouse, the functional simulation of implementation algorithm.Algorithm simulating mainly is that the algoritic module or the hardware map level realistic model that call in the software algorithm storehouse are finished the actual emulation computing, compare with traditional simulation software, system provides parameter that interface is set, in the grade simulated phase process of behavior, the operational precision of algoritic module can be set, the computing dynamic range.The true hardware map level stage on the throne, by calling the C language algorithm model of actual hardware based on the Cycle level, thereby on data precision and the sequential the accurate duty of simulation actual hardware system.
Step 3 generates the required pumping signal of hardware unit emulation by software module.System provides abundant signal library, mainly is divided into standard signal, radar signal, signal of communication, customization signal.And signal library provides standard extension interface so that carry out signal extension.To all signals, can the signalization sampling count sampling frequency, data layout.And as required, the signal after quantizing can be stored in the wave file with binary form, for simulation hardware produces required signal excitation.
Step 4, according to the instruction of software module, the control hardware device enters compute mode.The software module of PC is sent steering order by the pci bus interface drive unit to hardware unit, makes each hardware unit enter the initial launch state, and makes live signal data stream generation device store the pumping signal that receives into Ddrsdram.
Step 5, under the control action of software module, the data stream generation device, signal processing apparatus, the collaborative work of signal capture device, working condition by data stream generation device simulation actual hardware sends real time data stream to signal processing apparatus, and by the signal capture device real time data stream of catching is sent back software module by pci interface.
Step 6 according to the data that send back, is carried out correctness comparison, precision analysis, Performance Evaluation by software module to the signal processing results that sends back.
Step 2 and step 5 are keys of the present invention, and step 2 utilizes the true pattern setting in system true signal storehouse, peculiar position and position to finish multi-level algorithm simulating.Step 5 utilizes the processing power of the high data throughput of system hardware device and signal processing apparatus to finish the simulation hardware of system.
Claims (4)
1, the true development system in a kind of real-time position, it is characterized in that: development system is made of software module and hardware unit, hardware unit comprises: Digital I pumping signal generating apparatus and coupled pci bus interface drive unit, calculation process plate and Digital I operation result acquisition equipment and coupled pci bus interface drive unit, the calculation process plate is connected with Digital I operation result acquisition equipment with Digital I pumping signal generating apparatus respectively
Software module comprises: algorithm simulating and signal post-processing device, hardware pumping signal generating apparatus and hardware operation result acquisition equipment, algorithm simulating and signal post-processing device are connected to hardware pumping signal generating apparatus and hardware operation result acquisition equipment, finish accurate emulation based on the bit emulator model, and the required pumping signal of generation hardware unit operation, hardware unit is finished the real-time simulation validation of signal processing algorithm under the control of software module.
2, the true development system in real-time position according to claim 1, it is characterized in that: the restructural characteristics of hardware unit are meant live signal data stream generation device and real time data stream acquisition equipment, has size according to real time data stream, be configured as the high-speed buffer structure of different buffer capacities, real time data stream less than 4096 conditions under, utilize two-port RAM to constitute impact damper; Real time data stream greater than 4096 situations under, then utilize two-port RAM to constitute the impact damper of 2048Mb amount of capacity in conjunction with DDRSDRAM.
3, the true development system in real-time position according to claim 1, it is characterized in that: system has the characteristics of software and hardware cooperating simulation checking, be that software module realizes the algorithm simulating based on the position true mode, the actual hardware of hardware unit implementation algorithm moves, and realizes that by pci interface the hardware service data is back to software module does the post analysis processing.
4, a kind of method of the true development system in real-time position based on claim 1, its concrete steps are as follows:
Step 1 is determined the algorithm and the operating index of design and simulation checking target;
Step 2 is called the algorithm simulating storehouse, the functional simulation of implementation algorithm;
Step 3 generates the required pumping signal of hardware unit emulation by software module;
Step 4, according to the instruction of software module, the control hardware device enters compute mode;
Step 5, the data stream generation device, signal processing apparatus, the collaborative work of signal capture device, and by the signal capture device operation result is turned back in the software module;
Step 6, software module is carried out aftertreatment and analysis and evaluation according to the hardware unit operation result.
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| CN101504690B (en) * | 2009-03-26 | 2011-04-13 | 北京航空航天大学 | Real-time simulation validation system and method for communication system integrated circuit design |
| CN101630343B (en) * | 2009-08-18 | 2011-07-13 | 中兴通讯股份有限公司 | Simulation method and simulation system |
| WO2012167536A1 (en) * | 2011-11-02 | 2012-12-13 | 华为技术有限公司 | Method and system for multi-thread collaborative simulation |
| CN102867087A (en) * | 2012-09-11 | 2013-01-09 | 西安电子科技大学 | Graphical radar signal processing high-level integrated design platform and method |
| CN104331282B (en) * | 2014-10-28 | 2017-10-31 | 电子科技大学 | A kind of radio products restructural comprehensive exploitation test system |
| CN109190210B (en) * | 2018-08-17 | 2020-05-12 | 电子科技大学 | Circuit performance reliability analysis method based on Saber platform modeling simulation |
| CN110716537B (en) * | 2019-11-19 | 2021-02-19 | 北京润科通用技术有限公司 | Simulation test method and device |
| CN112328495B (en) * | 2020-11-27 | 2024-04-26 | 上海移远通信技术股份有限公司 | Testing system and testing method for module function |
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