CN101630343B - Simulation method and simulation system - Google Patents
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- CN101630343B CN101630343B CN2009101661814A CN200910166181A CN101630343B CN 101630343 B CN101630343 B CN 101630343B CN 2009101661814 A CN2009101661814 A CN 2009101661814A CN 200910166181 A CN200910166181 A CN 200910166181A CN 101630343 B CN101630343 B CN 101630343B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
Abstract
The invention discloses a simulation method and a simulation device. The simulation method is used for developing a hardware device drive and/or business software and comprises the following steps: setting a hardware interface abstraction module, wherein the hardware interface abstraction module is used for providing a real visit interface for the hardware device drive and/or business software; setting a central processing unit (CPU) interface abstraction module, wherein the CPU interface abstraction module is used for connecting with a chip simulation model to generate a time sequence according with the chip simulation model; and performing message interaction between the hardware interface abstraction module and the CPU interface abstraction module. The invention can enable the drive and the business software to be transplanted to a real soft hardware environment in a seamless way, realizes the parallel development, and quickens the project development schedule.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of emulation mode and system.
Background technology
Integrated circuit or field programmable gate array (Field Programable Gate Array, abbreviate FPGA as) all need under the support of driving and business software, could realize its specific function, in the chip development simulation stage, how to realize driving the configuration management function with business software, determined the adequacy and the completeness of chip emulation.
At present, conventional way is in the functional development stage, adopt register transfer language (Register Transfer Language, abbreviate RTL as) or SYSTEMC descriptive language coding, analog-driven and business software function, finish initialization, configuration and management, finish the functional simulation and the checking of chip chip.In the hardware debug stage, realize real the driving and business software at the target software environment.
This method can satisfy that function is few, the simple relatively chip emulation demand of configuration management.But, for extensive and function complex chip, realize that with RTL the work of the business software consistent with actual functional capability is a huge job, in converting actual driving and business software process to, can consume the extensive work amount once more.Fine difference between simulator program and the actual software, the problem that will run in the time of will causing hardware debug can't be in simulated environment reproduction.The exploitation of simultaneously true drive software need just can be finished in the hardware stage, caused the prolongation of construction cycle.
At present, in the chip emulation stage, lack complete cross-platform software-hardware synergism development approach in the correlation technique.
Summary of the invention
The problem big at the workload in the chip development simulation stage in the correlation technique, that debugging is complicated, the construction cycle is long and propose the present invention, for this reason, fundamental purpose of the present invention is to provide a kind of simulating scheme, one of to address the above problem at least.
To achieve these goals, according to an aspect of the present invention, provide a kind of emulation mode.
According to emulation mode of the present invention, be used for the exploitation of hardware device drivers and/or business software, comprise: the hardware interface abstract module is set, the hardware interface abstract module is used for hardware operation is packaged into the system call consistent with destination software systems, for hardware device drivers and/or business software provide real access interface; Central processor CPU interface abstract module is set, and the cpu i/f abstract module is used for being connected with the chip emulation model, produces the sequential that meets the chip emulation model; Hardware interface abstract module and cpu i/f abstract module carry out message interaction.
Preferably, the hardware interface abstract module is connected by virtual bus with the cpu i/f abstract module, and carries out message interaction by virtual bus.
Preferably, the hardware interface abstract module is connected by virtual bus with the cpu i/f abstract module and comprises alternately: the hardware interface abstract module is connected by communications protocol with the cpu i/f abstract module, and mutual data are packaged into the packet of the desired form of communications protocol between hardware interface abstract module and the cpu i/f abstract module.
Preferably, hardware interface abstract module and cpu i/f abstract module comprise alternately by virtual bus: the hardware interface abstract module receives the read/write command from hardware device drivers, and will be according to the following packet that produces one of at least read/write command: the type of the length of the data of the address of read/write command, read/write command correspondence, the data of read/write command correspondence; The hardware interface abstract module sends packet by virtual bus to the cpu i/f abstract module.
Preferably, hardware interface abstract module and cpu i/f abstract module comprise alternately by virtual bus: when the hardware interface abstract module receives write order from hardware device drivers, the hardware interface abstract module becomes packet with the data encapsulation to be written of write order correspondence, and sends to the cpu i/f abstract module by virtual bus.
Preferably, hardware interface abstract module and cpu i/f abstract module comprise alternately by virtual bus: the hardware interface abstract module obtains message from the cpu i/f abstract module by virtual bus, wherein, when message when reading return command, then finish the read request of hardware device drivers, and return the pairing data of read request; When order for from the read command of external unit the time, then directly initiate direct storage register and visit the DMA read operation, after the data that read the read command correspondence, return the data that read to external unit; When order for from the write order of external unit the time, then directly initiate the DMA write operation, with the data write memory of write order correspondence.
Preferably, communications protocol comprises transmission control protocol.
To achieve these goals, according to a further aspect in the invention, provide a kind of analogue system.
According to analogue system of the present invention, the exploitation that is used for hardware device drivers and/or business software comprises: the hardware interface abstract module, be used for hardware operation is packaged into the system call consistent with destination software systems, for hardware device drivers and/or business software provide real access interface; The cpu i/f abstract module is connected with the chip emulation model, is used to produce the sequential that meets the chip emulation model; Hardware interface abstract module and cpu i/f abstract module carry out message interaction.
Preferably, said system also comprises: virtual bus is used for connection hardware interface abstract module and cpu i/f abstract module, and carries out message interaction between hardware interface abstract module and cpu i/f abstract module.
Preferably, virtual bus specifically is used for by communications protocol connection hardware interface abstract module and cpu i/f abstract module, and mutual data encapsulation between hardware interface abstract module and the cpu i/f abstract module is become the packet of the desired form of communications protocol.
By the present invention, employing is provided with to the upper strata and provides hardware operation that hardware interface abstract module, hardware abstraction interface module are set and be connected to the chip emulation model of hardware interface abstract module, solved the problem that the workload in the chip development simulation stage in the correlation technique is big, debugging is complicated, the construction cycle is long, make driving and business software can seamlessly be transplanted to actual hardware environment, realize concurrent development, and then accelerated the project development progress.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the process flow diagram according to the emulation mode of the embodiment of the invention;
Fig. 2 is the synoptic diagram one according to module in the emulation mode of the embodiment of the invention;
Fig. 3 is the synoptic diagram two according to module in the emulation mode of the embodiment of the invention;
Fig. 4 is a synoptic diagram of forming structure according to the data message on the virtual bus of the embodiment of the invention;
Fig. 5 handles the functional flow diagram that drives hardware operation according to the hardware interface abstract module of the embodiment of the invention;
Fig. 6 is the processing flow chart according to message between the hardware interface abstract module of the embodiment of the invention and the virtual bus;
Fig. 7 is a process flow diagram of handling virtual bus message message according to the hardware interface abstract module of the embodiment of the invention;
Fig. 8 is a process flow diagram of handling on-chip bus or direct storage register accessing operation request of chip exterior bus and Interrupt Process according to the hardware interface abstract module of the embodiment of the invention;
Fig. 9 is the structured flowchart according to the analogue system of the embodiment of the invention.
Embodiment
Functional overview
The problem that workload in the chip development simulation stage in the correlation technique is big, debugging is complicated, the construction cycle is long, the embodiment of the invention provides a kind of simulating scheme, between realistic model and software environment, set up communication by this scheme, software is transferred in the emulation platform the hardware access demand finishes by model, direct storage register visit (Directory Memory Access the abbreviates DMA as) operation of interrupt message that the result of model execution simultaneously and model produce and model passes to be replaced to software environment.Virtual bus has shielded the realization details of hardware, provides a real hardware environment to software, realizes virtual and unification true environment.The treatment principle of this scheme is as follows: the hardware interface abstract module is set, and the hardware interface abstract module is used to hardware device drivers and/or business software that real access interface is provided; Central processor CPU interface abstract module is set, and the cpu i/f abstract module is used for being connected with the chip emulation model, produces the sequential that meets the chip emulation model; Hardware interface abstract module and cpu i/f abstract module carry out message interaction.
Need to prove that under the situation of not conflicting, embodiment and the feature among the embodiment among the application can make up mutually.Describe the present invention below with reference to the accompanying drawings and in conjunction with the embodiments in detail.
In following examples, can in computer system, carry out in the step shown in the process flow diagram of accompanying drawing such as a set of computer-executable instructions, and, though there is shown logical order in flow process, but in some cases, can carry out step shown or that describe with the order that is different from herein.
Method embodiment
According to embodiments of the invention, a kind of emulation mode is provided, be used for the exploitation of hardware device drivers and/or business software, Fig. 1 is the process flow diagram according to the emulation mode of the embodiment of the invention, as shown in Figure 1, this flow process comprises the steps that S102 is to step S106:
Step S102 is provided with the hardware interface abstract module, and the hardware interface abstract module is used to hardware device drivers and/or business software that real access interface is provided;
Step S104 is provided with central processor CPU interface abstract module, and the cpu i/f abstract module is used for being connected with the chip emulation model, produces the sequential that meets the chip emulation model;
Step S106, hardware interface abstract module and cpu i/f abstract module carry out message interaction.
In step S106, the hardware interface abstract module is connected by virtual bus with the cpu i/f abstract module, and carries out message interaction by virtual bus.
The hardware interface abstract module is connected by communications protocol with the cpu i/f abstract module, mutual data are packaged into the packet of the desired form of communications protocol between hardware interface abstract module and the cpu i/f abstract module, from the following aspects this are described in detail below.
Aspect one, the hardware interface abstract module receives the read/write command from hardware device drivers, and will be according to the following packet that produces one of at least read/write command: the type of the length of the data of the address of read/write command, read/write command correspondence, the data of read/write command correspondence; The hardware interface abstract module sends packet by virtual bus to the cpu i/f abstract module.
Aspect two, when the hardware interface abstract module received write order from hardware device drivers, the hardware interface abstract module became packet with the data encapsulation to be written of write order correspondence, and sends to the cpu i/f abstract module by virtual bus.
Aspect three, the hardware interface abstract module obtains message from the cpu i/f abstract module by virtual bus, wherein, when message when reading return command, then finish the read request of hardware device drivers, and return the pairing data of read request; When order for from the read command of external unit the time, then directly initiate direct storage register and visit the DMA read operation, after the data that read the read command correspondence, the read operation of returning to external equipment; When mentioned order is write order from external unit, then directly initiate the DMA write operation, with the data write memory of write order correspondence.
Preferably, communications protocol comprises transmission control protocol.
From four aspects present embodiment is described in detail below.
Aspect one
At target software (promptly, business software) hardware interface abstract module of environment bottom layer realization, this hardware interface abstract module drives (promptly the upper strata, hardware device drivers) and business software basic hardware operation is provided, wherein, hardware operation can include but not limited to: to the copy of the blocks of data during hardware register read and write access, Installed System Memory and the target, response hardware interrupts function etc., this module is used for hardware operation is packaged into the system call consistent with destination software systems, so that the hardware device drivers on upper strata and/or business software call.And in the actual hardware environment, this hardware interface abstract module is replaced by the hardware operation that actual hardware provides, actual hardware interface is PCI or LOCAL BUS, therefore, only need the driving of development interface, the driving and the business software that are positioned on the basic hardware operation need not to revise and can directly use.
Aspect two
Also relate to a cpu i/f abstract module that is connected with the chip emulation model in the present embodiment.This cpu i/f abstract module is connected to the chip internal on-chip bus or is directly connected to the outer CPU interface bus of chip, realizes visit and control to internal unit.Mask CPU side interface hardware details, be directly connected to software development environment.
Aspect three
In the exploitation of reality, operating system platform commonly used has vxworks, linux, and windows mobile system etc., model emulation software commonly used has Modelsim, Ncsim, SystemC etc.Therefore, various emulation platforms need be in the operation of different operating system environment, Windows for example, Linux etc.Can adopt Transmission Control Protocol to realize cross-platform communication, but be not limited only to this communication protocol, for example, if emulation and software environment are moved on same computing machine, also can adopt to share between memory mode implementation process and communicate by letter, perhaps, adopt specialized hardware to realize cross-platform communication in the higher occasion of communicating requirement.
Aspect four
Between hardware interface abstract module and cpu i/f abstract module, can adopt communication protocol to carry out communication, this communication protocol is packaged into the cpu i/f abstract module that data packet transmission is given chip emulation platform to the operation of the basic hardware of hardware interface abstract module, gives realistic model and carries out.Be transferred to the hardware interface abstract module again after the data that need return to software platform are packaged into bag by the cpu i/f abstract module, be transferred to software by basic hardware abstraction interface module.The look-at-me state of model also is packaged into data packet transmission and gives the hardware interface abstract module, gives interrupt service routine and carries out.
Describe the present invention below in conjunction with drawings and Examples.
Fig. 2 is the synoptic diagram one according to module in the emulation mode of the embodiment of the invention, as shown in Figure 2, comprise: business software 101, hardware device driver 102 (promptly, hardware device drivers), hardware interface abstract module 103, cpu i/f abstract module 104, virtual bus 105, chip exterior bus 106 and chip emulation environment 107.
Fig. 3 is the synoptic diagram two according to module in the emulation mode of the embodiment of the invention, as shown in Figure 3, comprise: business software 101, hardware device driver 102, hardware interface abstract module 103, cpu i/f abstract module 104, virtual bus 105, chip on-chip bus 106 and chip emulation environment 107, different with Fig. 2 is that the cpu i/f abstract module directly links to each other with internal bus in Fig. 3.Based on Fig. 2 and Fig. 3 present embodiment is described below.
Business software 101 among Fig. 2 and Fig. 3 is the application software that realize the chip functions correspondence, and its function realizes being structured on the basis of hardware device driver 102.Hardware device driver 102 has encapsulated the realization details of hardware, and different hardware is realized being packaged into unified interface.Hardware device driver 102 calls basic hardware and operates control and the visit that realizes hardware.To chip newly developed, need develop whole hardware device drivers 102 and partial service software 101. again
Fig. 2 and hardware interface abstract module among Fig. 3 are used for communicating by letter between hardware driving and realistic model.To driving side, the actual hardware behavior of this interface simulation provides the hardware operation interface, and adopts virtual bus 105 to be connected with chip emulation environment 107, if actual veneer then adopts actual bus to be connected to chip.
The message that cpu i/f abstract module 104 receives from virtual bus 105, and produce the sequential that meets the chip interface requirement, thus realize visit to chip exterior or internal bus 106.
Wherein, virtual bus 105 is certain cross-platform means of communication, the mode of its order and The data package is transmitted, Fig. 4 is a synoptic diagram of forming structure according to the data message on the virtual bus of the embodiment of the invention, as shown in Figure 4, hardware operation is converted into heading and optional data division, and heading comprises a type of message, for example, write order, read command, read return command, interruption status update command etc.For write order and read return command, the back needs corresponding data division, and its length is determined by the length field in the heading.Defined an origing address field (OAF) in addition.But the order meeting according to hardware supported during actual the realization increases and decreases to some extent.
Cpu i/f abstract module 104 and hardware interface abstract module 103 need produce corresponding order and data according to the requirement of hardware, software, and the data of returning are handled.Below in conjunction with Fig. 5 to Fig. 8 to being described in detail.
Fig. 5 handles the functional flow diagram that drives hardware operation according to the hardware interface abstract module of the embodiment of the invention, as shown in Figure 5, if hardware interface abstract module 103 receives from hardware device drivers (promptly, Drive Layer) read write command, can be according to the address of read write command, data length and type produce corresponding heading and send to cpu i/f abstract module 104 by virtual bus, if write order also sends to cpu i/f abstract module 104 to data to be written by virtual bus 105 again.
Fig. 6 is the processing flow chart according to message between the hardware interface abstract module of the embodiment of the invention and the virtual bus, and as shown in Figure 6, hardware interface abstract module 103 is also constantly monitored the message packet from virtual bus.If read return command, then finish all requests of Drive Layer, return data; If, then directly initiate dma operation from the read write command of external unit (peripheral hardware), write operation is directly write specified memory to data, read operation then from interior access data, is finished the peripheral hardware read operation.If from peripheral hardware be that interruption status is switched, then whether decision carries out the interrupt service routine of driver according to the look-at-me state.
Fig. 7 is a process flow diagram of handling virtual bus message message according to the hardware interface abstract module of the embodiment of the invention, Fig. 8 is a process flow diagram of handling on-chip bus or dma operation request of chip exterior bus and Interrupt Process according to the hardware interface abstract module of the embodiment of the invention, as shown in Figure 7 and Figure 8, cpu i/f abstract module function is similar substantially with the hardware interface function, for identical not repeating them here, different is, the cpu i/f module only can produce the interruption status update command, and the hardware interface abstract module only can respond interrupt request.The hardware interface abstract module provides interface to drive software, does not have sequential, and the cpu i/f abstract module needs to communicate by letter with the chip interface model, and its interface sequence must meet design requirement.
In sum, by Fig. 2 and Fig. 3 as seen,, only need replace the hardware interface abstract module, and other software modules are identical with hardware interface drivers if adopt real hardware single board debugging software.Therefore, can realize only need increase the driving of actual hardware interface when being transplanted in the actual hardware system, and hardware driving and business software can seamlessly being transplanted by present embodiment based on driving on the realistic model basis and business software exploitation.
System embodiment
According to embodiments of the invention, a kind of analogue system is provided, be used for the exploitation of hardware device drivers and/or business software, Fig. 9 is the structured flowchart according to the analogue system of the embodiment of the invention, as shown in Figure 9, this system comprises: hardware interface abstract module 92, cpu i/f abstract module 94 are described in detail this system below.
Hardware interface abstract module 92 is used to hardware device drivers and/or business software that real access interface is provided; Cpu i/f abstract module 94 is connected with the chip emulation model, is used to produce the sequential that meets the chip emulation model; Hardware interface abstract module and cpu i/f abstract module carry out message interaction.
As shown in Figure 8, this system also comprises virtual bus, and this virtual bus is used for connection hardware interface abstract module and cpu i/f abstract module, and carries out message interaction between hardware interface abstract module and cpu i/f abstract module.
Virtual bus specifically is used for by communications protocol connection hardware interface abstract module and cpu i/f abstract module, and mutual data encapsulation between hardware interface abstract module and the cpu i/f abstract module is become the packet of the desired form of communications protocol.
In sum, by the above embodiment of the present invention, can realize making things convenient for the emulation and the debugging of chip functions based on the driving of model and the exploitation of business software; Simultaneously, the hardware driving of exploitation and business software can seamlessly be transplanted in the actual hardware environment, thereby have realized concurrent development, have accelerated the project development progress.
Obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with the general calculation device, they can concentrate on the single calculation element, perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in the memory storage and carry out by calculation element, perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. an emulation mode is used for the exploitation of hardware device drivers and/or business software, it is characterized in that, comprising:
The hardware interface abstract module is set, and described hardware interface abstract module is used for hardware operation is packaged into the system call consistent with destination software systems, for hardware device drivers and/or business software provide real access interface;
Central processor CPU interface abstract module is set, and described cpu i/f abstract module is used for being connected with the chip emulation model, produces the sequential that meets described chip emulation model;
Described hardware interface abstract module and cpu i/f abstract module carry out message interaction.
2. method according to claim 1 is characterized in that, described hardware interface abstract module is connected by virtual bus with described cpu i/f abstract module, and carries out message interaction by described virtual bus.
3. method according to claim 2 is characterized in that, described hardware interface abstract module is connected by described virtual bus with described cpu i/f abstract module and comprises alternately:
Described hardware interface abstract module is connected by communications protocol with described cpu i/f abstract module, and mutual data are packaged into the packet of the desired form of described communications protocol between described hardware interface abstract module and the described cpu i/f abstract module.
4. method according to claim 2 is characterized in that, described hardware interface abstract module and described cpu i/f abstract module comprise alternately by described virtual bus:
Described hardware interface abstract module receives the read/write command from described hardware device drivers, and will be according to the following packet that produces one of at least described read/write command: the type of the length of the data of the address of described read/write command, described read/write command correspondence, the data of described read/write command correspondence;
Described hardware interface abstract module sends described packet by described virtual bus to described cpu i/f abstract module.
5. method according to claim 2 is characterized in that, described hardware interface abstract module and described cpu i/f abstract module comprise alternately by described virtual bus:
When described hardware interface abstract module receives write order from described hardware device drivers, described hardware interface abstract module becomes packet with the data encapsulation to be written of described write order correspondence, and sends to described cpu i/f abstract module by described virtual bus.
6. method according to claim 2 is characterized in that, described hardware interface abstract module and described cpu i/f abstract module comprise alternately by described virtual bus:
Described hardware interface abstract module obtains message from described cpu i/f abstract module by described virtual bus, wherein,
When described message when reading return command, then finish the read request of described hardware device drivers, and return the pairing data of described read request;
When described order is read command from external unit, then directly initiate direct storage register visit DMA read operation, after the data that read described read command correspondence, return the described data that read to described external unit;
When described order is write order from described external unit, then directly initiate the DMA write operation, with the data write memory of described write order correspondence.
7. method according to claim 3 is characterized in that described communications protocol comprises transmission control protocol.
8. an analogue system is used for the exploitation of hardware device drivers and/or business software, it is characterized in that, comprising:
The hardware interface abstract module is used for hardware operation is packaged into the system call consistent with destination software systems, for hardware device drivers and/or business software provide real access interface;
The cpu i/f abstract module is connected with the chip emulation model, is used to produce the sequential that meets described chip emulation model;
Described hardware interface abstract module and cpu i/f abstract module carry out message interaction.
9. system according to claim 8 is characterized in that, also comprises:
Virtual bus is used to connect described hardware interface abstract module and described cpu i/f abstract module, and carries out message interaction between described hardware interface abstract module and described cpu i/f abstract module.
10. system according to claim 9, it is characterized in that, described virtual bus specifically is used for connecting described hardware interface abstract module and described cpu i/f abstract module by communications protocol, and mutual data encapsulation between described hardware interface abstract module and the described cpu i/f abstract module is become the packet of the desired form of described communications protocol.
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| CN101630343B (en) * | 2009-08-18 | 2011-07-13 | 中兴通讯股份有限公司 | Simulation method and simulation system |
| CN101944152B (en) * | 2010-09-29 | 2012-07-04 | 中国电子科技集团公司第十四研究所 | Simulation method of switch control chip |
| CN101950167B (en) * | 2010-10-20 | 2012-05-30 | 广州数控设备有限公司 | Simulated embedded type numerical control system based on Windows operating system and implementation method thereof |
| CN103093777B (en) * | 2012-12-28 | 2015-12-23 | Tcl康钛汽车信息服务（深圳）有限公司 | A kind of method and system adopting android system control DVD equipment |
| CN108008945A (en) * | 2017-12-13 | 2018-05-08 | 天津津航计算技术研究所 | Device PCI drives development approach under a kind of LINUX system |
| CN109683877B (en) * | 2018-12-11 | 2022-03-15 | 中国航空工业集团公司西安航空计算技术研究所 | SystemC-based GPU software and hardware interaction TLM system |
| CN112861468B (en) * | 2021-02-08 | 2022-12-06 | 山东云海国创云计算装备产业创新中心有限公司 | Software and hardware collaborative simulation verification method, device and medium |
| CN114118356B (en) * | 2021-10-11 | 2023-02-28 | 北京百度网讯科技有限公司 | Neural network processor verification method and device, electronic equipment and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1996263A (en) * | 2005-12-28 | 2007-07-11 | 中国科学院微电子研究所 | Real-time simulation development system and method therefor |
| CN101261600A (en) * | 2007-03-06 | 2008-09-10 | 中兴通讯股份有限公司 | Software test apparatus and test software design method |
| CN101499937A (en) * | 2009-03-16 | 2009-08-05 | 盛科网络（苏州）有限公司 | Software and hardware collaborative simulation verification system and method based on FPGA |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030088710A1 (en) * | 2001-07-05 | 2003-05-08 | Sukhwinder Sandhu | Simulation environment software |
| CN1731337A (en) * | 2005-08-23 | 2006-02-08 | 深圳市盈宁科技有限公司 | Network simulated floppy disk driving method and simulated floppy disk driver |
| CN201222243Y (en) * | 2007-12-24 | 2009-04-15 | 深圳市富怡时代科技有限公司 | Artificial floppy disk drive |
| CN101630343B (en) * | 2009-08-18 | 2011-07-13 | 中兴通讯股份有限公司 | Simulation method and simulation system |
-
2009
- 2009-08-18 CN CN2009101661814A patent/CN101630343B/en active Active
-
2010
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1996263A (en) * | 2005-12-28 | 2007-07-11 | 中国科学院微电子研究所 | Real-time simulation development system and method therefor |
| CN101261600A (en) * | 2007-03-06 | 2008-09-10 | 中兴通讯股份有限公司 | Software test apparatus and test software design method |
| CN101499937A (en) * | 2009-03-16 | 2009-08-05 | 盛科网络（苏州）有限公司 | Software and hardware collaborative simulation verification system and method based on FPGA |
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