WO2011020353A1

WO2011020353A1 - Emulation method and system

Info

Publication number: WO2011020353A1
Application number: PCT/CN2010/073117
Authority: WO
Inventors: 缪众林; 李彧; 王志忠; 刘衡祁
Original assignee: 中兴通讯股份有限公司
Priority date: 2009-08-18
Filing date: 2010-05-24
Publication date: 2011-02-24
Also published as: CN101630343B; CN101630343A

Abstract

An emulation method and system, the method for developing a hardware device driver (91) and/or a service software comprises: setting a hardware interface abstract module for providing a real access interface for the hardware device driver (91) and/or the service software, wherein the access interface used for encapsulating hardware access operations of the hardware device driver (91) and/or the service software to a system call command data package; setting a central processing unit (CPU) interface abstract module (94) for receiving the system call command data package, generating a time sequence consistent with a chip emulation model (95) and performing the hardware access operations; performing the message interaction between the hardware interface abstract module and the CPU interface abstract module (94). The driver and the service software can be seamlessly migrated to the real software-hardware environment by the method and the system to be parallel developed, thereby accelerating the development progress of the project.

Description

TECHNICAL FIELD The present invention relates to the field of communications, and in particular to a simulation method and system. BACKGROUND OF THE INVENTION An integrated circuit or field programmable gate array (Field Programable Gate Array, referred to as

FPGAs need to be supported by the driver and business software to achieve their specific functions. In the chip development and simulation phase, how to implement the configuration and management functions of the driver and business software determines the sufficiency and completeness of the chip simulation. At present, the conventional practice is to write a program in the function development stage, using the Register Transfer Language (RTL) or SYSTEMC description language, simulate the driver and business software functions, complete the initialization, configuration and management of the chip, and complete Functional simulation of the chip and - insurance. In the hardware debugging phase, real drive and business software are implemented in the target software environment. The method can meet the needs of chip simulation with few functions and relatively simple configuration management. However, for large-scale and functionally complex chips, the use of RTL to implement business software that is consistent with the actual functions is a huge task, and in the process of converting into actual drive and business software, it will consume a lot of work again. Minor differences between the simulation program and the actual software will cause problems in hardware debugging that cannot be reproduced in the simulation environment. At the same time, the development of real driver software needs to be completed in the hardware phase, resulting in an extension of the development cycle. At present, in the chip simulation phase, the related technology lacks a complete cross-platform software and hardware collaborative development method. SUMMARY OF THE INVENTION The present invention has been made in view of the problems of large workload, complicated debugging, and long development cycle in the chip development simulation stage in the related art. Therefore, the main object of the present invention is to provide a simulation solution to solve the above problems. one. In order to achieve the above object, in accordance with an aspect of the present invention, a simulation method is provided. The simulation method according to the present invention for the development of hardware device drivers and/or business software includes: setting a hardware interface abstraction module to provide an access interface for hardware device drivers and/or business software, the access interface for using the hardware The hardware access operation of the device driver and/or the business software is encapsulated into a system call command data packet; the central processor CPU interface abstraction module receives the system call command data packet, generates a timing conforming to the chip simulation model, and performs the hardware access operation. The hardware interface abstraction module interacts with the CPU interface abstraction module to exchange messages. Preferably, the hardware interface abstraction module and the CPU interface abstraction module are connected through a virtual bus, and perform message exchange through the virtual bus. Preferably, the hardware interface abstraction module and the CPU interface abstraction module are connected and interacted through the virtual bus, including: encapsulating the exchanged message data into a communication between the hardware interface abstraction module and the CPU interface abstraction module. a data packet in a format required by the protocol; the data packet interaction is performed through the virtual bus. . Preferably, the hardware interface abstraction module interacts with the CPU interface abstraction module through the virtual bus comprises: the hardware interface abstraction module receives a read/write command from the hardware device driver, and generates a read/write command data packet according to at least one of the following: The address of the /write command, the length of the data corresponding to the read/write command, and the type of data corresponding to the read/write command; the hardware interface abstraction module sends the data packet to the CPU interface abstraction module through the virtual bus. Preferably, the hardware interface abstraction module and the CPU interface abstraction module interacting through the virtual bus include: when the hardware interface abstraction module receives the write command from the hardware device driver, the hardware interface abstraction module encapsulates the data to be written corresponding to the write command into data. The package is sent to the CPU interface abstraction module via the virtual bus. Preferably, the hardware interface abstraction module and the CPU interface abstraction module interacting through the virtual bus include: the hardware interface abstraction module acquires a message from the CPU interface abstraction module through the virtual bus, wherein when the message is a read return command, the hardware device driver is ended. The read request returns the data corresponding to the read request; when the command is a read command from the external device, the direct storage register access DMA read operation is directly initiated, and after reading the data corresponding to the read command, the external device is Return the read data; When the command is a write command from an external device, the DMA write operation is directly initiated, and the data corresponding to the write command is written into the memory. Preferably, the communication protocol comprises a transmission control protocol. In order to achieve the above object, in accordance with another aspect of the present invention, an emulation system is provided. The simulation system according to the present invention is for the development of hardware device drivers and/or business software, comprising: a hardware interface abstraction module for providing an access interface for hardware device drivers and/or service software, the access interface for The hardware access operation of the hardware device driver and/or the service software is encapsulated into a system call command data packet; the CPU interface abstraction module is connected to the chip simulation model, and is configured to receive the system call command data packet to generate a chip simulation model. Timing, the hardware access operation is performed; the hardware interface abstraction module and the CPU interface abstraction module perform message interaction. Preferably, the system further includes: a virtual bus, configured to connect the hardware interface abstraction module and the CPU interface abstraction module, and perform message interaction between the hardware interface abstraction module and the CPU interface abstraction module. Preferably, the virtual bus is specifically configured to connect the hardware interface abstraction module and the CPU interface abstraction module through a communication protocol, and encapsulate the data exchanged between the hardware interface abstraction module and the CPU interface abstraction module into a data packet in a format required by the communication protocol. Through the invention, the hardware interface abstraction module, the CPU interface abstraction module and the chip simulation model connected to the hardware interface abstraction module which provide the hardware operation to the upper layer are solved, and the workload in the chip development and simulation stage is solved in the related art. Debugging complex and long development cycles, enabling drivers and business software to be seamlessly ported to the actual hardware and software environment, enabling parallel development, thereby accelerating project development. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set to illustrate,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 is a flowchart of a simulation method in an embodiment of the present invention; FIG. 2 is a schematic diagram of a module in a simulation method according to an embodiment of the present invention; and FIG. 3 is a module in a simulation method according to an embodiment of the present invention; Figure 2 is a schematic diagram showing the structure of the data on the virtual bus in the embodiment of the present invention; Figure 5 is a functional flow chart of the hardware interface abstraction module processing the driving hardware operation according to an embodiment of the present invention; 6 is a flowchart of processing a message between a hardware interface abstraction module and a virtual bus according to an embodiment of the present invention; FIG. 7 is a flowchart of processing a virtual bus message message by a hardware interface abstraction module according to an embodiment of the present invention; A hardware interface abstraction module according to an embodiment of the present invention processes a flowchart of an on-chip bus or a chip external bus direct storage register access operation request and interrupt processing; and FIG. 9 is a structural block diagram of a simulation system according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION Related Art In the chip development and simulation stage, the workload is large, the debugging is complicated, and the development period is long. The embodiment of the present invention provides a simulation solution, and the communication between the simulation model and the software environment is established through the solution, and the software pair is The hardware access requirements are transferred to the simulation platform by the model, and the results of the model execution and the interrupt messages generated by the model and the model's Direct Memory Access (DMA) operations are passed to the software environment. The virtual bus shields the implementation details of the hardware and provides a real hardware environment for the software to achieve a unified virtual and real environment. The processing principles of the scheme are as follows: Set hardware interface abstraction module, hardware interface abstraction module is used to provide real access interface for hardware device driver and/or business software; set central processor CPU interface abstraction module, CPU interface abstraction module is used for The chip simulation model is connected to generate timings in accordance with the chip simulation model; the hardware interface abstraction module and the CPU interface abstraction module perform message interaction. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. The invention will be described in detail below with reference to the drawings in conjunction with the embodiments. In the following embodiments, the steps shown in the flowchart of the accompanying drawings may be performed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some In this case, the steps shown or described may be performed in a different order than the ones described herein. Method Embodiments According to an embodiment of the present invention, a simulation method is provided for hardware device driver and/or service software development. FIG. 1 is a flowchart of a simulation method according to an embodiment of the present invention, as shown in FIG. The process includes the following steps S102 to S106: Step SI 02, setting a hardware interface abstraction module, providing an access interface for the hardware device driver and/or the service software; the access interface is configured to encapsulate the hardware device driver and/or the hardware access operation of the service software into a system call command data packet. Step S104, setting a central processor CPU interface abstraction module, receiving a system call command data packet, generating a timing conforming to the chip simulation model, performing a hardware access operation; step S106, the hardware interface abstraction module and the CPU interface abstraction module performing message interaction . In step S106, the hardware interface abstraction module and the CPU interface abstraction module are connected through a virtual bus, and perform message exchange through the virtual bus. Related technologies In the chip simulation phase, there is a lack of a complete cross-platform software and hardware collaborative development method, and the corresponding software only performs chip simulation through a real hardware interface. In this embodiment, by providing a hardware interface abstraction module, the upper layer hardware operation is closed into a system call command, and the timing is generated by the CPU interface abstraction module, so that the driver and the business software can be seamlessly transplanted to the actual software and hardware environment to realize parallel development. The hardware interface abstraction module and the CPU interface abstraction module are connected by a communication protocol, and the data exchanged between the hardware interface abstraction module and the CPU interface abstraction module is encapsulated into a data packet of a format required by the communication protocol, and the following aspects are performed on J3⁄4 from the following aspects: Detailed description. Aspect 1, the hardware interface abstraction module receives a read/write command from the hardware device driver, and generates a data packet of the read/write command according to at least one of the following: an address of the read/write command, and a length of the data corresponding to the read/write command The type of data corresponding to the read/write command; the hardware interface abstraction module sends a data packet to the CPU interface abstraction module through the virtual bus. Aspect 2: When the hardware interface abstraction module receives the write command from the hardware device driver, the hardware interface abstraction module encapsulates the data to be written corresponding to the write command into a data packet, and sends the data to the CPU interface abstraction module through the virtual bus. Aspect 3: The hardware interface abstraction module obtains a message from the CPU interface abstraction module through the virtual bus, wherein when the message is a read return command, the hardware device driver read request is ended, and the data corresponding to the read request is returned; when the command is When a read command from an external device directly initiates a direct storage register access DMA read operation, after reading the data corresponding to the read command, it returns a read operation of the external device; when the above command is a write command from an external device, Directly initiate DMA Write operation, write the data corresponding to the write command to the memory. Preferably, the communication protocol comprises a transmission control protocol. The present embodiment will be described in detail in four aspects below. Aspect 1 implements a hardware interface abstraction module at the bottom of the target software (ie, business software) environment, the hardware interface abstraction module provides basic hardware operations for upper layer drivers (ie, hardware device drivers) and business software, wherein hardware operations may include However, it is not limited to: read and write access to hardware registers, block data copy during system memory and target, response hardware interrupt function, etc. This module provides an interface for hardware device drivers and/or business software to encapsulate hardware operations into and A consistent system call of the target software system for the upper hardware device driver and/or business software to make calls. In the actual hardware environment, the hardware interface abstraction module is replaced by the hardware operation provided by the actual hardware. The actual hardware interface is PCI or LOCAL BUS. Therefore, only the driver of the development interface needs to be driven, and the driver and service located above the basic hardware operation. The software can be used directly without modification. Aspect 2 also relates to a CPU interface abstraction module connected to the chip simulation model in this embodiment. The CPU interface abstraction module is connected to the chip internal on-chip bus or directly connected to the chip's external CPU interface bus to realize access and control of internal devices. Mask out the hardware details of the CPU side interface and connect directly to the software development environment. Aspect 3 In actual development, commonly used operating system platforms include vxworks, linux, windows mobile systems, etc. Commonly used model simulation softwares include Modelsim, Ncsim, SystemC, etc. Therefore, various simulation platforms need to run in different operating system environments, such as Windows, Linux, and so on. Cross-platform communication can be implemented using the TCP protocol, but it is not limited to this communication protocol. For example, if the emulation and software environment are running on the same computer, shared memory can be used to implement inter-process communication, or in communication requirements. In higher cases, dedicated hardware is used to achieve cross-platform communication. Aspect 4 may use a communication protocol to communicate between the hardware interface abstraction module and the CPU interface abstraction module, and the communication protocol encapsulates the basic hardware operation of the hardware interface abstraction module into a data packet transmission to The CPU interface abstraction module of the chip simulation platform is handed over to the simulation model for execution. The data that needs to be returned to the software platform is encapsulated into a packet by the CPU interface abstraction module and then transmitted to the hardware interface abstraction module, and transmitted to the software through the basic hardware abstraction interface module. The interrupt signal state of the model is also encapsulated into a data packet transmission to the hardware interface abstraction module, which is passed to the interrupt service routine for execution. The invention will now be described in detail in conjunction with the drawings and embodiments. 2 is a schematic diagram of a module in a simulation method according to an embodiment of the present invention. As shown in FIG. 2, the method includes: a service software 101, a hardware device driver 102 (ie, a hardware device driver), a hardware interface abstraction module 103, and a CPU interface. Abstract module 104, virtual bus 105, chip external bus 106 and chip emulation environment 107. 3 is a schematic diagram 2 of a module in a simulation method according to an embodiment of the present invention. As shown in FIG. 3, the method includes: a service software 101, a hardware device driver 102, a hardware interface abstraction module 103, a CPU interface abstraction module 104, and a virtual bus 105. The on-chip bus 106 and the chip emulation environment 107 differ from FIG. 2 in that the CPU interface abstraction module is directly connected to the internal bus in FIG. The present embodiment will be described below based on FIGS. 2 and 3. The service software 101 in FIG. 2 and FIG. 3 is an application software that implements a chip function, and its function implementation is built on the hardware device driver 102. The hardware device driver 102 encapsulates the implementation details of the hardware and encapsulates the different hardware implementations into a unified interface. The hardware device driver 102 invokes basic hardware operations to implement control and access to the hardware. For newly developed chips, all hardware device drivers 102 and some business software 101 need to be re-developed. The hardware interface abstraction modules in Figures 2 and 3 are used for communication between hardware drivers and simulation models. For the driver side, the interface simulates the actual hardware behavior, provides a hardware operation interface, and uses the virtual bus 105 to connect to the chip emulation environment 107. If it is an actual board, the actual bus is connected to the chip.

The CPU interface abstraction module 104 receives the messages from the virtual bus 105 and generates timings that conform to the chip interface requirements to enable access to the chip external or internal bus 106. The virtual bus 105 is a cross-platform communication means, and the command and data are transmitted in a packet manner. FIG. 4 is a schematic diagram showing the structure of a data packet on the virtual bus according to an embodiment of the present invention. The hardware operation is converted into a 4-head header and an optional data portion. The header includes a message type, such as a write command, a read command, a read return command, an interrupt status update command, and the like. For the write command and the read return command, the corresponding data part is required later, and the length is reported by The length field in the header is determined. A start address field is also defined. However, the actual implementation of the command according to hardware support will increase or decrease.

The CPU interface abstraction module 104 and the hardware interface abstraction module 103 need to generate corresponding commands and data according to the requirements of hardware and software, and process the returned data. The details will be described below with reference to FIGS. 5 to 8. 5 is a functional flow diagram of a hardware interface abstraction module processing driver hardware operation according to an embodiment of the present invention. As shown in FIG. 5, the hardware interface abstraction module 103 receives a read/write command from a hardware device driver (ie, a driver layer). The corresponding header is generated according to the address, data length and type of the read/write command and sent to the CPU interface abstraction module 104 through the virtual bus. If the command is a write command, the data to be written is also sent to the CPU through the virtual bus 105. Interface abstraction module 104. FIG. 6 is a flowchart of processing a message between a hardware interface abstraction module and a virtual bus according to an embodiment of the present invention. As shown in FIG. 6, the hardware interface abstraction module 103 also continuously monitors messages from the virtual bus. If it is a read return command, the drive layer read request is terminated, and the data is returned; if it is a read/write command from an external device (peripheral), the DMA operation is directly initiated, and the write operation directly writes the data to the specified memory, and reads The operation accesses the data from within and ends the peripheral read operation. If the interrupt is switched from the peripheral, the interrupt service routine of the driver is executed according to the state of the interrupt signal. 7 is a flowchart of a hardware interface abstraction module processing a virtual bus message message according to an embodiment of the present invention, and FIG. 8 is a hardware interface abstraction module for processing an on-chip bus or chip external bus DMA operation request and interrupt processing according to an embodiment of the present invention. Flowchart, as shown in Figure 7 and Figure 8, the CPU interface abstract module function and the hardware interface function are basically similar, and the same is not mentioned here, the difference is that the CPU interface module only generates the interrupt status update command, and The hardware interface abstraction module will only respond to interrupt requests. The hardware interface abstraction module provides an interface to the driver software, and there is no timing, and the CPU interface abstraction module needs to communicate with the chip interface model, and its interface timing must meet the design requirements. In summary, as can be seen from Figure 2 and Figure 3, if you use real hardware board debugging software, you only need to replace the hardware interface abstract module with the hardware interface driver, and the other software modules are identical. Therefore, the driving and service software development based on the simulation model can be realized by the embodiment, and only the driver of the actual hardware interface needs to be added when transplanting into the actual hardware system, and the hardware driver and the business software can be seamlessly transplanted. System embodiment According to an embodiment of the present invention, a simulation system is provided for hardware device driver and/or business software development, and FIG. 9 is a structural block diagram of a simulation system according to an embodiment of the present invention, as shown in FIG. The system includes: a hardware interface abstraction module 92, a CPU interface abstraction module 94, which is described in detail below. The hardware interface abstraction module 92 is configured to provide a real access interface for the hardware device driver and/or the service software, where the access interface is used to encapsulate the hardware device driver and/or the hardware access operation of the service software into a system call command data packet; The CPU interface abstraction module 94 is connected to the chip simulation model, configured to receive the system call command data packet, generate a timing conforming to the chip simulation model, and perform the hardware access operation; the hardware interface abstraction module and the CPU interface abstraction module perform the message Interaction. As shown in FIG. 9, the system further includes a virtual bus for connecting the hardware interface abstraction module and the CPU interface abstraction module, and performing interaction between the hardware interface abstraction module and the CPU interface abstraction module. The virtual bus is specifically configured to connect the hardware interface abstraction module and the CPU interface abstraction module through a communication protocol, and encapsulate the data exchanged between the hardware interface abstraction module and the CPU interface abstraction module into a data packet in a format required by the communication protocol. In summary, through the above embodiments of the present invention, model-based driving and business software development can be realized, and the simulation and debugging of the chip function can be facilitated. Meanwhile, the developed hardware driver and business software can be seamlessly transplanted to the actual soft. In the hardware environment, parallel development is realized, and the project development progress is accelerated. Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device, or they may be separately fabricated into individual integrated circuit modules, or they may be Multiple modules or steps are made into a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the scope of the present invention are intended to be included within the scope of the present invention.

Claims

Claim

A simulation method for hardware device driver and/or business software development, comprising:

Setting a hardware interface abstraction module, providing an access interface for the hardware device driver and/or service software, the access interface for packaging the hardware device driver and/or the hardware access operation of the service software into a system call command data packet;

Setting a central processor CPU interface abstraction module, receiving the system call command data packet, generating a timing conforming to a chip simulation model, and performing the hardware access operation;

The hardware interface abstraction module interacts with the CPU interface abstraction module to perform packet exchange.

The method according to claim 1, wherein the step of the hardware interface abstraction module interacting with the CPU interface abstraction module comprises:

The hardware interface abstraction module interacts with the CPU interface abstraction module through a virtual bus.

The method according to claim 2, wherein the step of the hardware interface abstraction module interacting with the CPU interface abstraction module through the virtual bus comprises:

Encapsulating the exchanged message data into a data packet in a format required by a communication protocol used by the hardware interface abstraction module and the CPU interface abstraction module;

The data packet interaction is performed through the virtual bus.

The hardware interface abstraction module receives a read/write command from the hardware device driver, and generates a data packet of the read/write command according to at least one of: an address of the read/write command, the read/write The length of the data corresponding to the command, the type of the data corresponding to the read/write command; the hardware interface abstraction module sends the data packet to the CPU interface abstraction module through the virtual bus.

The method according to claim 2, wherein the step of the hardware interface abstraction module and the CPU interface abstraction module performing packet exchange through the virtual bus comprises: When the hardware interface abstraction module receives a write command from the hardware device driver, the hardware interface abstraction module encapsulates the data to be written corresponding to the write command into a data packet, and sends the data to the server through the virtual bus. The CPU interface abstraction module.

The hardware interface abstraction module acquires a message from the CPU interface abstraction module through the virtual bus, where

When the message is a read return command, the hardware device driver read request is ended, and the data corresponding to the read request is returned;

When the command is a read command from an external device, directly initiating a direct storage register access DMA read operation, and after reading the data corresponding to the read command, returning the read to the external device Data

When the command is a write command from the external device, a DMA write operation is directly initiated, and data corresponding to the write command is written into the memory.

7. The method of claim 3, wherein the communication protocol comprises a transmission control protocol.

8. A simulation system for the development of hardware device drivers and/or business software, characterized in that it comprises:

a hardware interface abstraction module, configured to provide an access interface for the hardware device driver and/or service software, where the access interface is used to encapsulate the hardware device driver and/or the hardware access operation of the service software into a system call command data packet. ;

a CPU interface abstraction module, connected to the chip simulation model, configured to receive the system call command data packet, generate a timing conforming to a chip simulation model, and perform the hardware access operation; and the hardware interface abstraction module and the CPU interface abstraction module report Text interaction.

9. The system according to claim 8, further comprising:

And a virtual bus, configured to connect the hardware interface abstraction module and the CPU interface abstraction module, and perform message interaction between the hardware interface abstraction module and the CPU interface abstraction module. The system according to claim 9, wherein the virtual bus is specifically configured to connect the hardware interface abstraction module and the CPU interface abstraction module by a communication protocol, and the hardware interface abstraction module and the CPU The data exchanged between the interface abstraction modules is encapsulated into data packets in the format required by the communication protocol.