CN1293387C - Multiple virtual logic tester supported semiconductor test system - Google Patents
Multiple virtual logic tester supported semiconductor test system Download PDFInfo
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- CN1293387C CN1293387C CNB011158840A CN01115884A CN1293387C CN 1293387 C CN1293387 C CN 1293387C CN B011158840 A CNB011158840 A CN B011158840A CN 01115884 A CN01115884 A CN 01115884A CN 1293387 C CN1293387 C CN 1293387C
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Abstract
The present invention provides a single semiconductor testing system which is used as a multiple logical tester. The single semiconductor testing systems are mutually independent, and run in an asynchronous mode. The system comprises a host machine computer, a plurality of pin units, a bus line of the pin units and a device, wherein the host machine computer controls the whole run of the single semiconductor testing system by executing testing program; each pin unit is provided with a device for producing a testing mode for distributing pins of a semiconductor device to be tested and evaluating the obtained response of the semiconductor device to be tested; the bus line of the pin units is arranged among the host machine computer and the pin units, and is used for conveying addresses, data, control signals and timing clock signals; the device is used for configuring the pin units which are corresponding to input pins or output pins of the semiconductor device to be tested when the host machine computer puts a group of selected addresses in the bus line of the pin units.
Description
Technical field
The present invention relates to a kind of semiconductor test system that is used for measuring semiconductor device such as IC and LSI, as automatic test equipment (ATE), especially relate to a kind of simple ATE system, as many logic testers, each all moves independently of one another and asynchronously, and the simple logic tester of a routine.
Background technology
When utilizing semiconductor test system such as automatic test equipment (ATE) or IC tester measuring semiconductor device such as IC or LSI, will sentence a predetermined test sequence at the corresponding pin of device to be measured test signal (pattern) is provided, semiconductor test system receives the output signal that this test signal of response produces from this device to be measured, and whether correctly this output signal is sampled with the sequential of regulation so that compare to determine this semiconductor device to be measured function of carry out desired with the value signal of expecting by signal strobe.
Fig. 1 is a schematic block scheme, and an example of the semiconductor test system of a routine is described.In the semiconductor test system of Fig. 1, a mode generator 12 is from a test handler 11 acceptance test data.This mode generator 12 produces the test pattern data and the binarization mode that will offer the expectation of a pattern comparator 17 that will offer a waveform format device 14.A timing sequencer 13 produces the operation of clock signal with synchronous whole test system.In Fig. 1, clock signal offers for example this mode generator 12, pattern comparator 17, waveform format device 14 and analog comparator 16.
Timing sequencer 13 also provides (tester speed) pulse of a test loop and time series data to give this waveform format device 14.This pattern (test vector) data definition ' 0 ' and ' 1 ', just, the rising edge of test signal waveform and negative edge.Time series data (sequential is provided with data) has defined the rising edge of waveform and the negative edge sequential (decay time) with respect to the test loop pulse.Usually, this time series data also comprises shape information such as RZ (returning zero), NRZ (not returning zero) or EOR (XOR) waveform.
According to from the mode data of mode generator 12 and test loop pulse and from the time series data of timing sequencer 13, waveform format device 14 forms has the waveform of regulation and the test signal of sequential, and this waveform format device 14 sends to DUT19 by a driver 15 with this test signal.This waveform format device 14 comprises setting/reset flip-flop (not shown) to form the test signal that will offer this driver 15, and this driver 15 is adjusted amplitude, impedance and/or the switching rate of this test signal and this test signal is imposed on DUT19.
Analog comparator 16 is with gate (strobe) sequential comparison of being scheduled to response signal and reference voltage from DUT 19, resulting logical signal is provided for this pattern comparator 17, is wherein carrying out logic from the logical schema of analog comparator 16 and between from the expected value pattern of mode generator 12 relatively.This pattern comparator 17 checks that whether two patterns match each other, and come to determine passing through and inefficacy of this DUT19 thus.When determine losing efficacy, this fail message is offered a dead-file 18, and store so that carry out failure analysis with fail address information from the DUT19 of mode generator 12.
In routine techniques, this semiconductor test system is configured to or every pin system (every pin tester) or shared resource system (pin group system).At this, every pin tester is meant a semiconductor test system, and all hardware resource that wherein is used to produce test parameter such as signal all is each test channel (test pin) that test macro is provided independently.Subsequently, in every pin tester, be used for the various test parameters of semiconductor device to be measured and can be independently be provided with at each pin of DUT.
Pin group tester is meant a semiconductor test system, and wherein tester resource and the reference voltage such as timing sequencer all is common to test channel all or predetermined quantity (test pin).One has shared resource (group pin) as shown in Figure 1 though the test of the IC tester very economical of structure but underaction ground is nearest, high complicated and IC device at a high speed.Enjoy together in the shared resource tester of the test parameter of each terminal pin of DUT and comparing, every pin tester is applicable to test high speed LSI preferably, because it can be each terminal pin generation test parameter of DUT independently, therefore can freely produce complicated test pattern and sequential.In typical every pin IC tester, this timing sequencer 13 and waveform format device 14 shown in Figure 1 offer each test pin independently, promptly give each terminal pin of DUT.
In semiconductor test industry, need test multiple arrangement concurrently so that improve testing efficiency, existence can be measured the semiconductor test system of multiple arrangement concurrently, and Fig. 2 A and 2B have provided the example of the basic configuration that is used for testing simultaneously a plurality of semiconductor devices.In Fig. 2 A, two measuring head TH1 and TH2 are connected to an automatic test equipment (ATE) 10 to test two device DUT1 and DUT2 concurrently.In Fig. 2 B, two devices DUT1 and DUT2 test being connected on the single signal testing head TH of ATE10.
But, in traditional test macro, or every pin system or pin group system, this test pin all is to treat as a single pin group, they start together and move up to finishing whole test procedure.In other words, these traditional test macros are to carry out parallel test by duplicate same test pattern on a single mode memory, therefore the operation above just has such restriction: the same test pattern of each device operation, and the pattern on each device must be moved and finish, and mistake occurs even detect the device of DUT.
Summary of the invention
Therefore, a target of the present invention provides a kind of semiconductor test system that plays many logic testers function, and wherein each logic tester can both move independently of one another and asynchronously.
Another target of the present invention provides a kind of semiconductor test system as many logic testers, and wherein the requirement that each logic tester can corresponding semiconductor device to be measured freely is configured according to test pin.
Another target of the present invention provides a kind of semiconductor test system, and it can carry out synchronous or asynchronous concurrent testing to multiple arrangement.
Another target of the present invention provides a kind of semiconductor test system, and it can move a plurality of test procedures concurrently and can simplify the software programming that is used for the multiple arrangement concurrent testing.
Another target of the present invention provides a kind of semiconductor test system, and it can be with low-cost and high test dirigibility and the many logic testers of testing efficiency virtual support.
According to the present invention, this semiconductor test system comprises: host computer, by carrying out the whole service of a semiconductor test system of test procedure control; A plurality of pin unit, each unit have the device of the semiconductor device to be measured response of the test pattern of test pin of the described semiconductor test system that is used to produce the pin of distributing to semiconductor device to be measured and assessment gained; The pin unit bus is arranged between described host computer and this a plurality of pin unit, is used for transfer address, data, control signal and clock; Installing plate is used to install a plurality of semiconductor devices to be measured with from the described test pattern of described a plurality of pin unit parallel receives; And be used at the free device that also dynamically reconfigures described a plurality of pin unit of described a plurality of semiconductor devices to be measured, wherein the operation timing of each described pin unit is synchronized with each other or separate asynchronously.
In the test macro of many virtual tests of support instrument of the present invention, test pin in groups is dynamically to distribute to the independent subsystem of device independently to be measured (DUT) or Single Chip Microcomputer (SCM) system (SoC).These groups are carried out addressing independently by the tester bus and are treated as each test macro that disperses, this set of dispense and selection are to finish by a hardware mechanisms, and this mechanism allows this host computer to write this group selection address (GSA) on the pin unit bus.Operating in test on these virtual test instrument can be together or start independently or stop independently.Therefore, the present invention allows to test a plurality of different IC devices simultaneously on a single test macro, and thought of the present invention also is applicable to the tester of every pin system or pin group system.
Description of drawings
Fig. 1 is the synoptic diagram of an example that produces the structure of test strobe and test signal in the traditional semiconductor test system of expression on round-robin basis based on the test data of describing.
Fig. 2 A and 2B are that expression utilizes a semiconductor test system to be used for testing concurrently the synoptic diagram of the basic configuration of a plurality of IC devices to be measured.
Fig. 3 is the synoptic diagram of the basic structure of expression semiconductor test system of the present invention, and this test macro can support to test concurrently the multiple virtual logic tester of a plurality of different devices.
Fig. 4 is that expression is arranged in each pin unit of semiconductor test system of Fig. 3 so that the circuit diagram of an example of the structure in the pin unit write decoder that receives group address distributing pipe pin unit when selecting data.
Fig. 5 A-5I is a sequential chart, the operation related, that be used for the base pin selection unit and produce test enable signals of the pin unit group code translator of presentation graphs 4.
Fig. 6 is a circuit diagram, and expression realizes providing an example that stops test signal (end of test signal) with respect to each pin unit in a plurality of virtual test instrument of the present invention.
Fig. 7 A and 7B are the synoptic diagram that schema file is arranged and the pattern loading flows that expression is used for traditional semiconductor test system and a plurality of virtual test instrument of the present invention.
Fig. 8 is the process flow diagram of the interior concurrent testing operation of the semiconductor test system of the single measuring head of expression use of the present invention.
Fig. 9 is the process flow diagram of the interior concurrent testing operation of the semiconductor test system of the two or more measuring heads of expression use of the present invention.
Figure 10 is the process flow diagram that expression is used to test the concurrent testing operation in the semiconductor test system of the present invention of the function nuclear core in Single Chip Microcomputer (SCM) system (SoC) IC.
Figure 11 is the synoptic diagram of example that is illustrated in the software and hardware structure of a plurality of virtual logic testers that are used for three DUT of concurrent testing in the semiconductor test system of the present invention.
Figure 12 is illustrated in the process flow diagram that is distributed the process of one group of virtual logic tester between the concurrent testing of Figure 10 by semiconductor test system of the present invention.
Figure 13 is the process flow diagram of process that is carried out the concurrent testing of Figure 10 by the virtual logic tester in the semiconductor test system of the present invention.
Embodiment
Figure 3 illustrates the basic configuration of the semiconductor test system of a plurality of virtual logic testers of support of the present invention.A plurality of virtual logic testers in the present invention can be defined as by using specific test group control hardware to move a single ATE (ATE (automatic test equipment)) system of a plurality of test procedures simultaneously.The example of Fig. 3 comprises an engine control system (system's principal computer or host computer) 31, pin unit/host controller interface 32, pin unit bus 33, a plurality of pin unit 35
1-35
NWith DUT installing plate 37.
The main task of engine control system 31 is run user test procedures and this test procedure is translated into the tester bus data that this this bus data configuration is also operated pin unit and retrieved test result.This engine control system can be a single computing machine or computer interconnection network, and each all supports to control the software of this test macro.Computing machine for example, workstation or personal computer can be controlled this user interface and can be connected to the computing machine of the needed real-time function of another control this test system hardware of operation.
This pin unit/system controller interface 32 arrives this pin unit bus 33 with engine control system 31 interfaces.Pin unit/system controller interface 32 adopts a kind of in two kinds of forms: it can be host card or the target bus card that connects by a flexible cable of supporting serial or parallel communication protocol for (1); (2) can be the interface card that connects two diverse buses on the triangular web base plate.
Pin unit/system controller interface 32 allows engine control system 31 individually to pin unit 35
1-35
NOr write in the group able to programme and dispose and control data.A group able to programme is defined as hardware mechanisms, and it allows the package of engine control system 31 on target pin unit 35 to select the address register write data groups to select address (GSA).When the particular group that has normal group of qualification and destination register address to selects the address to be placed on the address bus, these bus datas will be written to all pin unit 35 of these GSA group data of coupling
1-35
NDestination register.Carry out this function by the pin unit data write decoder as shown in Figure 4 in each pin unit 35 53, will describe these below in detail.
Pin unit 35 will produce a test pattern and assess the response of the DUT pin of gained for the test pin of being distributed.The virtual test cell that pin unit 35 is videoed and distributed from one group of tester pin unit plate (as 64-256), wherein each cell board can be met with a response by it for a corresponding D UT pin produces a test pattern and assesses.In the present invention, this pin unit is distributed and can freely and dynamically be reconfigured under the control of engine control system 31.
Usually the Premium Features of carrying out on pin unit 35 are: (1) read test state end, and (2) load test pattern, and (3) start test pattern, (4) read mode fail address, and (5) configuration pin unit.On the principle, these are identical functions with what use in current ATE system, and these functions can impose on pin group or the son part of represent the virtual test instrument.These pin unit 35 can have microcontroller, and some can locally be handled by these microcontrollers or a part of function is handled so that simplify and quicken.
-virtual test instrument technology can impose on based on the round-robin tester or based on the tester of incident.Traditional based on the round-robin tester in, produce a test pattern according to the test data that comprises test rate, delay timing, waveform and vector description.In tester (the new thought of tester structure), change and test pattern of timing information generation according to value based on incident.Provide about being described in detail in the Application No. 09/406,300 (having) of test macro by same assignee of the present invention based on incident.
As described above, the function of engine control system 31 is conduct and pin unit 35
1-35
NUser interface, this engine control system 31 makes the user can indicate the beginning of test operation and termination, load test procedure or other test condition or carry out the analysis of test result.This engine control system 31 is by pin unit bus 33 and pin unit 35
1-35
NInterface.Describe as front institute is concise and to the point, this engine control system 31 is by sending the group selection address to pin unit write decoders 53 in each pin unit 35 and dispose and distributing pin unit 35.
Fig. 4 has provided an examples of circuits of pin unit write decoder 53.This pin unit write decoder is designed to allow this engine control system 31 side by side to register as a group and writes a single pin unit or a plurality of pin unit.In the present invention by using group registration to write the control operation that function can strengthen the virtual test instrument effectively.Best pin unit is write control code translator 53 and is set in each pin unit 35.The effect of pin unit write decoder 53 is to detect from the registered address data of this engine control system 31 and data are selected by group and allow instruction and data to arrive the internal register of the pin unit 35 of appointment.Fig. 4 also allows the signal wire of pin unit bus 33 to transmit control signal, address date, clock etc.
-in the example of Fig. 4, pin unit write decoder 53 comprises group's selection address register 41, unit card address device (set) 42, and comparer 43 and 44, AND (with) door 45 and 46, OR (or) door 47, code translator 48 and trigger 49.An example of signal on pin unit bus 33 and data comprises a master (system) clock, data, and register address, card/group address, address enable signal, card/group selection signal, signal and a pin bus clock are selected in Writing/Reading.Should understand, exist a lot of modes can realize the present invention, the example of Fig. 4 only be for illustrative purposes for an example.
When obtaining direct pin unit selection (group write operation), comprise pin unit address (card/group address) and pin unit target internal register address on this address wire from engine control system 31.Data line comprises will write the data that maybe will read from destination register.At this, destination register is a register (not shown) that internally is arranged in each pin unit, is used for data transmission purpose.Read/write signal, card/group selection signal and address enable signal are driven to tell pin unit 35 fill order affairs by this engine control system 31.
More specifically, in the sequential chart of the block scheme of Fig. 4 and Fig. 5, engine control system 31 is placed on data Di (Fig. 5 E) on the data line, and card/group address GAi (Fig. 5 G) and pin unit target internal register address RAi (Fig. 5 F) are placed on the address wire.Data Di will send the destination register in the selected pin unit 35 to, and card/group address GAi indicates a target group identification number.
When the group id in the register 41 and card/group address coupling, comparer 43 just sends a matched signal.Replacedly, when the address in the unit card address device 42 and card/group address coupling, comparer 44 sends a matched signal.Address in unit card address 42 by switch or Special Automatic layoutprocedure setting to identify this pin unit uniquely.From the matched signal of comparer 43 and 44 by AND door 45 and 46 and repel mutually.OR door 47 provides an enable signal to code translator 48, sends the register address of being decoded to destination register thus.
Two AND doors 45 and 46 are provided these control signals, i.e. address enable signal (Fig. 5 C), and signal is selected in card/group selection signal (Fig. 5 H) and Writing/Reading.In the group write operation, Writing/Reading selects signal to be configured to high level indicating a write operation, and block/the group selection signal is configured to low level to indicate this group write operation.This engine control system 31, sorts according to this address enable signal that sorts from low to high subsequently more from high to low with pin bus clock (Fig. 5 B).Therefore, when finishing this sequence, register address RAi addressing whenever go up the pin unit internal register, if the register that this pin unit has mates with the value of indicating in card/group address GAi, just data Di is stored.
The major function that the group data are write is to send an ability that ' starts and test ' signal synchronously to a virtual test instrument group, and the pin unit 35 in virtual test instrument group all starts test at same system major clock edge., the ATE system a general character be to have a main system clock, derive all system sequences by this clock.When having stipulated destination register by code translator 48, an enable signal 18 is provided for this trigger 49, is created in the startup test signal shown in the circuit diagram of the sequential chart of Fig. 5 I and Fig. 4 at the sequential place of next pin bus clock thus.
A feature of the present invention is to produce one from pin unit 35 independently to stop test signal, and this termination signal can be sent to the pin bus stopping the distributing to test of this pin unit 35, but it is unaffected to distribute to the test of other pin unit 35.Engine control system 31 detects this termination test signal and enters a new test relevant with this termination test signal at this pin unit 35.Fig. 6 provides and realizes that this detection stops a circuit diagram example of the ability of test signal.
Minimally, this termination test may occur in expiring of test pattern to be finished or detects an output of not expecting from device to be measured.Routinely, should stop test signal by the main control system computer monitor, when detecting effective ' stopping a test ' signal, this host computer detects and handles test result from tester hardware.
In the present invention, when a plurality of virtual test instrument parallel running, need to detect a plurality of ' stopping test ' signal that can monitor by engine control system 31.In the example of Fig. 6, pin unit bus 33 comprises a plurality of ' stopping test ' signal that can be dynamically allocated to a virtual test instrument group.In a virtual test instrument group, each pin unit must have the ability of ' stopping test ' signal of asserting on the partition line of this pin unit bus 33.
These can be arranged by the standard lines ' OR ' to ' stopping test ' signal that uses pin unit 35 and finish.So in the example of Fig. 6, each pin unit 35
1-35
NComprise 52, one mask registers 54 of a traffic pilot and the open set utmost point (collector) driver Dr.For example, owing to detect mistake, a termination test signal is provided for traffic pilot 52, and this converter is by selecting from the data of selecting register 54.Therefore, this termination test signal is transmitted to pin unit bus 33 and therefore offers engine control system 31 by selected open set driver Dr.
The virtual test instrument technology that is used for a plurality of DUT logic testings allows each virtual test instrument with respect to other virtual test instrument or synchronously operation or operation asynchronously.Each virtual test instrument all has the test pattern copy that moves independently with other tester.Benefit be to be used for multiple arrangement the virtual test pattern disk storage approximately less than it standard A TE pattern copy N doubly.The reason that sort memory reduces will simply be explained with reference to Fig. 7 A and 7B below.
The minimizing of disk storage space is based on such fact: at the standard A TE system that is used for testing concurrently multiple arrangement (shown in Fig. 7 A), a subpattern 63A is repeated multiplication in single schema file 61A.This subpattern 63A is the desired test pattern of test single assembly.Therefore, the size of whole file may be calculated the product that subpattern (SP) and this pattern repeat the number of times of (PR), equals SP * PR.But in the virtual test instrument shown in Fig. 7 B, the subschema file 63B or the pattern of test single assembly are used again and are loaded in each virtual test instrument.Therefore, the size of whole schema file 61B is exactly the size of subschema file 63B.
In traditional ATE system, be used for a plurality of (walking abreast) DUT logic testing test pattern form by the horizontal repeated test pattern of destination apparatus, its be limited in this test pattern must be on all devices the once parallel and synchronous operation of property.Being limited in of synchronous operation: it can not allow to have found that device devious moves this test pattern that other partly keeps all other DUT still testing simultaneously.But in the present invention, for the corresponding pin unit that comprises a virtual test instrument, stop test signal by detecting, this DUT can be replaced by a new DUT, simultaneously with the new test of initialization independently of other virtual test instrument example.
Mainly, this asynchronous parallel test reduces the whole test duration.In asynchronous test, each DUT test assignment be allowed to speed with maximum move and do not require and other device of testing synchronously (as in synchronism detection) move its test pattern.Synchronism detection requires planning synchronous again, and this just causes having prolonged the whole test duration.
Fig. 8 and 9 is illustrated in the process flow diagram of a plurality of DUT tests in a plurality of virtual logic tester of the present invention.In traditional ATE logic testing system, the simple planning algorithm of neither one is realized concurrent testing, each test procedure all will customize with relevant test pattern at the device that will test, in the semiconductor system of a plurality of tests of support of the present invention, the concurrent testing that loads the device on the processor in the batch processing shown in Fig. 2 B can use simple algorithm to finish at an easy rate, and an example of this algorithm is shown in the process flow diagram of Fig. 8.
At first step S11, in test macro, load a test plan, concurrent testing ' N DUT ' wanted in this test plan indication.At step S12, this system configuration pin assignments device also is instantiated as pin assignments in the virtual test instrument of ' N ' individual example, in hardware.This process enters step S13 with the individual test procedure of instantiation " N " and with each each virtual test instrument of videoing subsequently.At step S14, this process indication test handler loads N DUT.At step S15, all test procedure tasks synchronization or startup asynchronously, in this step, selected pin unit provides test pattern and assessment to export from the response of DUT to DUT concurrently.
At step S16, this process waits for that all test procedure tasks stop, when all the test procedure tasks at the DUT on the test handler all stopped, at step S17, this system exported to all test results the test handler that is used for receiving (binning).Like this, tested DUT is classified according to test result.At step S18, this test handler of this procedure command withdraws from DUT from measuring head.Determine at step S19 whether the semiconductor device of being tested is last DUT, if then this process stops at step S20 place, if not, then this process is got back to the step of step S14 repeating step S14-S19 up to testing all semiconductor devices.
In the semiconductor test system of a plurality of tests of support of the present invention, the concurrent testing of the device on a plurality of single DUT processors (shown in Fig. 2 A) can use single algorithm to finish at an easy rate, there is shown an example of this algorithm in the flow process of Fig. 9.
At first step S21, in test macro, load a test plan, concurrent testing ' N DUT ' wanted in this test plan indication.At step S22, this process configuration pin distributor also is instantiated as pin assignments in the virtual test instrument of ' N ' individual example, in hardware.This process enters step S23 with the individual test procedure of instantiation " N " and with each video each virtual test instrument and test handler subsequently.At step S24, this process indication test handler loads N DUT.At step S25, all test procedure tasks synchronization or startup asynchronously, in this step, selected pin unit provides test pattern and assessment to export from the response of DUT to DUT concurrently.
At step S26, this process waits for that all test procedure tasks stop, when all the test procedure tasks at the DUT on the test handler all stop, this process moves to step S27, wherein this system exports to test handler to all test results, like this, tested DUT is classified according to test result.At step S28, this test handler of this procedure command withdraws from DUT from measuring head.Determine at step S29 whether the semiconductor device of being tested is last DUT, if then this process stops at step S30 place, if not, then this process is got back to the step of step S24 repeating step S24-S29 up to testing all semiconductor devices.
A kind of method for concurrent testing SoC (Single Chip Microcomputer (SCM) system) subsystem is similar with the concurrent testing of the concrete logical unit that separates, exactly test signal collection (set) is imposed on nuclear core in the SoC device concurrently, utilize the virtual test instrument performance of synchronous or asynchronous parallel, the test of treatment S oC device at an easy rate, traditional test macro can apply the synchronism detection signal concurrently, but they can not walk abreast asynchronously and apply the test signal collection.Two major advantages of asynchronous test are: (1) some interactive subsystem operational issue only just shows in asynchronous test, (2) test duration of whole device will reduce, because each test assignment is allowed to move and usually do not require with maximum rate carry out synchronous with other subsystem of testing again.
On virtual test instrument of the present invention, during asynchronous concurrently test SoC subsystem, can use simple algorithm as shown in figure 10.In the beginning of the process of Figure 10, at step S31, in test macro, load a test plan, this test plan indication will be by N SoC subsystem of N test procedure concurrent testing.At step S32, this process configuration pin allocation set (sets) also is instantiated as pin assignments in ' N ' individual virtual test instrument and mates each virtual test instrument test port pin of each SoC subsystem.This process enters step S33 with the individual test procedure of instantiation " N " and with each test procedure each virtual test instrument of videoing subsequently.At step S34, this process indication test handler loads the SoC device.At step S35, all test procedure task starts, in this step, the virtual test instrument that is distributed provides test pattern concurrently and assesses its response output to the SoC device.
At step S36, this process waits for that all test procedure tasks stop, when all the test procedure tasks at the SoC subsystem on the test handler all stop, this process moves to step S37, wherein this test macro is exported to test handler to all test results, thus, according to test result classification SoC.At step S38, this test handler of this procedure command withdraws from SoC from measuring head.Determine at step S39 whether the SoC that is tested is last DUT, if then this process stops at step S40 place, if not, then this process is got back to the step of step S34 repeating step S34-S39 up to testing all semiconductor devices.
An advantage using the SoC method of virtual test is that the test procedure of each subsystem of testing all identifies at an easy rate with pattern and separates, rather than be blended in the pattern and test configurations of link, this makes the Test Engineer research and develop at an easy rate and debugs subsystem testing program and the test pattern of SoC.This in addition separating property also allows to carry out like a cork the subsystem characterization.
Figure 11 represents to be configured to test concurrently the example of software and hardware block scheme of the virtual test instrument system of three DUT.In this example, software program task 82 (virtual test task VT1), 83 (virtual test task VT2), 84 (virtual test task VT3) are by the example as the same test procedure of main test procedure 81 ' Test Plan (test plan) ' instantiation.Suppose in this example and in test procedure, have only a test pattern DTP from professional nuclear 86 transmission of tester, suppose that also device DUT1-3 only has the pin that two names are called DPI and DPO, this test pattern DTP comprises the test subpattern that is used for each test pin DPI and DPO, and it is offered pin unit 35 by tester unit bus driver 87 and tester unit bus hardware interface 88
1-35
N(or the pin unit 1-6 among Figure 11).
Equally with reference to Figure 12, an example of the test process of arranging in Figure 11 is as follows, at step S51, in test macro, load test plan, process moves on to step S52 then, by obtaining from the professional nuclear 86 of tester at the pin unit handle RPDI of pin unit 1 and 2 and RPDO and configuration task VT1, these handles RPDI and RPDO will be used by virtual test task VT1, as the pin DPI of DUT1 and the reference of DPO.At step S53, this test subpattern DTP is loaded into the pin unit RPDI (pin unit 1) at the pin DPI of DUT1.
Subsequent process enters step S54, and wherein pin unit RPDI (pin unit 1) and RPDO (pin unit 2) are videoed the virtual test group with reference to RVTGROUP by group.In order to create a virtual group, this system can use control pin unit group, and these groups will be formed for each and build unique group selection address.Under the simplest situation, have with ' 1 ' integer that begins to distribute number, and increase by 1 at each new group, this unique group number write into these unit, be used for GSA (group selection address) register that this group is responded.
In step 56, this systems communicate virtual test task VT1 and at its test pin with reference to RPDI and RPDO and as the RVTGROUP of virtual test group.Subsequently, determine whether that at step S57 all virtual test tasks all distribute, if then finish this process at step S59; If not, this process enters step S58, uses DUT2-DUT3 and corresponding pin unit 3-6 at task VT2-VT3 repeating step S52-S57.
After in the process of Figure 12, being provided with test plan, to carry out the concurrent testing process in the mode shown in the process flow diagram of Figure 13.In the example of Figure 13, begin this process so that the test parameter of the test grades, load (load) and the drive threshold that comprise pin RPDI and RPDO is set at step S62 at step S61.The test of virtual test group RVTGROUP starts at step S63.In order to start all pin unit of virtual test instrument group together, this unique GSA (group selection address) is assigned to this group, and this can be by utilizing the group selection signal, writing and select the correct start-up control digital data of signal, RVTGROUP GSA address and correct unit controls register address to finish by hardware.
At step S64, this process waits for that all virtual test group RVTGROUP tasks stop.When the virtual test group task of DUT1-DUT3 stops, this system's retrieval passing through/fail message of step S65 at this virtual test group.This process moves on to step S65 subsequently, wherein all test results of the output virtual test group RVTGROUP of this system.At step S66, this procedure command test handler withdraws from DUT1-DUT3 from measuring head.At step S67, the DUT that determines whether this test is last DUT.If stop in this process of step S70; If not, load new DUT and this process get back to step S62 with the process among the repeating step S62-68 up to testing all DUT.
As previously described, in the test macro of a plurality of virtual test instrument of support of the present invention, be dynamically allocated the subsystem of the component of test pin from DUT or SoC, these groups are carried out addressing independently and are used as test macro dispersion, separately by tester hardware, finish set of dispense and selection by a hardware mechanisms, this mechanism allows host computer to write group selection address (GSA) on the pin unit bus.Operating in test on these virtual test instrument can be together or start independently and stop independently.Therefore, the present invention allows to test a plurality of different IC devices simultaneously on a single test macro, and thought of the present invention also is applicable to every pin system of tester or pin group system.
Semiconductor test system of the present invention can be obtained following effect:
(1) allows at inter-sync of SoC device or concurrent testing subsystem asynchronously;
(2) by allowing a plurality of pin unit of multiple programming to quicken the tester configuration;
(3) configuration flexibility;
(4) simplified the hardware controls that a plurality of DUT test;
(5) simplified the software programming of a plurality of DUT system;
Although just illustrate and described preferred embodiment, should understand with reference to top disclosing and in appended claim scope, can make a lot of modifications and variations and can not depart from the spirit and scope of the present invention to the present invention at this.
Claims (16)
1, a kind of semiconductor test system of supporting a plurality of virtual test instrument, being used for testing concurrently a plurality of semiconductor devices comprises:
Host computer is by carrying out the whole service of a semiconductor test system of test procedure control;
A plurality of pin unit, each unit have the device of the semiconductor device to be measured response of the test pattern of test pin of the described semiconductor test system that is used to produce the pin of distributing to semiconductor device to be measured and assessment gained;
The pin unit bus is arranged between described host computer and this a plurality of pin unit, is used for transfer address, data, control signal and clock;
Installing plate is used to install a plurality of semiconductor devices to be measured with from the described test pattern of described a plurality of pin unit parallel receives; And
Be used at the free device that also dynamically reconfigures described a plurality of pin unit of described a plurality of semiconductor devices to be measured, wherein the operation timing of each described pin unit is synchronized with each other or separate asynchronously.
2, according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 1,
Wherein the device that reconfigures described pin unit with respect to described test pin distributes described pin unit according to a group selection address that is placed on by described host computer on the described pin unit bus;
The wherein said device that is used to dispose described pin unit comprises and is arranged in each described pin unit, allows described group selection address to write pin unit write decoder in the described register when being used for the package selection address register when described host computer identifies corresponding pin unit in.
3, according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 1, wherein operate in a plurality of different tests startup simultaneously and termination on a plurality of virtual test instrument, perhaps start independently of one another and termination.
4, according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 1, wherein each described pin unit is assigned to one or more test pin of this semiconductor test system, and the described pin that inputs or outputs of each of the semiconductor device to be measured on the wherein said installing plate is connected to a corresponding described test pin.
5, according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 1, wherein each described pin unit is assigned to one group of test pin of this semiconductor test system, and wherein the number of the test pin in described group run duration at described semiconductor test system under the control of this host computer is changed.
6, according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 1, wherein each described pin unit is assigned to one group of test pin of this semiconductor test system so that each pin unit one in the semiconductor device a plurality of to be measured on the concurrent testing installing plate independently.
7, according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 1, wherein each described pin unit be dynamically allocated to semiconductor test system one group of test pin in case each pin unit as one independently tester work test in the semiconductor device a plurality of to be measured on the installing plate one in such a way, promptly the test operation of a pin unit and other pin unit are to carry out synchronously or asynchronously.
8, according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 1, wherein each described pin unit is assigned to one group of test pin of this semiconductor test system at described semiconductor test system run duration, so that each pin unit as one independently tester work test in the semiconductor device a plurality of to be measured on the installing plate one in such a way, promptly the test operation of a pin unit with other pin unit is or starts dividually and be to stop dividually.
9, according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 2, wherein said pin unit write decoder comprises:
Be used to identify the device that this package is selected the group selection address of the pin unit in the address register;
Be used for receiving the group address data of a group under the destination register in this pin unit of indication so that write the device of test data therein from the pin unit bus;
The device that is used to contrast the group selection address of this pin unit and also when they mate, produces an enable signal from the group address data of pin unit bus; And
Code translator is used for deciphering these group address data this test data is write the destination register in the pin unit when receiving this enable signal.
10,, also comprise the device that is used for after these pin unit of grouping with the timing sequence generating test enable signals of major clock according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 9.
11, according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 1, also comprise from each pin unit producing a device that stops test signal, each pin unit all is assigned with one group of test pin of this semiconductor test system so that as an independently tester job herein.
12, according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 11, wherein this host computer monitors this termination test signal, and stop this test process at the pin unit that produce to stop test signal, proceed the test process in other pin unit simultaneously.
13, according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 11, wherein this host computer monitors this termination test signal, and change semiconductor device to be measured and come to proceed the test process in other pin unit simultaneously for it starts a new test at producing the pin unit that stops test signal.
14, according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 11, wherein this host computer monitors this termination test signal, and reconfigure the grouping of these test pin at the pin unit that produces this termination test signal, think that at the semiconductor device to be measured that this pin unit changes on the installing plate it starts a new test, and proceed the test process in other pin unit simultaneously.
15,, wherein saidly be used to produce the device that stops test signal and comprise that the collection driver of an opening that offers each pin unit is so that send to the pin unit bus to this termination test signal according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 11.
16, according to the semiconductor test system of a plurality of virtual test instrument of the described support of claim 1, further comprise:
Be used to each pin unit to start and stop a test process, be independent of the device that other pin unit is moved this pin unit thus;
Wherein when described host computer is placed on a group selection address on the described pin unit bus, the described device that is used to reconfigure pin unit reconfigures described pin unit with respect to described a plurality of semiconductor devices to be measured.
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| CNB011158840A CN1293387C (en) | 2001-05-11 | 2001-05-11 | Multiple virtual logic tester supported semiconductor test system |
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| CNB011158840A CN1293387C (en) | 2001-05-11 | 2001-05-11 | Multiple virtual logic tester supported semiconductor test system |
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| CN1293387C true CN1293387C (en) | 2007-01-03 |
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| CNB011158840A Expired - Fee Related CN1293387C (en) | 2001-05-11 | 2001-05-11 | Multiple virtual logic tester supported semiconductor test system |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7543200B2 (en) * | 2005-02-17 | 2009-06-02 | Advantest Corporation | Method and system for scheduling tests in a parallel test system |
| US9317351B2 (en) * | 2010-09-07 | 2016-04-19 | Advantest Corporation | System, methods and apparatus using virtual appliances in a semiconductor test environment |
| CN102333005B (en) * | 2011-06-02 | 2014-03-05 | 迈普通信技术股份有限公司 | Tester control method in automatic testing system |
| CN103176119B (en) * | 2011-12-23 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | USB chip silicon chip level auto testing instrument and method of testing |
| CN102608520A (en) * | 2012-03-08 | 2012-07-25 | 无锡华大国奇科技有限公司 | Chip testing system based on USB-IIC (universal serial bus to inter-integrated circuit) protocol |
| CN104572383B (en) * | 2014-11-28 | 2017-05-03 | 深圳市芯海科技有限公司 | ATE (automatic test equipment)-based MCU (microprogrammed control unit)/SOC (system on chip) test method |
| CN110045260A (en) * | 2019-04-03 | 2019-07-23 | 南京邮电大学 | Semiconductor devices virtual measurement platform and semiconductor devices virtual measuring method |
| CN112653598B (en) * | 2020-12-18 | 2022-02-22 | 迈普通信技术股份有限公司 | Automatic testing method, device, equipment and readable storage medium |
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| US4931723A (en) * | 1985-12-18 | 1990-06-05 | Schlumberger Technologies, Inc. | Automatic test system having a "true tester-per-pin" architecture |
| US5225772A (en) * | 1990-09-05 | 1993-07-06 | Schlumberger Technologies, Inc. | Automatic test equipment system using pin slice architecture |
| US6073259A (en) * | 1997-08-05 | 2000-06-06 | Teradyne, Inc. | Low cost CMOS tester with high channel density |
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| US6157200A (en) * | 1996-11-15 | 2000-12-05 | Advantest Corporation | Integrated circuit device tester |
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| US4931723A (en) * | 1985-12-18 | 1990-06-05 | Schlumberger Technologies, Inc. | Automatic test system having a "true tester-per-pin" architecture |
| US5225772A (en) * | 1990-09-05 | 1993-07-06 | Schlumberger Technologies, Inc. | Automatic test equipment system using pin slice architecture |
| US6157200A (en) * | 1996-11-15 | 2000-12-05 | Advantest Corporation | Integrated circuit device tester |
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| US6092225A (en) * | 1999-01-29 | 2000-07-18 | Credence Systems Corporation | Algorithmic pattern generator for integrated circuit tester |
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