CN1667589A - Structure-irrelevant micro-processor verification and evaluation method - Google Patents
Structure-irrelevant micro-processor verification and evaluation method Download PDFInfo
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Abstract
This invention relates to a checking and evaluating method about structure independency micro processing unit (abbreviation THUMPSim), which belongs to the micro processing unit chip checking and evaluating technique field. It is a micro processing unit simulative and checking method which is independent of system structure describing the simulative micro processing unit by facing part structure independency system structure defined method and processing simulated drive by event driven signal renewal arithmetic.
Description
Technical field
The micro-processor verification of structure-irrelevant and evaluating method (THUMPSim) belong to micro-processor verification and evaluation and test technical field
Background technology
In the design and realization technology of micro-processor architecture, the accurate software simulator of clock level signal has crucial researching value and practical significance, it is in the checking of architecture Design, and aspects such as performance evaluation and software-hardware synergism exploitation all play crucial effects.
In the design cycle of microprocessor, after architecture Design work is finished, what at first will do is exactly the logical correctness of checking design, that is to say and to check that whether this architecture can both normally be moved in all cases and do not go wrong, and further also will evaluate and test design and whether reach every technical performance index.It all is to rely on the microprocessor Design personnel to write out corresponding RTL level (register transfer level) hardware description code (abbreviation RTL code) that these checking evaluation and tests are operated in over, utilizes eda software instrument or FPGA to carry out that emulation finishes again.Such mode, need the personnel of awaiting development write out the RTL code on the one hand, and for this huge, baroque hardware design of microprocessor, in general this process is quite very long, and the logic checking of architecture does not need a lot of bottom circuit details of being concerned about that the RLT code relates to; On the other hand, the complicacy of writing and debug of RTL code itself also can be to verifying that evaluation and test work cause adverse effect, and the analog rate of various RTL code emulation devices is quite slow, and building analogue system with FPGA then wastes time and energy, and all is not suitable for carrying out in a short time a large amount of test jobs.We know, for the such project of microprocessor Design, it is quite crucial how finding the problem and shortage on the structural design as soon as possible and being corrected and improve, problem find more early, the cost that corrects is also just few more, if to the design latter stage also to carry out bug patch to the such top-level design of architecture, will be to influence very much the research and development progress.Therefore, only rely on original eda software emulation or FPGA method of emulation, can not satisfy microprocessor Design checking needs well the RTL code.
In order to satisfy the demand of this microprocessor Design checking, people have proposed the scheme of software simulator, promptly simulate the operation details of architecture with the method for software, thereby verify and evaluate and test.Its design philosophy is exactly, at the initial stage of microprocessor Design checking, the characteristics of utilizing software to develop fast, be easy to revise, verify the micro-processor architecture design fast with the method for software simulation, constantly find design mistake and deficiency first, revising for architecture provides foundation, guarantees that to greatest extent the microprocessor Design flow process carries out smoothly.
With respect to the RTL code emulation, this software simulator is indifferent to too much bottom circuit details, only be concerned about the correctness and the performance of the logic aspect of architecture own, therefore the eda software emulation than RTL code is faster on analog rate, also be easy to realize, be suitable as very much the early stage instrument of checking fast of architecture than FPGA emulation.
And this software simulator can also help to carry out the software-hardware synergism exploitation.Because the architecture that software simulator reflected is corresponding to hardware design, so can be with the development and testing platform of software simulator as the microprocessor software kit.Thus, when structural design is just finished, just can develop test, and need not wait until that the microprocessor flow finishes software kits such as compiler, operating system even application programs.By correctness test and the performance evaluating that software is moved on simulator, can find the mistake of software and hardware, can also provide foundation for the improvement of design of hardware and software, thereby really accomplish the collaborative design and the co-verification of software and hardware.
This shows that in microprocessor Design, software simulator occupies important status.
But existing this type of simulator is also fewer, and exists the shortcoming of 4 big classes:
1, the simulator that has has only been simulated the high-rise behavior of micro-processor architecture, can not embody all details of architecture.And, carry out complete checking and evaluation and test to whole architecture Design for software simulator, just must simulate and reproduce all details in the logical design of particular microprocessor architecture.
2, though the simulator that has has embodied all details of architecture, because the details that will simulate is very many, and the not enough optimization of modeling algorithm design itself, cause analog rate slower, make checking evaluation and test work to carry out apace, lost the meaning of software simulator.
3, the simulator that has has been taken into account the requirement of architectural detail and analog rate, but makes the complex structure of simulator own, and modularization is low, and the big and inconvenient debugging of programing work amount is not suitable for the multi-person synergy exploitation.And in order to adapt to the change of hardware design, simulator often needs change repeatedly, and complicated software configuration causes very big difficulty also can for the simulator programming personnel.
4, the simulator that also has is considered lessly aspect portable, such simulator adopts the implementation of formulating the simulator software structure according to architecture mostly, combination closely between the code of simulator itself and the architectural definition code, simulate another kind of architecture, from the beginning simulator will be compiled again, not accomplish code reuse.
Therefore, how the consideration that combines of simulation level, analog rate, modularization and portable these several aspects, make that software simulator has accurate simulation, fast exploitation, revises fast, simulation and characteristic such as transplanting fast fast, just become the key issue in the software simulator research field.
Summary of the invention
The present invention is exactly at this problem in the current microprocessor software simulator research, has proposed irrelevant microprocessor simplation verification and the evaluating method (being called for short THUMPSim) of architecture.Microprocessor internal signal, the parts of THUMPSim simulation all have accurate one-to-one relationship with hardware design, can simulate the action of microprocessor each parts in each clock period, the situation of change of each signal, so can verify and evaluate and test all details of micro-processor architecture logic aspect.THUMPSim is divided into analog platform and two independent sectors of architectural definition with whole simulation system simultaneously, thereby simulator common code and micro-processor architecture definition are separated, and adopt towards parts, with the architectural definition framework of structure-irrelevant, accomplished high portability, guaranteed that simulator has good modularization, had and be easy to develop, be easy to the characteristics revising, be easy to debug.And the event-driven formula signal update algorithm among the THUMPSim has guaranteed that it has higher execution performance, can satisfy the demand of microprocessor architecture design verification.
THUMPSim is describing the microprocessor that will simulate towards the structure-irrelevant architectural definition method of parts, and carries out the simulation and the verification method of the microprocessor that a kind of and architecture that system simulation drives has nothing to do with the signal update algorithm of event-driven formula.System is from the demand of micro-processor architecture design verification and evaluation and test, realized micro-processor architecture simulation fast, accurately, for architecture Design provides quick checking and performance evaluation, and provides platform for the software-hardware synergism exploitation.Its main innovative point is:
1. analog platform is divided into two independent sectors of analog platform and architectural definition, simulator common code and micro-processor architecture definition are separated, improved portability.
2. adopt architectural definition method towards parts, structure-irrelevant, provide the unified Definition form of microprocessor components, adopt precompiler method, as long as provide the interface and the logical definition of parts, program frame just can provide in pretreated process automatically to C++ code that should parts.
3. the form of the definition format of parts and advanced hardware descriptive language is closely similar, is convenient to describe from the simulator to the rtl hdl conversion of code.
4. propose the signal update algorithm of incident drive-type, when reducing the programming complicacy, improved execution efficient and reliability effectively.
5. have perfect implementation record and statistical function, as reference, can compare checking with this to the RTL code, all right evaluation process device performance provides foundation for improving the processor design.
6. support perfect debug function, breakpoint can be set, revise the data and the signal of processor inside, can either debug, can debug the program of moving on the microprocessor again the microprocessor architecture design.
7. the Behavior modeling of part microprocessor peripheral components is provided, has made simulator can be used as system-level simulator, the load operation system provides and the on all four software development environment of hardware system environment.
The invention is characterized in:
It contains following steps successively:
The 1st step: in microprocessor Design, set:
The analog platform modular assembly, it contains:
Top control module, it is the behavior of THUMPSim simulation system by the micro-processor verification and the evaluation and test of calling following other module controls structure-irrelevant of the present invention, wherein contains following two kinds of algorithms:
The parts grouping algorithm, it once determines the precedence relationship between each parts in the microprocessor automatically, contains following steps successively:
The a1 step: the affiliated group number of all parts all is initialized as 0;
The a2 step: all unsettled signals and latch signal are all joined in the abort signal tabulation;
The a3 step: current group number CurrentGroup is initialized as 0;
The a4 step: traversal is searched the parts that all group numbers equal CurrentGroup in parts, if do not find, then algorithm finishes; Otherwise, to each parts that finds, if the input signal of these parts then adds 1 with group number under it not entirely in abort signal tabulation;
The a5 step: traversal is searched the parts that all group numbers equal CurrentGroup in parts, if do not find, then algorithm finishes; Otherwise, the output signal of each parts of finding is all joined in the abort signal tabulation;
The a6 step: current group number CurrentGroup adds 1, goes to a4 step continuation and carries out.
Event-driven formula signal update algorithm, it is carried out once in the cycle at each microprocessor clock, the behavior in the one-period of microprocessor of, evaluation and test to be verified to simulate, it contains following steps successively:
The b1 step: empty pending list of parts;
The b2 step: travel through all signals, if find that change had taken place certain latch signal value in the last clock period, then the parts that it is had influence on (promptly being the parts of input signal with this signal) add in the pending list of parts;
The b3 step: current group number CurrentGroup is initialized as 0;
B4 step: search that group number is the parts of current group number in the pending list of parts,, then go to the b7 step if do not find;
The b5 step: if find, then these parts of Simulation execution are checked its variation of output signals situation, and the parts that the output signal that changes is had influence on add pending list of parts;
The b6 step: these parts are shifted out pending list of parts, go to the b4 step;
The b7 step: current group number CurrentGroup adds 1, if CurrentGroup is less than or equal to maximum group number, then goes to the b4 step;
The b8 step: upgrade latch signal, algorithm finishes;
Pretreatment module to be verified and the evaluation and test microprocessor components defines, it converts the parts definition to the C++ code;
The load-on module of program or instruction stream, it is loaded into program or the instruction stream that will carry out in the above-mentioned simulator;
The peripheral interface unit module, it provides the virtual peripheral interface for program frame;
Mutual display interface module;
Processor architecture definition module assembly, it contains:
The definition module of all signals of processor, definition format is:
The Name territory has defined the title of this signal;
The Type territory has defined the type of this signal, comprises two types of ST_WIRE and ST_REG, corresponds respectively to the line style signal in the advanced hardware descriptive language and deposits type signal (being latch signal);
The Width territory has defined the width of this signal, i.e. number of bits;
The Stage territory has defined this signal segment number under in streamline;
The definition module of all parts of processor, definition format is:
The Component territory, it has comprised following subdomain:
The NAME subdomain defines the title of these parts;
The TYPE subdomain defines the type of these parts, comprises combinational logic (combination), sequential logic (sequence);
INPUT and OUTPUT subdomain, the interface signal of definition component, the input signal of INPUT subdomain definition component wherein, OUTPUT is the output signal of definition component then;
The Variable territory, it defines the local variable of using in this parts definition, and the definition grammer is identical with the C++ grammer;
The Function territory, it defines the local function of using in this parts definition, and the definition grammer is identical with the C++ grammer;
The Initialize territory, it defines the initialization action of these parts, calls execution for analog platform before the beginning dry run;
The Execute territory defines the behavior logic of these parts in a processor clock cycle, calls for analog platform.
Each component logic simulation code module;
Processor internal data molded tissue block;
The 2nd step: simulate and the multiple different microprocessor of description towards parts and with the unified Definition method of structure-irrelevant according to of the present invention according to the following steps successively:
The 2.1st step: calling order sequence or compiled ECOFF form binary file at once after system brings into operation;
The 2.2nd step: analog platform begins the implementation of the defined micro-processor architecture in dry run front, and this simulation process has been used the above-mentioned parts grouping algorithm and the signal update algorithm of event-driven formula;
The 2.3rd step: the state of in operational process, observing and be provided with all parts, signal in each cycle that microprocessor carries out by the interactive interface module, and by debug function microprocessor architecture design and working procedure are debugged, find the mistake of design;
The 2.4th step: after system simulation is finished, obtain corresponding performance statistics parameter and the track record file that comprises register, Cache, main memory, these parts of TLB.
THUMPSim has simulated all parts of microprocessor operation and the variation details of signal, and for some essential microprocessor peripheral components have also been simulated by the operation system, owing to adopted the signal update algorithm of incident drive-type, make analog rate still very fast, satisfy the needs of microprocessor architecture design quick checking in early stage and evaluation and test and software development fully.
According to our test, on the computing machine of a Celeron 1.7G CPU that Windows XP Professional operating system is installed, 512M DDR266 internal memory, under the same conditions to same architecture---Tsing-Hua University's THUMP107 micro-processor architecture is simulated, dry run (SuSE) Linux OS start-up course, the averaging analog speed of THUMPSim is per second 6.09 * 10
4The individual clock period, the averaging analog speed of the NC-Verilog Software tool of the Cadence company that EDA emulation tool medium velocity is the fastest then is per second 3.31 * 10
3The individual clock period.Therefore, the analog rate of THUMPSim is more than ten times to tens times of general EDA emulation tool analog rate.
Description of drawings:
Fig. 1. the principle synoptic diagram of the method for the invention.
Fig. 2. the structural drawing of analog platform of the present invention.[0]
Embodiment:
This method is when guaranteeing higher simulated performance, maximize configurable, the reusable ability of software simulator as much as possible, for the architectural definition of microprocessor provides standardized unified interface, it is irrelevant that simulator is accomplished with microprocessor architecture, thereby have maximum transfer ability.
It contains have the following steps (as shown in Figure 1) successively:
1. define the microprocessor architecture that to simulate according to THUMPSim architectural definition method;
2.THUMPSim define all details of constructing this structure according to micro-processor architecture;
3. calling order sequence or compiled ECOFF form binary file at once after bringing into operation;
4. analog platform begins the implementation of the defined micro-processor architecture in dry run front;
5. in operational process, observe and be provided with the state of all parts, signal in each cycle that microprocessor carries out, and microprocessor architecture design and working procedure are debugged, find the mistake of design by debug function by interactive interface;
6. after Simulation execution finishes, obtain the track record file of parts such as corresponding performance statistics parameter and register, Cache, main memory, TLB, for the improved system structural design provides foundation, also the RTL code debugging for the later stage provides the contrast foundation.
The THUMPSim system architecture is seen accompanying drawing 2, is divided into analog platform (grey module among Fig. 2) and processor architecture definition (the white module among Fig. 2) two large divisions.The former has comprised the mutual display interface of load-on module, peripheral interface unit and simulator of pretreatment module, program or instruction stream of master control part, the microprocessor components definition of simulator, and the latter comprises the specific data structure of signals all in the micro-processor architecture and parts definition and CPU inside.
In the THUMPSim analog platform, the master control part is by calling the behavior of the whole simulator of other module controls, pretreatment module converts the parts definition to the C++ code, and program that load-on module will be carried out or instruction stream are loaded in the simulator, and interface module then is responsible for and the user carries out alternately.
In the THUMPSim architectural definition part, unified interface specification is all adopted in signal and parts definition, program frame provides virtual interface, and the architectural definition personnel only need declare the interface signal of specific data structure in the microprocessor, all signal, each parts and internal logic the behavior logic of a processor clock cycle inner part (promptly) and get final product.
Simulator by each parts internal logic and parts between the interconnected relationship that reflects by interface signal construct the integral framework structure of whole microprocessor.Therefore, the architecture of microprocessor is only relevant with the definition of signal, parts, modification to some parts even whole architecture all only needs the definition of corresponding signal of change and parts to get final product, so just accomplished that analog platform and architecture are irrelevant, made simulator have maximum portability.
The architectural definition standard:
In order to adapt to demands such as high portability, modularization, many people fast synergistic exploitation debugging, THUMPSim has used unified towards parts, and the architectural definition method of structure-irrelevant, comprises that signal definition and parts define the two large divisions.This definition mode makes THUMPSim when the micro-processor architecture of simulation different instruction collection or various flows line structure, and the framework of simulator itself does not need to do change, only needs the relevant signal of change, parts definition to get final product.
The signal definition of THUMPSim leaves in the special defined file, and definition format is as follows:
SIGNAL_DEFINE (Name, Type, Width, Stage), wherein:
The Name territory has defined the title of this signal
The Type territory has defined the type of this signal, comprises two types of ST_WIRE and ST_REG, corresponds respectively to the line style signal in the advanced hardware descriptive language and deposits type signal (being latch signal).
The Width territory has defined the width of this signal, i.e. number of bits.
The Stage territory has defined this signal segment number under in streamline.
Parts of each DEF document definition are left in the * .DEF file in the parts definition of THUMPSim in.A kind of form that is similar to the advanced hardware descriptive language is adopted in the parts definition, is handled before compiling by preprocessor, generates corresponding C ++ code.Do making the architectural definition personnel need not be concerned about too much simulator programming details like this, need not write the C++ code of a large amount of repetitions, and be convenient to the modification of each parts definition.And also be convenient to from the software simulator to the rtl hdl, describe the transplanting of code with the similar definition format of advanced hardware descriptive language.
Comprise Component, Variable, Function, Initialize and five kinds of field of definition of Execute in the parts definition format of THUMPSim, specify as follows:
1, the Component territory:
Comprised NAME, TYPE, INPUT, four kinds of subdomains of OUTPUT:
The NAME subdomain defines the title of these parts;
The TYPE subdomain defines the type of these parts, comprises combinational logic (combination), sequential logic (sequence);
The interface signal of INPUT and OUTPUT subdomain definition component, the input signal of INPUT subdomain definition component wherein,
OUTPUT is the output signal of definition component then.
2, the Variable territory:
Define the local variable of using in this parts definition, the definition grammer is with the C++ grammer.
3, the Function territory:
Define the local function of using in this parts definition, the definition grammer is with the C++ grammer.
4, the Initialize territory:
Define the initialization action of these parts, before the beginning dry run, call execution for analog platform.
5, the Execute territory:
Define the behavior logic of these parts in a processor clock cycle, call for analog platform.
The signal update algorithm of parts grouping algorithm and event-driven formula:
In fact the execution of using software to simulate microprocessor is exactly the variation of simulating each signal, and the variation of signal causes by the parts action, so signal update just relies on execution unit to move to finish.At the hardware upper-part all is executed in parallel, and software program is serial execution (the high-level language programs person from single-threaded processor is like this at least), so in the process of simulation, need a kind of mechanism, can guarantee the correctness of serial program analog hardware executed in parallel logic, obtain again than higher execution efficient.The signal update algorithm of THUMPSim has adopted the thought of incident drive-type, only simulate the parts that exist input signal to change in the current period, other combiner then need not be carried out simulation, and guarantee in the same clock period, can repeatedly not simulate same parts because of the variation of a plurality of input signals, make the efficient of Simulation execution improve greatly.The prerequisite of signal update algorithm is determining of parts simulation precedence relationship, be responsible for once generating automatically this relation by a parts grouping algorithm among the THUMPSim, do not need the architectural definition personnel to specify by hand, under the prerequisite that guarantees the Simulation execution logical correctness, reduce programming personnel's workload, thereby accelerated development process.
The automatic grouping algorithm of the parts of THUMPSim is carried out when starting by simulator, and only need carry out once, and arthmetic statement is as follows:
1. the affiliated group number with all parts all is initialized as 0;
2. all unsettled signals and latch signal are all joined in the abort signal tabulation;
3. current group number CurrentGroup is initialized as 0;
4. traversal is searched the parts that all group numbers equal CurrentGroup in parts, if do not find, then algorithm finishes; Otherwise, to each parts that finds, if the input signal of these parts then adds 1 with group number under it not entirely in abort signal tabulation;
5. traversal is searched the parts that all group numbers equal CurrentGroup in parts, if do not find, then algorithm finishes; Otherwise, the output signal of each parts of finding is all joined in the abort signal tabulation;
6. current group number CurrentGroup adds 1, goes to 4 and continues to carry out.
The signal update algorithm of THUMPSim is carried out once in the cycle at each microprocessor clock, is responsible for the behavior of a simulation clock period of microprocessor, and arthmetic statement is as follows:
1. empty pending list of parts;
2. travel through all signals, if find that change had taken place certain latch signal value in the last clock period, then the parts that it is had influence on (promptly being the parts of input signal with this signal) add in the pending list of parts;
3. current group number CurrentGroup is initialized as 0;
4. search that group number is the parts of CurrentGroup in the pending list of parts,, then go to 7 if do not find;
5. these parts of Simulation execution are checked its variation of output signals situation, and the parts that the output signal that changes is had influence on add pending list of parts;
6. these parts are shifted out pending list of parts, go to 4;
7. current group number CurrentGroup adds 1, if CurrentGroup is less than or equal to maximum group number, then goes to 4;
8. renewal latch signal, algorithm finishes;
Illustrate: for each latch signal, simulator has been safeguarded two values, the initial value of a signal when being used for depositing present clock period and beginning, read in this cycle for parts, another is used for depositing the new value that produces in this cycle, in the final step of signal update algorithm is end of term this week during tail, and new value can be processed, is written in the initial value as required.Do like this is in order to meet the characteristic of latch signal.
Claims (1)
1. the micro-processor verification of structure-irrelevant and evaluating method is characterized in that, it contains following steps successively:
The 1st step: in microprocessor Design, set:
The analog platform modular assembly, it contains:
Top control module, it is the behavior of THUMPSim simulation system by the micro-processor verification and the evaluation and test of calling following other module controls structure-irrelevant of the present invention, wherein contains following two kinds of algorithms:
The parts grouping algorithm, it once determines the precedence relationship between each parts in the microprocessor automatically, contains following steps successively:
The a1 step: the affiliated group number of all parts all is initialized as 0;
The a2 step: all unsettled signals and latch signal are all joined in the abort signal tabulation;
The a3 step: current group number CurrentGroup is initialized as 0;
The a4 step: traversal is searched the parts that all group numbers equal CurrentGroup in parts, if do not find, then algorithm finishes; Otherwise, to each parts that finds, if the input signal of these parts then adds 1 with group number under it not entirely in abort signal tabulation;
The a5 step: traversal is searched the parts that all group numbers equal CurrentGroup in parts, if do not find, then algorithm finishes; Otherwise, the output signal of each parts of finding is all joined in the abort signal tabulation;
The a6 step: current group number CurrentGroup adds 1, goes to a4 step continuation and carries out.
Event-driven formula signal update algorithm, it is carried out once in the cycle at each microprocessor clock, the behavior in the one-period of microprocessor of, evaluation and test to be verified to simulate, it contains following steps successively:
The b1 step: empty pending list of parts;
The b2 step: travel through all signals, if find that change had taken place certain latch signal value in the last clock period, then the parts that it is had influence on (promptly being the parts of input signal with this signal) add in the pending list of parts;
The b3 step: current group number CurrentGroup is initialized as 0;
B4 step: search that group number is the parts of current group number in the pending list of parts,, then go to the b7 step if do not find;
The b5 step: if find, then these parts of Simulation execution are checked its variation of output signals situation, and the parts that the output signal that changes is had influence on add pending list of parts;
The b6 step: these parts are shifted out pending list of parts, go to the b4 step;
The b7 step: current group number CurrentGroup adds 1, if CurrentGroup is less than or equal to maximum group number, then goes to the b4 step;
The b8 step: upgrade latch signal, algorithm finishes;
Pretreatment module to be verified and the evaluation and test microprocessor components defines, it converts the parts definition to the C++ code;
The load-on module of program or instruction stream, it is loaded into program or the instruction stream that will carry out in the above-mentioned simulator;
The peripheral interface unit module, it provides the virtual peripheral interface for program frame;
Mutual display interface module;
Processor architecture definition module assembly, it contains:
The definition module of all signals of processor, definition format is:
The Name territory has defined the title of this signal;
The Type territory has defined the type of this signal, comprises two types of ST_WIRE and ST_REG, corresponds respectively to the line style signal in the advanced hardware descriptive language and deposits type signal (being latch signal);
The Width territory has defined the width of this signal, i.e. number of bits;
The Stage territory has defined this signal segment number under in streamline;
The definition module of all parts of processor, definition format is:
The Component territory, it has comprised following subdomain:
The NAME subdomain defines the title of these parts;
The TYPE subdomain defines the type of these parts, comprises combinational logic (combination), sequential logic (sequence);
INPUT and OUTPUT subdomain, the interface signal of definition component, the input signal of INPUT subdomain definition component wherein, OUTPUT is the output signal of definition component then;
The Variable territory, it defines the local variable of using in this parts definition, and the definition grammer is identical with the C++ grammer;
The Function territory, it defines the local function of using in this parts definition, and the definition grammer is identical with the C++ grammer;
The Initialize territory, it defines the initialization action of these parts, calls execution for analog platform before the beginning dry run;
The Execute territory defines the behavior logic of these parts in a processor clock cycle, calls for analog platform.
Each component logic simulation code module;
Processor internal data molded tissue block;
The 2nd step: simulate and the multiple different microprocessor of description towards parts and with the unified Definition method of structure-irrelevant according to of the present invention according to the following steps successively:
The 2.1st step: calling order sequence or compiled ECOFF form binary file at once after system brings into operation;
The 2.2nd step: analog platform begins the implementation of the defined micro-processor architecture in dry run front, and this simulation process has been used the above-mentioned parts grouping algorithm and the signal update algorithm of event-driven formula;
The 2.3rd step: the state of in operational process, observing and be provided with all parts, signal in each cycle that microprocessor carries out by the interactive interface module, and by debug function microprocessor architecture design and working procedure are debugged, find the mistake of design;
The 2.4th step: after system simulation is finished, obtain corresponding performance statistics parameter and the track record file that comprises register, Cache, main memory, these parts of TLB.
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| US5845064A (en) * | 1995-09-11 | 1998-12-01 | Digital Equipment Corporation | Method for testing and verification of a CPU using a reference model |
| CN1294495C (en) * | 2004-05-20 | 2007-01-10 | 北京大学 | Simulator structure method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101482891B (en) * | 2008-01-08 | 2011-12-28 | 富士通株式会社 | performance evaluation simulation |
| CN101256217B (en) * | 2008-04-17 | 2011-11-02 | 复旦大学 | High-monitoring coverage percentage on-chip system debug platform |
| CN102854457A (en) * | 2011-07-01 | 2013-01-02 | 康宇星科技(北京)有限公司 | Field programmable gate array (FPGA) evaluating method |
| CN105718661A (en) * | 2016-01-21 | 2016-06-29 | 烽火通信科技股份有限公司 | Universal chip performance verifying device and method |
| WO2017177705A1 (en) * | 2016-04-11 | 2017-10-19 | 浪潮电子信息产业股份有限公司 | Very-large-scale integration circuit (vlsi) formal verification platform and method |
| CN107885652A (en) * | 2016-09-30 | 2018-04-06 | 电信科学技术研究院 | A kind of method and debugger for carrying out software test |
| CN107239400A (en) * | 2017-06-09 | 2017-10-10 | 山东超越数控电子有限公司 | A kind of NandFlash abrasion equilibriums emulation platform |
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