CN102854457A

CN102854457A - Field programmable gate array (FPGA) evaluating method

Info

Publication number: CN102854457A
Application number: CN2011101828877A
Authority: CN
Inventors: 杜和青
Original assignee: KANGYUXING TECHNOLOGY (BEIJING) CO LTD
Current assignee: KANGYUXING TECHNOLOGY (BEIJING) CO LTD
Priority date: 2011-07-01
Filing date: 2011-07-01
Publication date: 2013-01-02

Abstract

The invention relates to a field programmable gate array (FPGA) evaluating method which includes: performing requirement verification on FPGA codes according to an assignment book supplied by a developer; performing checking on codes of FPGA configuration items; performing code rule checking on the FPGA configuration items; performing simulation and verification on the FPGA configuration items; performing time sequence analyzing on an FPGA; and submitting the problems emerging in the processes to an FPGA developer to enable the developer to perform code improvement on the FPGA. Before the FPGA evaluating method is provided, only a designer and a verifier exist in development of the FPGA, and no independent evaluating third party exists. Along with increasingly wide application of the FPGA in the high-grade field and particularly application in the field of aerospace science and technology and precision guided munition, reliability and availability of the FPGA are improved to a very important position by users, and a method for comprehensively evaluating the function of the FPGA is in urgent need. The FPGA evaluating method provides a just and fair FPGA evaluating platform for users from a third party angle and is innovate in the field of FPGA development.

Description

A kind of FPGA evaluating method

Technical field

The present invention relates to the evaluation and test of field programmable logic chip, be specifically related to the evaluation and test of field programmable logic chip code.

Background technology

Chip mainly is divided into two large classes: special IC (application specificintegrated circuits is called for short ASIC) and field programmable logic (Field-ProgrammableGate Arra is called for short FPGA).ASIC is through the chip of typing after manufacturing and designing, and can not change again; FPGA then is the chip that can change design circuit.FPGA has compared its obvious characteristics with the asic chip design, and its product advantage embodies a concentrated reflection of the following aspects:

Without the design processing charges---the cost relevant with ASIC design processing;

Need not special production---utilize product ready-made on the market, shortened the design cycle

Change is flexible---on-the-spot reprogrammable ability.

And the asic chip design then has the aspects such as certain cost advantage and miniaturization and has its corresponding product advantage when large capacity is produced.

Just because of this, FPGA obtains general use in all trades and professions.The application of FPGA product expands to the widely field such as Aero-Space, consumer electronics, automotive electronics, Industry Control, thermometrically from original communication.Along with the expansion of application, thing followed problem is how to guarantee that the design code of FPGA meets the requirement of task.Especially in the application of some special dimensions, such as Aero-Space, just be difficult to go change in case the FPGA of design goes wrong after equipment is worked, and the result who brings is exactly catastrophic, loss also is huge again.This has strict control program to check in FPGA Code Design, checking, delivery process with regard to requiring, simultaneously in order to guarantee reliability and the credibility of control program execution, should carry out these programs by the three parts, namely finish respectively whole flow process by design, checking, evaluation and test three parts.

In the market the Code Design of FPGA itself there has been relevant product with checking, but also do not had to do for the third party specially technology and the product of FPGA evaluation and test.

Summary of the invention

Technical matters to be solved by this invention provides a kind of FPGA evaluating method, and the FPGA code is carried out just independently evaluation and test from aspects such as mission requirements, code quality, function realizations.

The technical scheme that the present invention solves the problems of the technologies described above is as follows:

A kind of FPGA evaluating method comprises:

Step 1: the charter according to exploitation side provides, carry out requirements verification to the FPGA code;

Step 2: FPGA configuration item code is checked;

Step 3: the FPGA configuration item is carried out the coding rule inspection;

Step 4: the FPGA configuration item is carried out emulation and checking;

Step 5: FPGA is carried out time series analysis;

Step 6: the problem that occurs in the said process is submitted to FPGA exploitation side, improve so that exploitation side carries out code to FPGA.

Further, also can comprise the requirements verification result according to the FPGA code in the step 1 of said method, the process of output checking statement of requirements.

Further, also can comprise the check result according to the FPGA configuration item in the step 2 of said method, the process of output configuration item audit report.

Further, also can comprise the coding rule check result according to the FPGA configuration item in the step 3 of said method, the process of output encoder rule audit report.

Further, also can comprise emulation and the result according to the FPGA configuration item in the step 4 of said method, the process of Output simulation checking report.

Further, also can comprise the time series analysis result according to FPGA in the step 5 of said method, the process of output timing analysis report.

Further, also can comprise the report that obtains according in above-mentioned each process in the step 6 in said method and each the further scheme, the process of output checking final report.

Further, said method and each further scheme in, after step 6, can also comprise: repeat step 1 to step 5, and the process of the as a result output regression checking report that obtains according to step 1 to step 5.

Beneficial effect of the present invention is: along with FPGA obtains using more and more widely in high-grade, precision and advanced field, especially in the application in Space Science and Technology and precision guided weapon field, the user brings up to a very important status to the reliabilty and availability of FPGA, evaluates and tests the function of FPGA in the urgent need to a kind of means are arranged comprehensively.And before the present invention, the exploitation of FPGA only has design side and authentication, does not have the third party of independent evaluation and test.The present invention is from third-party angle, and for the user provides just, a fair FPGA evaluation and test platform, this is an innovation at the FPGA development field.

Description of drawings

Fig. 1 is the FPGA evaluation and test platform framework synoptic diagram among the present invention;

Embodiment

Below in conjunction with accompanying drawing principle of the present invention and feature are described, institute gives an actual example and only is used for explaining the present invention, is not be used to limiting scope of the present invention.

Following examples are platforms of integrated various emulation and testing tool, and cover whole process according to the workflow of setting.

Platform framework

As shown in Figure 1, comprise simulating, verifying environment, DUT (Device Under Test, proving installation) and test case (Test Bench), wherein the simulating, verifying environment has comprised design environment, triplication redundancy instrument, operating system and simulation validation tool.

Workflow of the present invention comprises:

1. third-party authentication demand: according to the charter that exploitation side provides, do the demand analysis of FPGA code verification.Output: third-party authentication statement of requirements.

2.FPGA code walkthrough: FPGA configuration item to be measured is checked the rear formation questionnaire of pinpointing the problems.Output: Walkthrough report.

3. third party's coding rule checks: adopt specific purpose tool FPGA configuration item to be measured to be carried out the coding rule inspection, the rear formation questionnaire of pinpointing the problems.Output: third party's coding rule audit report

4. third party's simulating, verifying plan: FPGA configuration item to be measured is done the simulating, verifying plan.Output: third party's simulating, verifying planning report.

5. implement the simulating, verifying process: adopt specific purpose tool that FPGA configuration item to be measured is carried out emulation and checking.Output: third party's simulating, verifying report.

6. time series analysis: adopt specific purpose tool that FPGA to be measured is carried out time series analysis.Output: third party's time series analysis report.

7. checking is summed up: after finishing above process, the output file of each process is done analysis and summary.Output: third-party authentication final report.

8. return checking: the problem of finding in the evaluation and test process is submitted to FPGA exploitation side, after exploitation side improves code, do again checking.Output: the third party returns the checking report.

Before the present invention, the exploitation of FPGA only has design side and authentication, does not have the third party of independent evaluation and test.Along with FPGA obtains using more and more widely in high-grade, precision and advanced field, especially in the application in Space Science and Technology and precision guided weapon field, the user brings up to a very important status to the reliabilty and availability of FPGA, evaluates and tests the function of FPGA in the urgent need to a kind of means are arranged comprehensively.The present invention is from third-party angle, and for the user provides just, a fair FPGA evaluation and test platform, this is an innovation at the FPGA development field.

The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. a FPGA evaluating method is characterized in that, comprising:

Step 2: FPGA configuration item code is checked;

Step 3: the FPGA configuration item is carried out the coding rule inspection;

Step 4: the FPGA configuration item is carried out emulation and checking;

Step 5: FPGA is carried out time series analysis;

2. FPGA evaluating method according to claim 1 is characterized in that, also comprises the requirements verification result according to the FPGA code in the step 1, the process of output checking statement of requirements.

3. FPGA evaluating method according to claim 1 is characterized in that, also comprises the check result according to the FPGA configuration item in the step 2, the process of output configuration item audit report.

4. FPGA evaluating method according to claim 1 is characterized in that, also comprises the coding rule check result according to the FPGA configuration item in the step 3, the process of output encoder rule audit report.

5. FPGA evaluating method according to claim 1 is characterized in that, also comprises emulation and the result according to the FPGA configuration item in the step 4, the process of Output simulation checking report.

6. FPGA evaluating method according to claim 1 is characterized in that, also comprises the time series analysis result according to FPGA in the step 5, the process of output timing analysis report.

7. according to claim 1 to 6 each described FPGA evaluating methods, it is characterized in that, also comprise the report that obtains according in above-mentioned each process in the step 6, the process of output checking final report.

8. according to claim 1 to 6 each described FPGA evaluating methods, it is characterized in that, after step 6, also comprise: repeat step 1 to step 5, and verify the process of report according to the as a result output regression that step 1 to step 5 obtains.