CN109299530B - Simulation test case generation method, system, storage medium and terminal - Google Patents
Simulation test case generation method, system, storage medium and terminal Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The invention discloses a simulation test case generation method, a system, a storage medium and a terminal, wherein the method comprises the following steps: setting constraints based on design input specifications; reading in a design to be verified; extracting key signals of the design and corresponding state machines; generating corresponding reachability attributes for the state machine; formal verification of the design, the constraints, and the reachability attributes; wherein the reachability attribute is used to generate a test case; minimizing the generated test cases, including removing input signals in the test cases that are not related to both the reachability attribute and the constraints and/or removing duplicate test cases; simulating the test case after the minimization operation and calculating the simulation coverage rate; and analyzing the simulated loopholes and the unreachable attributes by adopting formal verification. The early application of the method for verifying the form automatically generates the test case, and achieves higher coverage rate before manual intervention as much as possible.
Description
Technical Field
The invention relates to the field of integrated circuit function verification, in particular to a simulation test case generation method, a system, a storage medium and a terminal.
Background
Simulation verification is an important means of chip design function verification. The first step in simulation verification is the generation of test cases. The conventional test case generation method is to manually generate test cases for each specification according to a design specification manual, and the test cases satisfy a certain coverage requirement, for example, a certain ratio of design codes must be run in the test. Manually generating all test cases is both time consuming and error prone, and often fails to meet the specified coverage requirements.
Constraint-based test case generation is more common in modern simulation testing, such as the UVM method in SystemVerilog. The advantage is that test cases do not need to be generated piece by piece. But it is a time consuming task to have to build constraints in advance that meet design specifications. The coverage rate must be improved by debugging the constraint at a later stage.
Since the difficulty of functional verification increases exponentially with the design scale in theory, it takes up 70% of the entire chip design process. As simulation of an important means of functional verification, the coverage rate of the method is improved as much as possible by an early manual scheme or a constraint-based scheme, or is compensated by a form verification technology at the later stage, so that the method is a relatively time-consuming and non-automatic process. The generation of the automated simulated overlay test will greatly improve the efficiency of the design verification and even the overall design process.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a simulation test case generation method, a system, a storage medium and a terminal, which improve the efficiency of design verification and even the whole design process.
The aim of the invention is realized by the following technical scheme: a simulation test case generation method comprises the following steps:
setting constraints based on design input specifications;
reading in a design to be verified;
extracting key signals of the design and corresponding state machines;
generating corresponding reachability attributes for the state machine;
formal verification of the design, the constraints, and the reachability attributes; wherein reachable reachability attributes are used to generate test cases, and unreachable reachability attributes are used to correct coverage criteria;
minimizing the generated test cases, including removing input signals in the test cases that are not related to both the reachability attribute and the constraints and/or removing duplicate test cases;
simulating the test case after the minimization operation and calculating the simulation coverage rate; and after the overlay attribute is regenerated for the simulated loopholes and the unreachable attributes, adopting form verification to analyze.
Further, the key signals include: which is itself one or more of the state signals of a state machine in a design, the control signals of a first-in first-out, the instruction pointer, the state memory and the bus with a width exceeding a certain value.
Further, after extracting the key signals of the design, the corresponding state machine is then extracted through structural analysis and/or logic analysis of the netlist.
Further, after the step of extracting the key signals of the design and the corresponding state machines, the method further comprises:
delete part of the key signals and corresponding state machines and/or add more key signals and corresponding state machines.
The invention also provides a simulation test case generation system, which comprises:
constraint setting module: for setting constraints based on design input specifications;
and (3) designing a read-in module: for reading in a design to be verified;
and an extraction module: the system comprises a state machine, a control unit and a control unit, wherein the state machine is used for extracting key signals of the design and corresponding state machines;
reachability attribute generation module: for generating respective reachability attributes for said state machine;
the test case generation module: for formal verification of the design, the constraints, and the reachability attributes; wherein reachable reachability attributes are used to generate test cases, and unreachable reachability attributes are used to correct coverage criteria;
the test case optimizing module: minimizing the generated test cases, including removing input signals in the test cases that are not related to both the reachability attribute and the constraints and/or removing duplicate test cases;
and (3) a simulation module: simulating the test case after the minimization operation and calculating the simulation coverage rate;
coverage attribute generation and form verification module: and after the overlay attribute is regenerated for the simulated loopholes and the unreachable attributes, adopting form verification to analyze.
Further, the key signals include: which is itself one or more of the state signals of a state machine in a design, the control signals of a first-in first-out, the instruction pointer, the state memory and the bus with a width exceeding a certain value.
Further, after extracting the key signals of the design, the corresponding state machine is then extracted through structural analysis and/or logic analysis of the netlist.
Further, the system further comprises:
signal and state machine selection module: the processing module is used for processing the key signals and the corresponding state machines extracted by the extracting module, including deleting part of the key signals and the corresponding state machines and/or adding more key signals and the corresponding state machines.
The invention also provides a storage medium having stored thereon computer instructions which, when run, perform the steps of the simulation test case generation method.
The invention also provides a terminal, which comprises a memory and a processor, wherein the memory stores computer instructions capable of running on the processor, and the processor executes the steps of the simulation test case generation method when running the computer instructions.
The beneficial effects of the invention are as follows:
(1) The invention has the main advantages that the early application of the form verification method automatically generates the test case, and reaches a higher coverage rate as far as possible before manual intervention.
While the present invention also applies to constraints, these directly originate from the specification of the design inputs, unlike constraints in constraint-based test generation, which tend to be for a class of tests, which require different constraints.
The test case optimization of the present invention minimizes testing such that a case can be applied multiple times for greater coverage because of random selection of design inputs.
In addition, in the last step, the method also uses the loopholes and the unreachables of the existing form verification method, so that the constraint-based, random test, loopholes and the unreachable analysis are organically combined into the automatic extraction-based test generation flow, and the advantages of the four are brought into full play with maximum efficiency.
(2) The method steps of the invention are realized in an automatic mode, and the method can be realized without the intervention of peripheral personnel. The simulation test case generation system, the storage medium and the terminal provided by the invention also solve the corresponding technical problems.
Drawings
FIG. 1 is a flow chart of the method of the present invention;
FIG. 2 is a state machine attribute diagram of the present invention;
FIG. 3 is a block diagram of a system of the present invention;
fig. 4 is a schematic diagram of a terminal connection according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully understood from the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Example 1
Embodiment 1 provides a simulation test case generation method for realizing automatic generation, coverage rate simulation detection and subsequent analysis of a simulation test case. Specifically, as shown in fig. 1, the method includes the steps of:
s1: constraints based on design input specifications are set.
Wherein, compared with the constraint in the test case row generating process, the method adopts the constraint based on the design input end specification. Constraints in the test case string generation process are often for a certain class of test, while different constraints are required for different classes of test.
S2: the design to be verified is read in.
Typically, the design includes any chip design content, such as a CPU, GPU, embedded controller, and the like. While chip designs are typically described in a hardware design language, such as SystemVerilog, VHDL.
In the present embodiment, however, the design is verified by the EDA tool for the verified design.
S3: analyzing the design, and extracting key signals and corresponding state machines of the design.
Wherein, in a preferred scheme of the present embodiment, the default conditions of the key signal include one or more of the following conditions: the state signal, the first-in first-out control signal, the instruction pointer, the state memory and the bus with the width exceeding a certain value of the state machine in one design are adopted.
In addition, the user can specify any signal of interest to him and set the threshold for the broadband of the bus.
After extracting the key signals, the state machine may then be extracted through structural analysis or logic analysis of the netlist.
In a preferred aspect of this embodiment, after this step, the method further includes:
s3': the user may delete a portion of the key signal and corresponding state machine and/or add more key signals and corresponding state machines.
S4: generating corresponding reachability attributes for the state machine;
in this step the state machine attributes are then automatically generated, as in fig. 2, and the state machine attributes are divided into three categories: the reachability of the state, the reachability of the state transition, and finally the stateless deadlock.
Fig. 2 is an example of an arbiter, with four states representing possible combinations of two key signals Ack0 and Robin in the arbiter. For example, state 10 represents Ack0 as 1 and robin as 0. The arrow marked d represents the transition from state 10 to state 00, i.e., the state machine enters the 00 state when state 10 and the input is d.
That is, in this example, each state in FIG. 2 corresponds to a state reachable and deadlock free attribute, while each transition (an arrow) corresponds to a transition reachable attribute.
In addition, as shown in fig. 1, after this step, a new coverage attribute determination step is preferably included.
Specifically, since the automatic generation in step S4 is a loop process, the initial coverage attribute is generated by the key signal state machine. Reachability attributes generate simulation cases, and unreachable attributes are accumulated in a pool of unreachable attributes. After the simulation is driven with the simulation cases generated in step S7 and the simulation coverage is collected, the coverage hole is used to regenerate coverage properties, which are first compared with the unreachable properties library, and if included, are not new coverage properties. And the new overlay attribute is validated in form and a second cycle (i.e., the contents of step S7) is performed.
S5: formal verification of the design, the constraints, and the reachability attributes; wherein reachable reachability attributes are used to generate test cases and unreachable reachability attributes are used to correct coverage criteria.
Specifically, in the formal verification method, when a reachability attribute is verified (reachability is established) and a deadlock-free (a particular reachability) attribute is verified, the verification algorithm automatically generates a set of input signal sequences that, when driving the design to be verified in sequence, bring the design from its initial state to the state described by the reachability attribute (or, for the deadlock-free attribute, to a state loop, forming a deadlock). This is a simulation process and the set of signals is also referred to as simulated test cases.
That is, both for the case where reachability is proven and the case where no status deadlock is witnessed, the automatic generation of test cases for witnessing these proofs (i.e. any of the three classes containing the state machine attributes mentioned in step S4) will be triggered.
S6: minimizing the generated test cases includes removing input signals from the test cases that are not related to both the reachability attribute and the constraints and/or removing duplicate test cases.
Each test case optimized by the step can be randomly assigned to a plurality of tests due to possible unassigned inputs, so that a case can be applied for a plurality of times due to the random selection of design inputs, thereby achieving larger coverage rate.
S7: simulating the test case after the minimization operation and calculating the simulation coverage rate; and after the overlay attribute is regenerated for the simulated loophole and the unreachable attribute, the overlay attribute is analyzed by adopting form verification (returning to the step S4).
Reverse reachability attributes of vulnerabilities and inaccessibility, which are demonstrated by an analytical instant form verification method. As with the previous reachability attribute verification results, one class of reachability is verified and a third class of reachability is verified, and the formal verification tool can generate test cases to cover these vulnerabilities.
Example 2
The embodiment provides a simulation test case generation system, which has the same inventive concept as that of embodiment 1 and is used for realizing automatic generation, coverage rate simulation detection and subsequent analysis of simulation test cases. Specifically, as shown in fig. 3, the system includes:
constraint setting module: for setting constraints based on design input specifications;
and (3) designing a read-in module: for reading in a design to be verified;
and an extraction module: the system comprises a state machine, a control unit and a control unit, wherein the state machine is used for extracting key signals of the design and corresponding state machines;
reachability attribute generation module: for generating respective reachability attributes for said state machine;
the test case generation module: for formal verification of the design, the constraints, and the reachability attributes; wherein reachable reachability attributes are used to generate test cases, and unreachable reachability attributes are used to correct coverage criteria;
the test case optimizing module: minimizing the generated test cases, including removing input signals in the test cases that are not related to both the reachability attribute and the constraints and/or removing duplicate test cases;
and (3) a simulation module: simulating the test case after the minimization operation and calculating the simulation coverage rate;
coverage attribute generation and form verification module: and after the overlay attribute is regenerated for the simulated loopholes and the unreachable attributes, adopting form verification to analyze.
Specifically, as shown in fig. 3, the design constraint in the diagram includes a constraint setting module, the form verification and automatic coverage in the diagram includes a design reading-in module, an extraction module, a reachability attribute generation module, a test case generation module and a test case optimization module, the simulation in the diagram includes a simulation module, the simulation coverage in the diagram includes a part of the coverage attribute generation and form verification module for regenerating the coverage attribute for the simulated vulnerability and unreachable attribute, and the analysis of the coverage attribute generation and the form verification module by adopting the form verification belongs to the form verification and automatic coverage in the diagram.
More preferably, in this embodiment, the key signals include: which is itself one or more of the state signals of a state machine in a design, the control signals of a first-in first-out, the instruction pointer, the state memory and the bus with a width exceeding a certain value.
Preferably, in the present embodiment, after extracting the key signals of the design, the corresponding state machines are then extracted through structural analysis and/or logic analysis of the netlist.
More preferably, in this embodiment, the system further includes:
signal and state machine selection module: the processing module is used for processing the key signals and the corresponding state machines extracted by the extracting module, including deleting part of the key signals and the corresponding state machines and/or adding more key signals and the corresponding state machines.
The description of the relevant parts in the simulation test case generation system provided by the embodiment of the present invention is referred to the detailed description of the corresponding parts in the simulation test case generation method provided by the embodiment 1 of the present invention, and will not be repeated here. In addition, in the above technical solutions provided in the embodiments of the present invention, the parts consistent with the implementation principles of the corresponding technical solutions in the prior art are not described in detail, so that redundant descriptions are avoided.
Example 3
Based on the implementation of embodiment 1, the embodiment also provides a storage medium having stored thereon computer instructions that, when executed, perform the steps of a simulation test case generation method as described in embodiment 1.
Based on such understanding, the technical solution of the present embodiment may be essentially or a part contributing to the prior art or a part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only memory (ROM), a random access memory (RandomAccessMemory, RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
Example 4
Based on the implementation of embodiment 1, this embodiment further provides a terminal, including a memory and a processor, where the memory stores computer instructions that can be executed on the processor, and the processor executes the steps of a simulation test case generating method described in embodiment 1 when executing the computer instructions.
The functional units in the embodiments provided in the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
As shown in fig. 4, one of the ways of this embodiment is that the formal verification part and the simulation part are run on different processors, respectively. Yet another way in this embodiment is for all parts to run on a unified processor.
In all embodiments provided herein, it should be understood that the disclosed apparatus and methods may be implemented in other ways. The above-described apparatus embodiments are merely illustrative, for example, the division of the units/modules is merely a logical function division, and there may be additional divisions when actually implemented, and for example, multiple units or modules may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
It is apparent that the above examples are given by way of illustration only and not by way of limitation, and that other variations or modifications may be made in the various forms based on the above description by those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.
Claims (10)
1. A simulation test case generation method is characterized in that: the method comprises the following steps:
setting constraints based on design input specifications;
reading in a design to be verified;
extracting key signals of the design and corresponding state machines;
generating corresponding reachability attributes for the state machine;
formal verification of the design, the constraints, and the reachability attributes; wherein reachable reachability attributes are used to generate test cases, and unreachable reachability attributes are used to correct coverage criteria;
minimizing the generated test cases, including removing input signals in the test cases that are not related to both the reachability attribute and the constraints and/or removing duplicate test cases; each test case optimized by the step can be randomly assigned to form a plurality of tests due to possible unassigned input, and one case can be applied for a plurality of times due to the random selection of design input;
simulating the test case after the minimization operation and calculating the simulation coverage rate; and after the overlay attribute is regenerated for the simulated loopholes and the unreachable attributes, adopting form verification to analyze.
2. The method for generating simulated test cases as claimed in claim 1, wherein: the key signals include: which is itself one or more of the state signals of a state machine in a design, the control signals of a first-in first-out, the instruction pointer, the state memory and the bus with a width exceeding a certain value.
3. The method for generating simulated test cases as claimed in claim 1, wherein: after extracting the key signals of the design, the corresponding state machines are then extracted through structural analysis and/or logic analysis of the netlist.
4. The method for generating simulated test cases as claimed in claim 1, wherein: after the step of extracting the key signals of the design and the corresponding state machines, the method further comprises the following steps:
delete part of the key signals and corresponding state machines and/or add more key signals and corresponding state machines.
5. A simulation test case generation system, characterized in that: comprising the following steps:
constraint setting module: for setting constraints based on design input specifications;
and (3) designing a read-in module: for reading in a design to be verified;
and an extraction module: the system comprises a state machine, a control unit and a control unit, wherein the state machine is used for extracting key signals of the design and corresponding state machines;
reachability attribute generation module: for generating respective reachability attributes for said state machine;
the test case generation module: for formal verification of the design, the constraints, and the reachability attributes; wherein reachable reachability attributes are used to generate test cases, and unreachable reachability attributes are used to correct coverage criteria;
the test case optimizing module: minimizing the generated test cases, including removing input signals in the test cases that are not related to both the reachability attribute and the constraints and/or removing duplicate test cases; each test case after optimization can be randomly assigned to form a plurality of tests due to possible unassigned input, and thus, one case can be applied for a plurality of times due to the random selection of design input;
and (3) a simulation module: simulating the test case after the minimization operation and calculating the simulation coverage rate;
coverage attribute generation and form verification module: and after the overlay attribute is regenerated for the simulated loopholes and the unreachable attributes, adopting form verification to analyze.
6. The simulated test case generation system of claim 5, wherein: the key signals include: which is itself one or more of the state signals of a state machine in a design, the control signals of a first-in first-out, the instruction pointer, the state memory and the bus with a width exceeding a certain value.
7. The simulated test case generation system of claim 5, wherein: after extracting the key signals of the design, the corresponding state machines are then extracted through structural analysis and/or logic analysis of the netlist.
8. The simulated test case generation system of claim 5, wherein: the system further comprises:
signal and state machine selection module: the processing module is used for processing the key signals and the corresponding state machines extracted by the extracting module, including deleting part of the key signals and the corresponding state machines and/or adding more key signals and the corresponding state machines.
9. A storage medium having stored thereon computer instructions, characterized by: the computer instructions, when executed, perform the steps of a simulated test case generation method of any of claims 1 to 4.
10. A terminal comprising a memory and a processor, said memory having stored thereon computer instructions executable on said processor, characterized in that said processor executes the steps of a simulation test case generation method according to any of claims 1 to 4 when said computer instructions are executed.
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| CN110311977B (en) * | 2019-07-01 | 2022-03-08 | 成都奥卡思微电科技有限公司 | Form verification platform based on cloud computing and method thereof |
| CN110287630A (en) * | 2019-07-01 | 2019-09-27 | 成都奥卡思微电科技有限公司 | A kind of chip form verification method, storage medium, terminal and the system of opening |
| CN112749526A (en) * | 2019-10-30 | 2021-05-04 | 瑞昱半导体股份有限公司 | Power rail design method, apparatus and non-transitory computer readable medium thereof |
| CN110990263B (en) * | 2019-11-09 | 2024-03-15 | 上海集成电路研发中心有限公司 | Automatic generator and generation method of test case set |
| CN111539174B (en) * | 2020-07-08 | 2020-11-06 | 成都奥卡思微电科技有限公司 | Regression testing method, storage medium and system based on proof kernel |
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