CN115455876B - Method for debugging logic system design and electronic equipment - Google Patents
Method for debugging logic system design and electronic equipment Download PDFInfo
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- CN115455876B CN115455876B CN202211150883.5A CN202211150883A CN115455876B CN 115455876 B CN115455876 B CN 115455876B CN 202211150883 A CN202211150883 A CN 202211150883A CN 115455876 B CN115455876 B CN 115455876B
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Abstract
The application relates to the technical field of computer application, and particularly discloses a method for debugging logic system design and electronic equipment, wherein the method comprises the following steps: receiving an instruction to select a debug object in a graphical debug tool, the debug object comprising one or more design elements; determining a characterization of the one or more design elements; generating a graphic window in the debugging tool according to the feature description, wherein the graphic window is used for displaying information of the one or more design elements in a drag operation. According to the application, the information of one or more design elements of the selected debugging object in the drag operation is displayed through the graphical interface, so that a user can conveniently judge whether the currently selected debugging object comprises the design elements to be debugged, the user can adjust the selected debugging object, unnecessary drag operation to a function window to check signals is reduced, the debugging efficiency is improved, and the time cost of the user is reduced.
Description
Technical Field
The present application relates to the field of computer application technologies, and in particular, to a method for debugging a logic system design and an electronic device.
Background
Before the logic system design is put into actual operation, the compiled logic system design needs to be operated and debugged, and the logic system design is found to be abnormal in the debugging process. The method is characterized in that the discovered anomalies are required to be further diagnosed, the reasons and the specific source positions of the anomalies are found out, the corrections are carried out, and the robustness of the logic system design is ensured. In the process of designing and debugging a logic system, many functions, such as waveform debugging, coverage rate debugging, source code debugging and circuit schematic diagram debugging, are involved, and the debugging functions often run independently.
In the related art, a user needs to repeatedly check a schematic circuit diagram, a waveform diagram, a source code, a coverage rate, etc. of a logic system design in different ranges (for example, a signal, a circuit module, a code, etc.) during the process of debugging the logic system design. Therefore, the user needs to modify the selected range multiple times and continuously drag the user to the function window to view the signal, and may need to try many times to obtain the part of the signal which the user wants to debug, so that the debugging efficiency is limited.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method, an electronic device, and a readable storage medium for debugging a logic system design.
In a first aspect, the present application provides a method for debugging a logic system design. The method comprises the following steps: receiving an instruction to select a debug object in a graphical debug tool, the debug object comprising one or more design elements; determining a characterization of the one or more design elements; and generating a graphical window in the debugging tool according to the feature description, wherein the graphical window is used for displaying information of the one or more design elements in a drag operation.
In a second aspect, the application further provides electronic equipment. The electronic device includes a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of the first aspect.
In a third aspect, the present application also provides a non-transitory computer readable storage medium storing a set of instructions of a computer for, when executed, causing the computer to perform the method according to the first aspect.
The method for debugging the design of the logic system, the electronic equipment and the readable storage medium at least comprise the following beneficial effects:
according to the application, the information of one or more design elements of the selected debugging object in the dragging operation is displayed through the graphical interface, and the design elements included in the debugging object can be determined before the debugging object is dragged to the function window checking signal according to the information, so that a user can conveniently judge whether the currently selected debugging object comprises the design elements required to be debugged, the user can adjust the selected debugging object, unnecessary operations for dragging to the function window checking signal are reduced, the debugging efficiency is improved, and the time cost of the user is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 shows a schematic diagram of a host in accordance with an embodiment of the application;
FIG. 2 shows a schematic diagram of a debug tool according to an embodiment of the present application;
FIG. 3 shows a schematic diagram of a graphical interface of a debug tool according to an embodiment of the present application;
FIG. 4 illustrates a source code region schematic diagram of a debug tool in accordance with an embodiment of the present application;
FIG. 5 illustrates a schematic diagram of a method for debugging a logic system design in accordance with an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, it is not excluded that additional identical or equivalent elements may be present in a process, method, article, or apparatus that comprises a described element. For example, if first, second, etc. words are used to indicate a name, but not any particular order. The term "coupled" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
As described above, in the simulation debugging process, there are often cases where it is necessary to repeatedly check the schematic circuit diagram, the waveform diagram, the source code, the coverage rate, etc. of the logic system design in different ranges (for example, one signal, one circuit module, one code, etc.), however, in the simulation debugging process, the user needs to modify the selected range multiple times, continuously drag to the functional window to check the signal, and may need to try multiple times to obtain the portion of the signal that the user wants to debug, so that the debugging efficiency is limited. The method for debugging the logic system design provided by the embodiment of the application can be applied to simulation debugging occasions. By adopting the method provided by the embodiment of the application, the simulation debugging efficiency can be improved to a certain extent.
Specifically, the simulation test is to apply various stimuli to the logic system design on a host running the simulation test system to detect whether the logic system design can realize a predetermined function.
Fig. 1 shows a schematic diagram of a host 100 according to an embodiment of the application. The host 100 may be an electronic device running a simulation test system. As shown in fig. 1, the host 100 may include: processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110. Wherein the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively coupled to each other within the host via a bus 110.
The processor 102 may be a central processing unit (Central Processing Unit, CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits. The processor 102 may be used to perform functions related to the techniques described herein. In some embodiments, processor 102 may also include multiple processors integrated as a single logical component. As shown in fig. 1, the processor 102 may include a plurality of processors 103A, 103B, and 102c.
The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, the simulation test system used to simulate the test design may be a computer program stored in memory 104. As shown in fig. 1, the data stored by the memory may include program instructions (e.g., program instructions for implementing the method of the present application for debugging a logic system design) as well as data to be processed (e.g., the memory may store temporary code generated during compilation). The processor 102 may also access program instructions and data stored in the memory and execute the program instructions to perform operations on the data to be processed. The memory 104 may include volatile storage or nonvolatile storage. In some embodiments, memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSD), flash memory, memory sticks, and the like.
The network interface 106 may be configured to provide communication with other external devices to the host 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the above. It will be appreciated that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, receivers, modems, routers, gateways, adapters, cellular network chips, etc.
The peripheral interface 108 may be configured to connect the host 100 with one or more peripheral devices to enable information input and output. For example, the peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, various types of sensors, and output devices such as displays, speakers, vibrators, and indicators.
Bus 110 may be configured to transfer information between the various components of host 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as an internal bus (e.g., processor-memory bus), an external bus (USB port, PCI-E bus), etc.
It should be noted that, although the above-described host architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in a specific implementation, the host architecture may also include other components necessary to achieve proper operation. Furthermore, it will be understood by those skilled in the art that the above-described host architecture may include only components necessary for implementing the embodiments of the present application, and not all components shown in the drawings.
FIG. 2 shows a schematic diagram of a debug tool 200 and a simulation tool 202 in accordance with an embodiment of the present application. Debug tool 200 and emulation tool 202 may be computer programs running on host 100.
In the field of chip design, a design may be simulated, typically with simulation tools. The simulation tool may be, for example, a GalaxSim simulation tool available from Kagaku Co., ltd. The exemplary simulation tool 202 illustrated in FIG. 2 may include a compiler 120 and a simulator 220. Compiler 120 may compile a design (e.g., logic system design 210) into object code 204, simulator 220 may simulate based on object code 204, and output simulation results 206. Logic system design may include several design elements. For example, the simulation tool 202 may output simulation results (e.g., simulation waveform diagrams) onto an output device (e.g., displayed on a display) via the peripheral interface 108 of fig. 1.
Debug tool 200 may also read simulation results 206. The Debug tool 200 may be, for example, a Fusion Debug tool available from core chapter technologies, inc. For example, debug tool 200 may read simulation results 206 stored in a waveform file and generate corresponding simulated waveforms for debugging. Debug tool 200 may also read simulation results 206 stored in a circuit netlist file and generate a corresponding schematic for debugging. Debug tool 200 may also read a description of logic system design 210 (typically SystemVerilog and Verilog code) and display to the user. Debug tool 200 may also read the coverage of logic system design 210 in simulation results 206 and display to the user. Debug tool 200 may also generate graphical interfaces (e.g. various debug areas) to facilitate the user's debugging efforts. The debug areas may include waveform areas, schematic areas, source code areas, coverage areas, or the like. The user may view waveforms, schematic circuits, code, coverage, etc. through the corresponding debug areas of debug tool 200. The user may issue a debug command 208 to the debug tool 200 (e.g. run the logic system design 210 to a certain time, or view the simulation results in the debug area, etc.), which the debug tool 200 then applies to the simulation tool 202 to execute accordingly.
Through the mode, the application constructs the debugging environment for debugging the design of the logic system, and the design of the logic system is debugged through the debugging environment. The debug interface may include a plurality of debug areas, each debug area corresponding to a variety of functions, such as viewing waveforms, schematic diagrams, code, or coverage, as described above. In order to facilitate the debugging work of the user, the user can select a debugging object in one debugging area of the debugging interface and drag the object to another debugging area, and the debugging tool displays a waveform diagram, a schematic circuit diagram, codes, coverage rate and the like corresponding to the debugging object in the other debugging area according to the drag operation. In actual operation, a debug object selected in one debug area is not necessarily capable of activating a corresponding debug function in another debug area. For example, when a selected signal does not have any coverage statistics, the coverage of the signal cannot be viewed even if the signal is dragged to a coverage window. However, it is difficult for the user to know this information when selecting a debug object. Meanwhile, because the debugging objects selected by the user and the debugging parts required to be selected by the user often have the conditions of wrong selection range or overlarge or undersize selection range, the user needs to modify the selection range for many times and continuously drag the function window to view signals, and the part of signals which the user wants to debug can be obtained by trying for many times, so that the debugging efficiency is limited, and the time cost of the user is greatly increased.
Based on this, the application further proposes a method, an electronic device and a storage medium for debugging a logical system design. According to the method provided by the application, in the debugging process, the information of one or more design elements of the selected debugging object in the dragging operation can be displayed through the graphical interface, the design elements included in the debugging object can be determined according to the information before the debugging object is dragged to the function window checking signal, so that a user can conveniently judge whether the currently selected debugging object comprises the design elements required to be debugged, the user can adjust the selected debugging object, unnecessary operations for dragging to the function window checking signal are reduced, the debugging efficiency is improved, and the time cost of the user is reduced.
Next, the application will be explained further on how to design this debugging tool and how to debug the region display for this debugging tool.
FIG. 3 illustrates a schematic diagram of a graphical interface 300 of a debug tool 200 in accordance with an embodiment of the present application. Graphical interface 300 may be displayed on an output device of host 100 (e.g., on a display). In some embodiments, graphical interface 300 of debug tool 200 includes a plurality of debug areas corresponding to a plurality of debug functions. For example, the graphical interface 300 includes a waveform area 310, a schematic circuit area 320, a source code area 330, a coverage area 340, and the like, corresponding to a waveform display function, a schematic circuit display function, a source code display function, a coverage information display function, and the like, respectively. The graphical interface 300 may further include a logic system design framework area 302, where the logic system design framework area 302 may display a code framework (typically in a tree structure) of the logic system design, for displaying a top-bottom hierarchical relationship between each module of the logic system design, which may further facilitate a user to quickly locate a portion that needs to be debugged.
Waveform area 310 may be used to display a waveform map of the selected signal over a given time interval. For example, as shown in FIG. 3, waveform region 310 shows waveforms for signals a and b between 811000ns and 812000 ns.
The schematic circuit diagram area 320 may be used to display a schematic circuit diagram of a selected module. For example, as shown in FIG. 3, schematic circuit area 320 shows a schematic circuit diagram of the module associated with signals a and b.
Source code region 330 may be used to display source code for a logical system design. In some embodiments, source code region 330 may display the source code of the selected module.
Coverage area 340 may be used to display coverage information for the selected signal. For example, as shown in FIG. 3, coverage area 340 shows 40% coverage for signal a and 90% coverage for signal b.
It will be appreciated that the graphical interface 300 may include more or less display area.
The waveform area 310, schematic area 320, source code area 330, and coverage area 340 described above may be displayed in separate or embedded window forms.
The user may select a debug object in any one of a plurality of display areas (e.g. waveform area 310, schematic circuit area 320, source code area 330, and coverage area 340) of graphical interface 300, such as by way of a mouse, touch screen, or the like. The debug object may comprise one or more design elements in the logic system design, which may comprise a piece of source code, a signal waveform (e.g., the waveform of signal a), a signal (e.g., signal a), a port, or a module of the logic system design. Debug tool 200 may determine a characterization of one or more design elements in the debug object. The feature description may include source code associated with one or more design elements (e.g., a module). That is, the feature description may include code (e.g., object code 204 or source code) in the logical system design that corresponds to the design element.
The debugging tool 200 may generate a graphical window on the graphical interface 300 according to the feature description of the debugging object, and display information of the design elements in the debugging object in the drag operation in the graphical window.
FIG. 4 illustrates a schematic diagram of a drag operation of debug tool 200 in accordance with an embodiment of the present application.
A schematic diagram of a drag operation performed in the source code region 330 is shown in fig. 4. More specifically, FIG. 4 illustrates a corresponding graphical window 334 generated by debug tool 200 when debug object 322 is selected during a drag operation.
The drag operation may refer to a type of debug validation operation that a user has on graphical interface 300 through debug tool 200. The debugging tool 200 may recognize a drag operation and accordingly display corresponding information, e.g., waveform diagrams, schematic circuit diagrams, codes, coverage, etc., in a debugging region having different functions according to the drag operation.
In FIG. 4, the user-selected debug object 322 is a piece of source code. For example, the code in the black shadow area of the 327 th line-330 th line is the selected debug object, and the selected state can be displayed by using the color block background with other colors. Debug object 322 includes a number of design elements, such as a module named u_e203_soc_top, functions hfextclk (hfclk) and hfxoscnt () included in the module, and a signal hfclk.
Debug tool 200 may determine the characterization of the design elements described above from the source code of the logic system design to determine the information displayed in graphical window 334. The information displayed in graphical window 334 may include the name, attributes, etc. of the design elements.
For example, debug tool 200 may determine that module u_e203_soc_top may be displayed in schematic diagram area 320, and thus may determine that module u_e203_soc_top has schematic diagram properties; the signal hfclk may be displayed in the waveform area 310 (e.g., have a waveform file corresponding to hfclk), and thus it may be determined that the signal hfclk has waveform properties. However, the debug tool 200 may similarly determine that there is no coverage information corresponding to the signal hfclk, and therefore, the signal hfclk does not have a coverage attribute.
Accordingly, the information displayed in the graphical window 334 may include the names of the modules u_e203_soc_top and the signals hfclk and their corresponding attributes. The attributes may be displayed in the form of icons, such as the schematic circuit diagram icon and the waveform icon in fig. 4. The box below the debug object in fig. 4 is a graphic window, and the graphic window may also take other shapes, such as a circular frame, a cloud-shaped frame, and the like.
In some embodiments, debug tool 200 may determine the characterization of the design elements described above from keywords in debug object 322. The debug tool 200 may extract keywords of the debug object, for example, with "u_e203_soc_top" and "hfclk" as keywords, and extract feature descriptions (e.g., source code) corresponding to or related to "u_e203_soc_top" and "hfclk" in the description of the logical system design, thereby determining feature descriptions of design elements in the debug object. The debug tool 200 then parses the feature descriptions of "u_e203_soc_top" and "hfclk" to determine that a design element included in the currently selected debug object is "u_e203_soc_top", representing a module; another design element is "hfclk" representing a signal.
In some embodiments, the drag operation may include: clicking on icons in graphical window 334, such as the schematic circuit diagram icon and the waveform icon in fig. 4. In this case, the debug tool 200 may send the debug object 322 to the debug area corresponding to the clicked icon according to the clicked icon, thereby calling the debug function. For example, when the user clicks a signal icon corresponding to hfclk, the debug tool 200 transmits the debug object 322 selected by the user to the waveform region 310 corresponding to the signal icon, and displays the waveform of the signal hfclk in the waveform region 310. It will be appreciated that for debug tool 200, sending debug object 322 to the debug area corresponding to the clicked icon may be just a graphical presentation process, and in fact, debug tool 200 may call the debug function corresponding to the icon directly without further determination of its debug area. In other embodiments, the drag operation may include: drag debug object 322 from the current debug area (e.g. source code area 330) to the other debug areas (e.g. schematic circuit area 320 or waveform area 310) and release the debug object. In this case, the debug tool 200 calls a debug function corresponding to a debug region of the release debug object 322 according to the debug object 322.
In some embodiments, debug object 322 is in source code region 330, and in response to a drag operation, in the case where schematic circuit diagram region 320 invokes a schematic circuit diagram display function according to debug object 322, in particular, debug tool 200 may obtain a circuit netlist corresponding to design elements included in debug object 322 from a circuit netlist database, where the circuit netlist generally refers to a netlist describing a connection relationship of circuit elements to each other. Debug tool 200 may read the circuit netlist file in simulation result 206 from the circuit netlist database and further obtain a circuit netlist corresponding to the design elements included in debug object 322 based on the names of the design elements included in debug object 322. Debug tool 200 loads the obtained circuit netlist in circuit schematic region 320 and displays a circuit schematic corresponding to the circuit netlist in circuit schematic region 320 based on the circuit netlist.
According to the application, the information of one or more design elements of the selected debugging object in the dragging operation is displayed through the graphical interface, and the design elements included in the debugging object can be determined before the debugging object is dragged to the function window checking signal according to the information, so that a user can conveniently judge whether the currently selected debugging object comprises the design elements required to be debugged, the user can adjust the selected debugging object, unnecessary operations for dragging to the function window checking signal are reduced, the debugging efficiency is improved, and the time cost of the user is reduced. Meanwhile, by analyzing the debug attribute (e.g. the circuit diagram of u_e203_soc_top and the waveform of hfclk) corresponding to the debug object selected by the user, the user can know in advance which debug functions the debug object can call. The embodiment of the application also allows the user to click on the icon in the graphic window 334, thereby facilitating the user to quickly call the debugging function.
A method for debugging a logic system design is also provided in some embodiments of the application.
FIG. 5 illustrates a schematic diagram of a method 500 for debugging a logic system design, in accordance with an embodiment of the present application. Method 500 may be performed by host 100 of fig. 1, and more specifically, by graphical debug tool 200 of fig. 2 running on host 100. The method 500 may include the following steps.
At step 510, host 100 may receive an instruction to select a debug object in graphical debug tool 200. The instruction may be an operation in which the user selects the debug object using the mouse. Debug objects may refer, for example, to portions of graphical interface 300 of debug tool 200 that are in a selected state (e.g. debug object 322 in fig. 4). The debug object may include one or more design elements. In some embodiments, the one or more design elements may include a piece of source code, a signal waveform (e.g., the waveform of signal a in fig. 3), a signal (e.g., signal a in fig. 3), a port, or a module of the logic system design. In some embodiments, debug tool 200 includes a plurality of debug areas corresponding to a plurality of debug functions including at least one of source code display, waveform display, schematic circuit display, or coverage statistics, for example, a debug area may include waveform area 310, schematic circuit area 320, source code area 330, and coverage area 340 as in fig. 3 corresponding to the plurality of debug functions described above. It is to be appreciated that the host 100 can process the description of the logical system design as target code (e.g., target code 204 in FIG. 2, target code 204 can include binary code or RTL code, etc.), and further process the target code of the logical system design.
Based on the selected debug object, host 100 may determine a characterization of one or more design elements included by the debug object at step 520. Wherein the feature description may include source code associated with one or more design elements, i.e., the feature description may include code (e.g., object code 204 or source code) corresponding to the design elements in the logical system design. In some embodiments, determining a characterization of the one or more design elements further comprises: host 100 may extract keywords of the debug object (e.g. "u_e203_soc_top" and "hfclk" of debug object 322 in fig. 4 as keywords); and extracting feature descriptions of one or more design elements corresponding to the keywords from the descriptions of the logic system design based on the keywords. The key of the debug object may refer to a key used to characterize a design element of the debug object, for example, where the design element includes a source code, the key may be a code description of a function or a module extracted after the initialization block statement is filtered out. According to the embodiment, the feature description of the design elements in the debugging object can be determined by extracting the keywords of the debugging object and extracting the feature description corresponding to the keywords according to the description of the keywords in the logic system design.
At step 530, based on the characterization, host 100 may generate a graphical window (e.g., 334 in FIG. 4) in debug tool 200 for displaying information of the one or more design elements in the drag operation. In some embodiments, the plurality of debug areas includes a first debug area and a second debug area, and the drag operation is used to transfer the selected debug object from the first debug area to the second debug area. For example, the first debug area and the second debug area may each be any of the waveform area 310, schematic circuit area 320, source code area 330, and coverage area 340 in fig. 3. According to the embodiment, the drag operation of the debugging object from the first debugging area and the second debugging area can be realized, the corresponding debugging function is displayed in the second debugging area, the debugging requirements in different occasions are met, the user can conveniently debug in different debugging areas, and the debugging efficiency is improved.
In some embodiments, a graphical window may be used to display names of one or more design elements and debug functions corresponding to the one or more design elements. In the embodiment, the names of the design elements are displayed in the graphic window, and the debugging functions corresponding to the design elements are also displayed, so that the user is conveniently instructed to which debugging area or areas the currently selected debugging object supports to be dragged to, and the debugging efficiency is further improved. In some embodiments, generating the graphical window in the debug tool according to the feature description further comprises: the host 100 may determine the name of the target design element of the one or more design elements from the characterization; the host 100 may determine candidate debug functions corresponding to the target design elements according to the target design elements, where the debug functions corresponding to the target design elements include debug functions that the target design elements can call, that is, the target design elements have properties corresponding to the debug functions, for example, a module u_e203_soc_top in fig. 4 has a schematic diagram property, and a signal hfclk has a waveform property; and displaying the names of the target design elements and attribute icons (e.g., schematic circuit diagram icons and waveform icons in fig. 4) of the candidate debug functions in the graphical window, wherein the attribute icons are in one-to-one correspondence with the candidate debug functions. According to the method and the device for displaying the target design element names and the attribute icons of the corresponding candidate debugging functions in the image window, the user can be clearly indicated to which debugging area or areas the currently selected debugging object supports to be dragged, and the debugging efficiency is further improved.
In some embodiments, the plurality of debug functions includes a first debug function corresponding to the first debug area and a second debug function corresponding to the second debug area. The method 500 may further include the steps of: the host 100 may receive a drag operation; and in response to receiving the drag operation, invoking a second debug feature for the target design element in a second debug area. In some embodiments, the drag operation includes: clicking an attribute icon of the candidate debugging function; or drag the debug object and release the debug object in the second debug area. For example, clicking on the schematic diagram icon or waveform icon in the graphical window 334 of FIG. 4; or drag debug object 322 to schematic area 320 or waveform area 310. The drag operation of the embodiment may include clicking the attribute icon or dragging the debug object and releasing the test object in the second debug area, which not only can support the user to call the corresponding debug function by dragging the debug object to the second debug area, but also can support the user to directly click the attribute icon of the candidate debug function in the graphic window, and the debug tool calls and displays in the second debug area according to the debug function corresponding to the clicked attribute icon, so that the user can conveniently and accurately call according to different debug functions, and the debug efficiency is improved.
In some embodiments, the first debug area is a source code area and the second debug area is a schematic circuit diagram area, and invoking the second debug function at the second debug area for the target design element further comprises: the host 100 may obtain a circuit netlist corresponding to the target design element from a circuit netlist database, load the circuit netlist, and display a schematic circuit diagram corresponding to the circuit netlist in a second debug area. In the embodiment, the debugging tool reads the circuit netlist file in the simulation result through the circuit netlist database, and rapidly acquires the circuit netlist corresponding to the target design element according to the name of the acquired target design element, so that the efficiency of loading the circuit netlist in a circuit schematic region and displaying a circuit schematic is improved, and the generated circuit schematic can be accurately matched with the selected debugging object, and the condition of loading redundancy is avoided.
According to the application, the information of one or more design elements of the selected debugging object in the drag operation can be displayed through the graphical interface, and the design elements included in the debugging object can be determined before the debugging object is dragged to the function window check signal according to the information, so that a user can conveniently judge whether the currently selected debugging object comprises the design elements required to be debugged, the user can adjust the selected debugging object, unnecessary operations of dragging to the function window check signal are reduced, the debugging efficiency is improved, and the time cost of the user is reduced.
It should be noted that the method of the present application may be performed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the method of the present application, the devices interacting with each other to complete the method.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
The embodiment of the application also provides electronic equipment, which comprises a memory, a first memory and a second memory, wherein the memory is used for storing a group of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method 500 provided by the embodiments of the present application.
Embodiments of the present application also provide a non-transitory computer readable storage medium storing a set of instructions for a computer, which when executed, are configured to cause the computer to perform the method 400 provided by the embodiments of the present application. Any reference to memory, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (Phase Change Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like. The databases referred to in the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processor referred to in the embodiments provided in the present application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, or the like, but is not limited thereto.
The foregoing describes some embodiments of the present application. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order, and there are many other variations of the different aspects of the application as described above, which are not provided in detail for the sake of brevity.
While the application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
The present application is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the present application should be included in the scope of the present application.
Claims (10)
1. A method for debugging a logic system design, the method comprising:
receiving an instruction to select a debug object in a graphical debug tool, the debug object comprising one or more design elements;
determining a characterization of the one or more design elements; and
generating a graphic window in the debugging tool according to the feature description, wherein the graphic window is used for displaying information of the one or more design elements in a drag operation, and the information of the one or more design elements comprises names and attributes of the one or more design elements;
wherein the debug tool includes a plurality of debug areas corresponding to a plurality of debug functions, the plurality of debug areas including a first debug area and a second debug area, the drag operation being for transferring the selected debug object from the first debug area to the second debug area; the graphical window is used for displaying names of the one or more design elements and debugging functions corresponding to the one or more design elements, and the attribute corresponds to the debugging functions.
2. The method of claim 1, wherein the plurality of debug functions includes at least one of a source code display, a waveform display, a schematic representation display, or coverage statistics.
3. The method of claim 2, wherein the one or more design elements comprise a piece of source code, a signal waveform, a signal, a port, or a module of the logic system design.
4. The method of claim 3, wherein the characterization includes source code associated with the one or more design elements, and wherein determining the characterization of the one or more design elements further comprises:
extracting keywords of the debug object; and
and extracting feature descriptions of one or more design elements corresponding to the keywords from the descriptions of the logic system design based on the keywords.
5. The method of claim 3, wherein the step of,
the generating a graphical window in the debug tool according to the feature description further comprises:
determining a name of a target design element of the one or more design elements according to the feature description;
determining candidate debugging functions corresponding to the target design elements according to the target design elements, wherein the debugging functions corresponding to the target design elements comprise debugging functions which can be called by the target design elements; and
and displaying the names of the target design elements and the attribute icons of the candidate debugging functions in the graphic window.
6. The method of claim 5, wherein the plurality of debug functions includes a first debug function corresponding to the first debug area and a second debug function corresponding to the second debug area, the method further comprising:
receiving the drag operation; and
and in response to receiving the drag operation, invoking the second debugging function for the target design element in the second debugging region.
7. The method of claim 6, wherein the drag operation comprises:
clicking the attribute icon of the candidate debugging function; or (b)
Dragging the debug object and releasing the debug object in the second debug area.
8. The method of claim 6, wherein the first debug area is a source code area and the second debug area is a schematic circuit area, wherein invoking the second debug function at the second debug area for the target design element further comprises:
obtaining a circuit netlist corresponding to the target design element from a circuit netlist database;
loading the circuit netlist; and
and displaying a circuit schematic diagram corresponding to the circuit netlist in the second debugging area.
9. An electronic device, comprising
A memory for storing a set of instructions; and
at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of any one of claims 1 to 8.
10. A non-transitory computer readable storage medium storing a set of instructions for a computer, which when executed, cause the computer to perform the method of any of claims 1 to 8.
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