CN113535494B - Equipment debugging method and electronic equipment - Google Patents

Equipment debugging method and electronic equipment Download PDF

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Publication number
CN113535494B
CN113535494B CN202110859747.2A CN202110859747A CN113535494B CN 113535494 B CN113535494 B CN 113535494B CN 202110859747 A CN202110859747 A CN 202110859747A CN 113535494 B CN113535494 B CN 113535494B
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cpu
serial port
main cpu
target sub
sub
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CN113535494A (en
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杨淦宇
陈宁
秦德楼
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Hangzhou DPTech Technologies Co Ltd
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Hangzhou DPTech Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G06F11/2242—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors in multi-processor systems, e.g. one processor becoming the test master
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2733—Test interface between tester and unit under test

Abstract

The specification provides a device debugging method and electronic device. The method is applied to the electronic equipment provided with the main CPU, the sub-CPU and the coprocessor, and is provided with a first serial port and a second serial port which are used for external debugging, wherein the first serial port is connected with the main CPU, the second serial port is connected with the coprocessor, and the coprocessor is connected with each sub-CPU and the main CPU; a main CPU of the electronic device informs a coprocessor to associate a second serial port with a target sub-CPU when receiving a debug command for the target sub-CPU input through the first serial port; and the coprocessor of the electronic equipment outputs debugging information of the target sub-CPU through the second serial port after receiving the notification that the main CPU associates the second serial port with the target sub-CPU. The two serial ports are separately arranged to respectively realize the functions of command receiving and information outputting, so that the problems that the related technology cannot receive commands after switching the serial ports to the fault sub-CPU, and the complete machine must be restarted because the serial ports cannot be continuously debugged are avoided, and the equipment debugging efficiency is improved.

Description

Equipment debugging method and electronic equipment
Technical Field
One or more embodiments of the present disclosure relate to the field of computer technology, and in particular, to a method for device debugging and an electronic device.
Background
As technology advances and demand increases, more and more devices employ a distributed management architecture in which subsystems, such as fan modules, and assembled card boards, in addition to a main CPU, are each configured with a sub-CPU. When debugging the device with the distributed management architecture, how to obtain the debugging information of the main CPU and the sub-CPU in the device becomes a problem to be solved.
In the related art, a serial port for external debugging is generally configured on the device, the serial port is connected with a coprocessor, and the coprocessor is connected with the debugging interfaces of all CPUs. And the debugging personnel issues a switching command to the coprocessor through the serial port, so that the coprocessor outputs the debugging information of any CPU in the plurality of CPUs of the device through the serial port switching. For example, when a switching command for any target CPU is input to the coprocessor through the serial port, the debug information of the target CPU can be output to the outside through the serial port under the condition that the target CPU has no fault; under the condition that the target CPU fails, debugging information cannot be output through the serial port, a switching command input by a debugging person cannot be received any more, and if the debugging information of other CPUs needs to be continuously output, the debugging process needs to be continuously carried out in a whole machine restarting mode. Therefore, the work of debugging personnel is greatly disturbed, and the equipment debugging efficiency is reduced.
Disclosure of Invention
In view of this, the present disclosure provides a method for debugging a device and an electronic device.
In order to achieve the above object, one or more embodiments of the present disclosure provide the following technical solutions:
according to a first aspect of one or more embodiments of the present disclosure, a method for device debugging is provided, which is applied to an electronic device configured with a main CPU, a sub-CPU, and a coprocessor, where the electronic device is configured with a first serial port and a second serial port for external debugging, the first serial port is connected to the main CPU, the second serial port is connected to the coprocessor, the coprocessor is connected to each sub-CPU, and the coprocessor is further connected to the main CPU;
the method comprises the following steps:
the main CPU of the electronic equipment informs the coprocessor to associate a second serial port with a target sub-CPU when receiving a debugging command input through the first serial port and aiming at the target sub-CPU;
and after receiving a notification that the main CPU associates the second serial port with the target sub-CPU, the coprocessor of the electronic equipment outputs debugging information of the target sub-CPU to the outside through the second serial port.
According to a second aspect of one or more embodiments of the present specification, an electronic device is provided, which is configured with a main CPU, sub-CPUs, and a coprocessor, and is configured with a first serial port and a second serial port for external debugging, where the first serial port is connected to the main CPU, the second serial port is connected to the coprocessor, the coprocessor is connected to each sub-CPU, and the coprocessor is further connected to the main CPU;
the main CPU of the electronic equipment is used for informing the coprocessor to associate the second serial port with the target sub-CPU when receiving a debugging command which is input through the first serial port and aims at the target sub-CPU;
and the coprocessor of the electronic device is used for outputting the debugging information of the target sub-CPU to the outside through the second serial port after receiving the notification that the main CPU associates the second serial port with the target sub-CPU.
As can be seen from the above description, in the present specification, two serial ports for external debugging are configured on an electronic device, after a debug command for a target sub-CPU is input to a main CPU through a first serial port, the main CPU will notify a coprocessor to associate a second serial port with the target sub-CPU, and then debug information of the target sub-CPU will be output externally through the second serial port by the coprocessor. Because the first serial port for receiving the debug command and the second serial port for outputting the debug information of each sub-CPU are two different serial ports which are mutually independent, as long as the main CPU keeps a normal state, even if the coprocessor is switched to a faulty sub-CPU for a certain time, the main CPU does not influence the new debug command to inform the coprocessor to switch and output the debug information of other non-faulty sub-CPUs after being input through the first serial port, and the whole machine restarting is not required because the debug command cannot be input after the main CPU is switched to the faulty sub-CPU, thereby avoiding the technical defects in the related art, smoothly completing the debugging of each sub-CPU, improving the equipment debugging efficiency and reducing the burden of debugging personnel.
Drawings
Fig. 1 is a schematic diagram of an architecture of an electronic device to be debugged in the related art, which is shown in an exemplary embodiment.
Fig. 2 is a schematic diagram of an architecture of an electronic device to be debugged in the present solution according to an exemplary embodiment.
FIG. 3 is a flowchart of a method for device commissioning in accordance with an example embodiment.
FIG. 4 is a flow chart illustrating a method of device commissioning in accordance with another example embodiment.
Fig. 5 is a schematic structural diagram of an electronic device according to an exemplary embodiment.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with one or more embodiments of the present specification. Rather, they are merely examples of apparatus and methods consistent with aspects of one or more embodiments of the present description as detailed in the accompanying claims.
It should be noted that: in other embodiments, the steps of the corresponding method are not necessarily performed in the order shown and described in this specification. In some other embodiments, the method may include more or fewer steps than described in this specification. Furthermore, individual steps described in this specification, in other embodiments, may be described as being split into multiple steps; while various steps described in this specification may be combined into a single step in other embodiments.
With the rapid development of the technical fields of large-scale integrated circuits and the like and the continuous improvement of network scale and equipment performance requirements of the masses, more and more electronic equipment starts to adopt a distributed management architecture. Under the distributed management architecture, the electronic device can be divided into a plurality of subsystems and/or a sub-board, each subsystem and the sub-board are configured with independent sub-CPUs, and the whole electronic device coordinates the plurality of sub-CPUs to jointly execute device tasks under the control of a main CPU. For example, one type of electronic device that uses the distributed architecture is a frame switch, in which a main CPU is a main control board CPU, and a sub-CPU is a subsystem such as a fan module and/or a CPU of a sub-board such as an interface board.
The above-mentioned distributed management architecture can improve the execution efficiency of the device task, but is complicated when the device is debugged. In the related art, as shown in fig. 1, an external debug serial port 0 is generally configured on a device, the serial port 0 is connected with a coprocessor such as an FPGA (Field Programmable Gate Array ) and a CPLD (Complex Programmable Logic Device, complex programmable logic device) in the device, a debugger communicates a switch command to the coprocessor through the serial port 0, and notifies the coprocessor to associate the external debug serial port 0 with a target CPU indicated in the switch command, so as to output debug information of the target CPU through the serial port 0, but once a certain switch command indicates to switch to a faulty CPU, the serial port 0 cannot output debug information of the faulty CPU and cannot receive a switch command input from outside, and the whole machine must be restarted in order to continue the debug work of other CPUs, so that the configuration mode of combining two functions of command receiving and information output with one port greatly interferes with the work of the debugger, and reduces the efficiency of device debugging.
In view of this, the present disclosure proposes a method for debugging an apparatus, which is applied to any electronic apparatus configured with a main CPU, sub-CPUs, and coprocessors, where the electronic apparatus is configured with a first serial port and a second serial port for external debugging, the first serial port is connected to the main CPU, the second serial port is connected to the coprocessors, the coprocessors are connected to the respective sub-CPUs, and the coprocessors are further connected to the main CPU.
Specifically, it is assumed that, as shown in fig. 2, the electronic device includes a main CPU 0, a sub CPU 1 and a sub CPU 2, where a debug interface UART 0 of the main CPU 0 is connected to the serial port 1, a debug interface UART 1 of the sub CPU 1 and a debug interface UART 2 of the sub CPU 2 are connected to a coprocessor CPLD, the CPLD is connected to the serial port 2, and the CPLD is further connected to the main CPU 0 through a device bus. The debugging interfaces UART 1 and UART 2 are UART interfaces (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter) and generally adopt TTL (Transistor-Transistor Logic level) standards; and the serial ports 1 and 2 are COM ports (Cluster Communication Port, serial communication ports) and generally adopt RS-232 (asynchronous transmission standard interface) standards.
It should be noted that, in this specification, as to what kind of electronic device is the electronic device, what kind of coprocessor is the coprocessor, what kind of subsystem and/or CPU of the sub-board is the sub-CPU, and what kind of number of sub-CPUs are the sub-CPU, and the electronic device, the coprocessor, the subsystem and/or the sub-board and the number thereof are referred to in the following embodiments are merely illustrative.
Referring to fig. 3, fig. 3 is a flowchart of a method for debugging a device provided in the present specification, where the method may include the following specific steps:
step 302, a main CPU of an electronic device to be debugged, when receiving a debug command for a target sub-CPU input through a first serial port, notifies a coprocessor to associate a second serial port with the target sub-CPU.
When a debugger inputs a debug command for a target sub-CPU 1 to a main CPU 0 through a serial port 1 at the time of debugging an electronic device shown in fig. 2, the main CPU 0 notifies a CPLD to associate the serial port 2 with the target sub-CPU 1 in response to the debug command.
The debugging personnel inputs a debugging command through a first serial port, in an example, the debugging personnel connects the first serial port with debugging equipment, and inputs the debugging command to a main CPU of the electronic equipment to be debugged through the first serial port by utilizing the debugging equipment; in another example, the debugger may call the first serial port to input a debug command to the main CPU through debug software running on the electronic device to be debugged.
The debug command for the target sub-CPU can carry the identification of the target sub-CPU, and the main CPU distinguishes the target sub-CPU and the non-target sub-CPU based on the sub-CPU identification in the debug command.
The main CPU informs the coprocessor to associate the second serial port with the target sub-CPU, and there are a plurality of alternative implementations, which are not particularly limited in this specification. Specifically, the main CPU may issue an instruction to the coprocessor, where the instruction indicates an association relationship between the second serial port and the target sub-CPU, so as to notify the coprocessor to associate the second serial port with the target sub-CPU; or, the instruction may only instruct the target sub-CPU to notify the coprocessor to associate the second serial port of the preset output sub-CPU debug information with the target sub-CPU.
Step 304, after receiving the notification that the main CPU associates the second serial port with the target sub-CPU, the coprocessor of the electronic device outputs the debug information of the target sub-CPU to the outside through the second serial port.
When the main CPU 0 transmits a notification that the serial port 2 is associated with the target sub-CPU 1 to the CPLD when the electronic device shown in fig. 2 is debugged, the CPLD associates the debug interface UART 1 of the target sub-CPU 1 with the serial port 2 in response to the notification, so that the debug information of the target sub-CPU 1 is output to the outside through the serial port 2.
Under the condition that the target sub-CPU 1 has no fault, the CPLD successfully outputs the debugging information of the target sub-CPU 1 to the outside through the serial port 2, a debugger can acquire the debugging information of the sub-CPU 1 through the serial port 2 and continuously inputs the debugging commands aiming at other target sub-CPUs to the main CPU through the serial port 1, so that the CPLD outputs the debugging information of other sub-CPUs to the outside through the serial port 2.
And under the condition that the target sub-CPU 1 has a fault, the CPLD fails to output the debug information of the target sub-CPU 1 to the outside through the serial port 2, and a debugger can continue to input debug commands for other target sub-CPUs to the main CPU through the serial port 1 although the debugger cannot acquire the debug information of the sub-CPU 1 through the serial port 2, so that the CPLD outputs the debug information of other sub-CPUs to the outside through the serial port 2.
Therefore, no matter whether the sub-CPU 1 fails, when the debugger inputs the debug command for the target sub-CPU 2 to the main CPU 0 again through the serial port 1, and after the main CPU 0 informs the CPLD to associate the serial port 2 with the target sub-CPU 2, the CPLD can still normally output the debug information of the target sub-CPU 2 to the outside through the serial port 2 under the condition that the target sub-CPU 2 has no failure.
The debug information of the target sub-CPU is output to the outside through the second serial port, which may be output to the external debug device through the second serial port, or the debug information of the target sub-CPU is returned to the debug software running on the electronic device through the second serial port, optionally, the debug information may be displayed to the debugger in a visual interface manner.
As can be seen from the above description, in the present specification, two serial ports for external debugging are configured on an electronic device, after a debug command for a target sub-CPU is input to a main CPU through a first serial port, the main CPU will notify a coprocessor to associate a second serial port with the target sub-CPU, and then debug information of the target sub-CPU will be output externally through the second serial port by the coprocessor. Because the first serial port for receiving the debug command and the second serial port for outputting the debug information of each sub-CPU are two different serial ports which are mutually independent, as long as the main CPU keeps a normal state, even if the coprocessor is switched to a faulty sub-CPU for a certain time, the main CPU does not influence the new debug command to inform the coprocessor to switch and output the debug information of other non-faulty sub-CPUs after being input through the first serial port, and the whole machine restarting is not needed because the debug command cannot be input after the main CPU is switched to the faulty sub-CPU, thus the functions of command receiving and information outputting are respectively realized by separately arranging the two serial ports, the technical defects in the related technology are avoided, the debugging of each sub-CPU can be successfully completed, the equipment debugging efficiency is improved, and the burden of debugging personnel is reduced.
In an alternative implementation manner, a control register used for indicating a sub-CPU associated with the second serial port is configured in the electronic device to be debugged, the control register may be a control register in the coprocessor, the main CPU and the coprocessor are preset with mapping relations between the sub-CPU and the control register identifier, and notification interaction between the main CPU and the coprocessor may be implemented based on the mapping relations between the sub-CPU and the control register identifier in the device debugging method shown in fig. 3.
Referring to fig. 4, in this implementation, fig. 4 is a flowchart of a method for device debugging provided in the present specification, where the method may include the following specific steps:
step 402, when receiving a debug command for a target sub-CPU input through a first serial port, a main CPU of an electronic device to be debugged determines a control register identifier corresponding to the target sub-CPU based on a mapping relationship between the sub-CPU and the control register identifier, and modifies a control register identifier currently recorded in a control register in a coprocessor to the control register identifier corresponding to the target sub-CPU.
When debugging the electronic device shown in fig. 2, when a debugger inputs a debug command for a target sub-CPU 1 to a main CPU 0 through a serial port 1, the main CPU 0 searches a preset mapping relationship between the sub-CPU and a control register identifier to determine the control register identifier 1 corresponding to the target sub-CPU 1, and issues a modification command for the control register to the CPLD through a device bus between the main CPU 0 and the CPLD, so that the control register identifier currently recorded by the CPLD control register is modified into the control register identifier 1.
And step 404, after detecting that the control register identifier is modified, determining a target sub-CPU corresponding to the modified control register identifier based on the mapping relation, and outputting the debug information of the target sub-CPU to the outside through the second serial port by the coprocessor of the electronic device.
When the electronic device shown in fig. 2 is debugged, after detecting that the internal identifier of the control register is modified to be the control register identifier 1, the CPLD searches a mapping relationship between a preset sub-CPU and the control register identifier to determine a target sub-CPU 1 corresponding to the controller register identifier 1, and connects a debug interface UART 1 of the target sub-CPU 1 with a serial port 2 preset to output debug information, so that the debug information of the target sub-CPU 1 is output to the outside through the serial port 2.
On the other hand, considering that in the related art, the debug information of the main CPU and the sub CPU is output through the unique serial port, only the debug information of one CPU can be output at a time, and the requirement that the debug information of the main CPU and the sub CPU is always required to be checked at the same time when the electronic device under the distributed management architecture is debugged can not be met, the device debugging method provided in the present specification may further include:
and when receiving a debugging command for the main CPU input through a first serial port, the main CPU of the electronic equipment outputs debugging information of the main CPU to the outside through the first serial port.
In the method, the debugging information of the main CPU is output through the first serial port, and the debugging information of the sub-CPU is output through the second serial port, so that the requirement of checking the debugging information of the main CPU and the sub-CPU simultaneously when the electronic equipment under the distributed management architecture is debugged is met.
Further, in order to make the device debugging more efficient and accurate, the method for device debugging provided in the present specification may further include:
and when receiving a state checking command for one or more target sub-CPUs input through a first serial port, the main CPU of the electronic equipment outputs the states of the one or more target sub-CPUs to the outside through the first serial port.
The states of the sub-CPUs comprise normal state, initialization state, unpowered state, failure state and the like, the main CPU can acquire the states of the sub-CPUs and output the states to the outside for a debugger to check, and the number of the sub-CPUs which acquire and output the debugging information to the outside specifically can be controlled by a state checking command of the debugger. It is understood that the main CPU may output more information than the status of each sub-CPU, including but not limited to voltage, temperature, etc. data, to the outside.
In one example, if a target sub-CPU to which a debug command is input at a time has a fault, a debugger may input a state check command for the target sub-CPU to a main CPU through a first serial port, and in response to the state check command, the main CPU outputs the state of the target sub-CPU to the outside through the first serial port.
In another example, after the debug personnel finishes the debug of all the sub-CPUs, a state check command for all the sub-CPUs is input to the main CPU through the first serial port, and in response to the state check command, the main CPU outputs the states of all the sub-CPUs to the outside through the first serial port.
In the method, the state information of one or more sub-CPUs can be acquired at any time based on the requirements of debugging personnel, so that the debugging personnel can be helped to further locate the problems of equipment faults and the like, and the equipment debugging is more efficient and accurate.
Fig. 5 is a schematic structural diagram of an electronic device according to an exemplary embodiment. Referring to fig. 5, at the hardware level, the device includes a processor 502, an internal bus 504, a network interface 506, a memory 508, and a nonvolatile memory 510, although other hardware may be included as needed for other services. One or more embodiments of the present description may be implemented in a software-based manner, such as by the processor 502 reading a corresponding computer program from the non-volatile storage 510 into the memory 508 and then running. Of course, in addition to software implementation, one or more embodiments of the present disclosure do not exclude other implementation manners, such as a logic device or a combination of software and hardware, etc., that is, the execution subject of the following processing flow is not limited to each logic unit, but may also be hardware or a logic device.
The electronic equipment is configured with a main CPU, sub-CPUs and coprocessors, and is configured with a first serial port and a second serial port for external debugging, wherein the first serial port is connected with the main CPU, the second serial port is connected with the coprocessors, the coprocessors are connected with all the sub-CPUs, and the coprocessors are also connected with the main CPU; wherein:
the main CPU of the electronic device is used for informing the coprocessor to associate the second serial port with the target sub-CPU when receiving the debug command input by the first serial port and aiming at the target sub-CPU;
and the coprocessor of the electronic device is used for outputting the debugging information of the target sub-CPU to the outside through the second serial port after receiving the notification that the main CPU associates the second serial port with the target sub-CPU.
Optionally, the main CPU is further configured to: when a debug command for the main CPU input through a first serial port is received, the debug information of the main CPU is output to the outside through the first serial port.
Optionally, the main CPU and the coprocessor are preset with a mapping relationship between a sub CPU and a control register identifier;
the main CPU is specifically configured to, when notifying the coprocessor to associate the second serial port with the target sub-CPU: determining a control register identifier corresponding to the target sub-CPU based on the mapping relation, and modifying the control register identifier currently recorded by the control register into the control register identifier corresponding to the target sub-CPU;
after receiving notification that the main CPU associates the second serial port with the target sub-CPU, the coprocessor outputs debugging information of the target sub-CPU to the outside through the second serial port, and the method is specifically used for: after the control register identification is detected to be modified, determining a target sub-CPU corresponding to the modified control register identification based on the mapping relation, and outputting debugging information of the target sub-CPU through the second serial port.
Optionally, the main CPU is further configured to: and when receiving a state check command for one or more target sub-CPUs input through a first serial port, outputting the states of the one or more target sub-CPUs to the outside through the first serial port.
Optionally, the electronic device is a frame switch, the main CPU is a main control board CPU, the sub-CPU is a card board CPU and/or a subsystem CPU, and the coprocessor is a complex programmable logic device CPLD.
The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer, which may be in the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or a combination of any of these devices.
In a typical configuration, a computer includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, read only compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic disk storage, quantum memory, graphene-based storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by the computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The foregoing describes specific embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
The terminology used in the one or more embodiments of the specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of the specification. As used in this specification, one or more embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used in one or more embodiments of the present description to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of one or more embodiments of the present description. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
The foregoing description of the preferred embodiment(s) is (are) merely intended to illustrate the embodiment(s) of the present invention, and it is not intended to limit the embodiment(s) of the present invention to the particular embodiment(s) described.

Claims (10)

1. The device debugging method is characterized by being applied to electronic equipment provided with a main CPU, sub-CPUs and coprocessors, wherein the electronic equipment is provided with a first serial port and a second serial port for external debugging, the first serial port is connected with the main CPU, the second serial port is connected with the coprocessors, the coprocessors are connected with all the sub-CPUs, and the coprocessors are also connected with the main CPU;
the method comprises the following steps:
the main CPU of the electronic equipment informs the coprocessor to associate a second serial port with a target sub-CPU when receiving a debugging command input through the first serial port and aiming at the target sub-CPU;
after receiving a notification that the main CPU associates a second serial port with the target sub-CPU, the coprocessor of the electronic device outputs debugging information of the target sub-CPU to the outside through the second serial port;
the main CPU and the coprocessor are preset with a mapping relation between the sub-CPU and a control register mark;
the notification coprocessor associates a second serial port with the target sub-CPU, comprising:
and the main CPU determines the control register identifier corresponding to the target sub-CPU based on the mapping relation, and modifies the control register identifier currently recorded by the control register into the control register identifier corresponding to the target sub-CPU.
2. The method according to claim 1, wherein the method further comprises:
and when receiving a debugging command for the main CPU, the main CPU outputs the debugging information of the main CPU to the outside through the first serial port.
3. The method according to claim 1, wherein the outputting the debug information of the target sub-CPU to the outside through the second serial port after receiving the notification that the main CPU associates the second serial port with the target sub-CPU includes:
and after detecting that the control register identifier is modified, the coprocessor determines a target sub-CPU corresponding to the modified control register identifier based on the mapping relation, and outputs debugging information of the target sub-CPU to the outside through the second serial port.
4. The method according to claim 1, wherein the method further comprises:
and when receiving a state checking command for one or more target sub-CPUs input through a first serial port, the main CPU of the electronic equipment outputs the states of the one or more target sub-CPUs to the outside through the first serial port.
5. The method according to claim 1, wherein the electronic device is a frame switch, the main CPU is a main control board CPU, the sub-CPU is a card board CPU and/or a subsystem CPU, and the coprocessor is a complex programmable logic device CPLD.
6. The electronic equipment is characterized by being provided with a main CPU, sub-CPUs and coprocessors, and a first serial port and a second serial port which are used for external debugging, wherein the first serial port is connected with the main CPU, the second serial port is connected with the coprocessors, the coprocessors are connected with all the sub-CPUs, and the coprocessors are also connected with the main CPU;
wherein:
the main CPU of the electronic device is used for informing the coprocessor to associate the second serial port with the target sub-CPU when receiving the debug command input by the first serial port and aiming at the target sub-CPU;
the coprocessor of the electronic device is used for outputting debugging information of the target sub-CPU to the outside through the second serial port after receiving a notification that the main CPU associates the second serial port with the target sub-CPU;
the main CPU and the coprocessor are preset with a mapping relation between the sub-CPU and a control register mark;
the main CPU is specifically configured to, when notifying the coprocessor to associate the second serial port with the target sub-CPU:
and determining a control register identifier corresponding to the target sub-CPU based on the mapping relation, and modifying the control register identifier currently recorded by the control register into the control register identifier corresponding to the target sub-CPU.
7. The electronic device of claim 6, wherein the main CPU is further configured to:
when a debug command for the main CPU input through a first serial port is received, the debug information of the main CPU is output to the outside through the first serial port.
8. The electronic device of claim 6, wherein the coprocessor, after receiving the notification that the main CPU associates the second serial port with the target sub-CPU, outputs the debug information of the target sub-CPU to the outside through the second serial port, specifically for:
after the control register identification is detected to be modified, determining a target sub-CPU corresponding to the modified control register identification based on the mapping relation, and outputting debugging information of the target sub-CPU through the second serial port.
9. The electronic device of claim 6, wherein the main CPU is further configured to:
and when receiving a state check command for one or more target sub-CPUs input through a first serial port, outputting the states of the one or more target sub-CPUs to the outside through the first serial port.
10. The electronic device of claim 6, wherein the electronic device is a frame switch, the main CPU is a main control board CPU, the sub-CPU is a card board CPU and/or a subsystem CPU, and the coprocessor is a complex programmable logic device CPLD.
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