CN109885519A - A kind of connection switching method and master control borad - Google Patents
A kind of connection switching method and master control borad Download PDFInfo
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- CN109885519A CN109885519A CN201910103259.1A CN201910103259A CN109885519A CN 109885519 A CN109885519 A CN 109885519A CN 201910103259 A CN201910103259 A CN 201910103259A CN 109885519 A CN109885519 A CN 109885519A
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Abstract
The embodiment of the present application provides a kind of connection switching method and master control borad, master control borad includes master control borad CPU, master control borad CPLD, first master control borad serial ports and preset interface, first master control borad serial ports can be connected by master control borad CPLD with the CPU serial ports in the CPU of each board to be debugged, master control borad CPU is connected with master control borad CPLD and preset interface, when receiving connection switching command by preset interface, master control borad CPU determines the target CPU serial ports being connected with the first master control borad serial ports, the control instruction for carrying the mark of target CPU serial ports is sent to master control borad CPLD, the connection end point of first master control borad serial ports is switched to the tie point being connected with target CPU serial ports by master control borad CPLD, master control borad CPLD sends the debugging instruction received by the first master control borad serial ports To target CPU serial ports, it is based on above-mentioned processing, largely can be avoided master control borad CPU operation error.
Description
Technical field
This application involves fields of communication technology, more particularly to a kind of connection switching method and master control borad.
Background technique
With the fast development of Internet technology, the board of multiple types can be usually configured in cabinet, for example, master control
Plate, network interface card and line card etc..Serial ports (being properly termed as board serial ports) and Computer card CPU (Central can be configured in board
Processing Unit, central processing unit), and it can also be configured with serial ports (being properly termed as CPU serial ports) in Computer card CPU, board
CPU can pass through CPU serial ports acquisition instruction.
In the prior art, it usually can use master control borad CPLD (the Complex Program mable in master control borad
Logic Device, Complex Programmable Logic Devices) control cabinet in serial ports between connection type, to the plate in cabinet
Card is debugged.For example, may include master control borad, network interface card, line card and other equipment in cabinet, referring to Fig. 1, master control borad CPU with
Master control borad CPLD is connected, and serial ports includes serial ports TX D (Transmit Data, data are sent) pin and serial ports RXD (Receive
Data, data receiver) pin.The board serial ports of master control borad is connected with master control borad CPLD, in master control borad CPLD and cabinet respectively to
The CPU serial ports debugged in the CPU of board is connected, master control borad CPLD can control the board serial ports of master control borad with it is above-mentioned each to be debugged
The connection of CPU serial ports in the CPU of board.In Fig. 1, master control borad CPLD is by the board serial ports TXD pin and NULL of master control borad
(sky) is connected with the CPU serial ports RX D pin of master control borad CPU, by the board serial ports RXD pin of master control borad with master control borad CPU's
CPU serial ports TX D pin is connected.Circuit diagram based on Fig. 1, commissioning staff can debug master control borad.
When needing to debug the board (such as line card) in addition to master control borad, master control borad CPU passes through master control borad
Board serial ports can receive the connection switching command of commissioning staff's input, and master control borad CPU determines line card according to connection switching command
The CPU serial ports needs of CPU are connected with the board serial ports of master control borad, and the CPU string for carrying line card CPU is sent to master control borad CPLD
The control instruction of the mark of mouth.Master control borad CPLD disconnects the board serial ports of master control borad according to the mark of the CPU serial ports of line card CPU
The CPU serial ports TXD pin of the board serial ports RXD pin and master control borad CPU of the connection and master control borad of TXD pin and NULL
Connection, and the board serial ports TXD pin of master control borad is connected with the CPU serial ports RXD pin of line card CPU, by the board of master control borad
Serial ports RXD pin is connected with the CPU serial ports TXD pin of line card CPU, obtains circuit diagram shown in Fig. 2.Circuit diagram based on Fig. 2,
Commissioning staff can input debugging instruction by the board serial ports of master control board card, debug to realize to line card.
By Fig. 1 and Fig. 2 as it can be seen that when being debugged to other boards in addition to master control borad, in order to enable master control borad CPU
Enough receive connection switching command, the CPU serial ports RXD pin of the board serial ports TXD pin of master control borad and master control borad C PU are always
Connection, master control borad CPU may receive the debugging instruction that commissioning staff is inputted by the board serial ports TXD pin of master control borad,
Master control borad CPU runs the debugging instruction, will lead to master control borad CPU operation error.
Summary of the invention
The embodiment of the present application is designed to provide a kind of connection switching method and master control borad, can largely keep away
Exempt from master control borad CPU operation error.Specific technical solution is as follows:
In a first aspect, in order to achieve the above object, the embodiment of the present application discloses a kind of connection switching method, the method
Applied to master control borad, the master control borad include master control borad central processor CPU, master control borad complex programmable logic device (CPLD),
First master control borad serial ports and preset interface, the first master control borad serial ports can pass through the master control borad CPLD and each plate to be debugged
CPU serial ports in the CPU of card is connected, and the master control borad CPU is connected with the master control borad CPLD, the preset interface and the master
Plate CPU is controlled to be connected, which comprises
When the master control borad CPU by the preset interface receive connection switching command when, the master control borad CPU according to
The connection switching command determines the target CPU string being connected in the CPU of target board to be debugged with the first master control borad serial ports
Mouthful, and the control instruction for carrying the mark of the target CPU serial ports is sent to the master control borad CPLD, the control instruction is used
The connection end point of the first master control borad serial ports is switched to and the mesh from current attachment point in the instruction master control borad CPLD
Mark the connected tie point of CPU serial ports；
The master control borad CPLD is according to the mark of the target CPU serial ports, by the connecting pin of the first master control borad serial ports
Point switches to the tie point being connected with the target CPU serial ports from current attachment point；
When the master control borad CPLD receives debugging instruction by the first master control borad serial ports, the master control borad CPLD
The debugging instruction is sent to the target CPU serial ports, so that the target including the affiliated CPU of target CPU serial ports waits adjusting
The debugging instruction is received in test plate (panel) clamping.
Optionally, if the first master control borad serial ports passes through the master control borad CPLD and target board to be debugged
CPU serial ports in CPU is connected, then the current attachment point is to be connected with the CPU serial ports in the CPU of target board to be debugged
Tie point.
Optionally, the master control borad CPLD is according to the mark of the target CPU serial ports, by the first master control borad serial ports
Connection end point switches to the tie point being connected with the target CPU serial ports from current attachment point, comprising:
The master control borad CPLD is according to the mark of the target CPU serial ports, by the serial ports number of the first master control borad serial ports
It is connected according to TXD pin is sent with the serial data of target CPU serial ports reception RXD pin, by the first master control borad serial ports
Serial ports RXD pin be connected with the serial ports TXD pin of the target CPU serial ports.
Optionally, the preset interface is the network interface configured in the master control borad.
Optionally, the preset interface is the second master control borad serial ports configured in the master control borad.
Second aspect, in order to achieve the above object, the embodiment of the present application disclose a kind of master control borad, and the master control borad includes
Master control borad central processor CPU, master control borad complex programmable logic device (CPLD), the first master control borad serial ports and preset interface, institute
Stating the first master control borad serial ports can be connected by the master control borad CPLD with the CPU serial ports in the CPU of each board to be debugged, described
Master control borad CPU is connected with the master control borad CPLD, and the preset interface is connected with the master control borad CPU, in which:
The master control borad CPU, for when by the preset interface receive connection switching command when, according to the connection
Switching command, determines the target CPU serial ports being connected in the CPU of target board to be debugged with the first master control borad serial ports, and to
The master control borad CPLD sends the control instruction for carrying the mark of the target CPU serial ports, and the control instruction is used to indicate
The connection end point of the first master control borad serial ports is switched to from current attachment point and is gone here and there with the target CPU by the master control borad CPLD
The connected tie point of mouth；
The master control borad CPLD, for the mark according to the target CPU serial ports, by the company of the first master control borad serial ports
It connects endpoint and switches to the tie point being connected with the target CPU serial ports from current attachment point；
The master control borad CPLD is also used to when receiving debugging instruction by the first master control borad serial ports, will be described
Debugging instruction is sent to the target CPU serial ports, so as to include the target board to be debugged of the affiliated CPU of target CPU serial ports
Receive the debugging instruction.
Optionally, if the first master control borad serial ports passes through the master control borad CPLD and target board to be debugged
CPU serial ports in CPU is connected, then the current attachment point is to be connected with the CPU serial ports in the CPU of target board to be debugged
Tie point.
Optionally, the master control borad CPLD, it is main by described first specifically for the mark according to the target CPU serial ports
The serial data of control plate serial ports sends TXD pin and is connected with the serial data of target CPU serial ports reception RXD pin, by institute
The serial ports RXD pin for stating the first master control borad serial ports is connected with the serial ports TXD pin of the target CPU serial ports.
Optionally, the preset interface is the network interface configured in the master control borad.
Optionally, the preset interface is the second master control borad serial ports configured in the master control borad.
The embodiment of the present application provides a kind of connection switching method, be applied to master control borad, master control borad include master control borad CPU,
Master control borad CPLD, the first master control borad serial ports and preset interface, the first master control borad serial ports can by master control borad CPLD with respectively wait adjust
CPU serial ports in the CPU of test plate (panel) card is connected, and master control borad CPU is connected with master control borad CPLD, and preset interface is connected with master control borad CPU；
When master control borad CPU receives connection switching command by preset interface, master control borad CPU determines mesh according to connection switching command
The target CPU serial ports being connected in the CPU of board to be debugged with the first master control borad serial ports is marked, and is carried to master control borad CPLD transmission
The control instruction of the mark of target CPU serial ports；Master control borad CPLD is according to the mark of target CPU serial ports, by the first master control borad serial ports
Connection end point the tie point being connected with target CPU serial ports is switched to from current attachment point；When master control borad CPLD is main by first
When control plate serial ports receives debugging instruction, debugging instruction is sent to target CPU serial ports, including target CPU string by master control borad CPLD
The target board to be debugged of CPU belonging to mouthful then can receive debugging instruction.That is, if current first master control borad serial ports and master control
The CPU serial ports of plate CPU is connected, and needs to debug the board in addition to master control borad, and master control borad CPU can be connect by default
Mouth receives connection switching command, and then can control master control borad CPLD, disconnects the CPU of the first master control borad serial ports and master control borad CPU
The connection of serial ports, correspondingly, master control borad CPU can't get the tune that master control borad CPLD is received by the first master control borad serial ports
Examination instruction largely can be avoided master control borad CPU operation error.
Certainly, implement the application any product or method it is not absolutely required to and meanwhile reach above all advantages.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of application for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the schematic diagram that a kind of serial ports connects in the prior art；
Fig. 2 is the schematic diagram that a kind of serial ports connects in the prior art；
Fig. 3 is a kind of schematic diagram of serial ports connection provided by the embodiments of the present application；
Fig. 4 is a kind of flow chart of serial ports connection switching method provided by the embodiments of the present application；
Fig. 5 is a kind of schematic diagram of serial ports connection provided by the embodiments of the present application；
Fig. 6 is a kind of schematic diagram of serial ports connection provided by the embodiments of the present application；
Fig. 7 is a kind of schematic diagram of serial ports connection provided by the embodiments of the present application；
Fig. 8 is a kind of schematic diagram of serial ports connection provided by the embodiments of the present application.
Marginal data
1, master control borad 2, master control borad CPU
3, master control borad CPLD 4, the first master control borad serial ports
5, preset interface 6, network interface
7, the second master control borad serial ports 8, the first master control borad serial ports TXD pin
9, the first master control borad serial ports RXD pin 10, master control borad CPU serial ports
11, master control borad CPU serial ports TXD pin 12, master control borad CPU serial ports RXD pin
13, line card CPU 14, line card CPU serial ports
15, line card CPU serial ports TXD pin 16, line card CPU serial ports RXD pin
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
Now in the art, when debugging to other boards in addition to master control borad, master control borad CPU may pass through master
The board serial ports of control plate receives the debugging instruction for being debugged to other boards of commissioning staff's input, master control borad CPU
The debugging instruction is run, will lead to master control borad CPU operation error, for example, master control borad CPU is restarted, alternatively, master control borad CPU is hung extremely.
To solve the above-mentioned problems, the embodiment of the present application provides a kind of connection switching method, can be applied to master control borad,
Referring to Fig. 3, master control borad 1 includes master control borad CPU2, master control borad CPLD3, the first master control borad serial ports 4 and preset interface 5, master control borad
CPU2 is connected with master control borad CPLD3, and preset interface 5 is connected with master control borad CPU2.
Each tie point in master control borad CPLD3 can be connected with the CPU serial ports in the CPU of each board to be debugged.For example, adjusting
Examination personnel can according to business needs, by each tie point respectively with cabinet belonging to the CPU serial ports of master control borad CPU2, master control borad 1
In the CPU serial ports of line card, the CPU serial ports of network interface card in cabinet belonging to master control borad 1 or the CPU serial ports of other equipment be connected.
Master control borad CPLD3 can be according to the control instruction of master control borad CPU2, to the company being connected with the connection end point of the first master control borad serial ports 4
Contact switches over, and the first master control borad serial ports 4 is enabled to pass through the CPU in the CPU of master control borad CPLD3 and each board to be debugged
Serial ports is connected.
Connection switching method based on the application, master control borad CPU2 can receive commissioning staff's input by preset interface 5
Connection switching command, then, master control borad CPU2 can be according to connection switching command, in the CPU for determining target board to be debugged
The target CPU serial ports being connected with the first master control borad serial ports 4, and the mark for carrying target CPU serial ports is sent to master control borad CPLD3
Control instruction.Master control borad CPLD3 then can be according to the mark of target CPU serial ports, by the connection end point of the first master control borad serial ports 4
The tie point being connected with target CPU serial ports is switched to from current attachment point.
When master control borad CPLD3 receives debugging instruction by the first master control borad serial ports 4, master control borad CPLD3 can will be adjusted
Examination instruction is sent to target CPU serial ports, and the target board to be debugged including the affiliated CPU of target CPU serial ports then can receive this
Debugging instruction.
As it can be seen that if current first master control borad serial ports 4 is connected with the CPU serial ports of master control borad CPU2, and needs are to except master control
Board other than plate 1 is debugged, and master control borad CPU2 can receive connection switching command by preset interface 5.Due to master control
Plate CPU2 is connected with master control borad CPLD3, master control borad CPU2 then can control master control borad CPLD3 disconnect the first master control borad serial ports 4 with
The connection of the CPU serial ports of master control borad CPU2.When commissioning staff inputs debugging instruction to the first master control borad serial ports 4, master control borad
CPU2 can't get the debugging instruction, can be largely avoided master control borad CPU2 operation error.
It referring to fig. 4, is a kind of flow chart of connection switching method provided by the embodiments of the present application, this method can be applied to
Master control borad 1 shown in Fig. 3, this method may comprise steps of:
S401: when master control borad CPU2 receives connection switching command by preset interface 5, master control borad CPU2 is according to connection
Switching command, determines the target CPU serial ports being connected in the CPU of target board to be debugged with the first master control borad serial ports 4, and to master control
Plate CPLD3 sends the control instruction for carrying the mark of target CPU serial ports.
Wherein, control instruction is used to indicate master control borad CPLD3 and connects the connection end point of the first master control borad serial ports 4 from current
Point switches to the tie point being connected with target CPU serial ports.The mark of target CPU serial ports can also be carried in connection switching command
Know.Target CPU serial ports can be any CPU serial ports in the CPU of each board to be debugged.For example, target CPU serial ports can be based on
Control the CPU serial ports of the line card in cabinet belonging to plate 1, or the CPU serial ports of the network interface card in cabinet belonging to master control borad 1,
It can also be the CPU serial ports of master control borad CPU2.
In application embodiment, when needing the connection to serial ports to switch over, commissioning staff can be defeated to preset interface 5
Enter to connect switching command.Master control borad CPU2 can then receive the connection switching command by preset interface 5, and identify the connection
Switching command determines the CPU string in the target board to be debugged that will be connected with the first master control borad serial ports 4 in each board to be debugged
Mouth (i.e. target CPU serial ports), then, master control borad CPU2 can send the mark that carry target CPU serial ports to master control borad CPLD3
Control instruction, to indicate that master control borad CPLD3 switches to the connection end point of the first master control borad serial ports 4 and mesh from current attachment point
Mark the connected tie point of CPU serial ports.
Since preset interface 5 is different from the first master control borad serial ports 4, the connection switching side based on the embodiment of the present application
Method makes the first master control borad serial ports 4 not be connected always with the CPU serial ports of master control borad CPU2, and master control borad CPU2 can be by default
Interface 5 receives connection switching command, and controls master control borad CPLD3 and switch over to the connection of serial ports.
Preset interface 5 can be different types of interface, and referring to Fig. 5, preset interface 5 can be the net configured in master control borad
Mouth 6.
Wherein, which can communicate with master control borad CPU2, for example, can be with base between network interface 6 and master control borad CPU2
It is communicated in Telnet (remote terminal protocol).
In application embodiment, network interface 6 can be connected with master control borad CPU2, and network interface 6 is for receiving connection switching command.
For example, commissioning staff can input connection switching command to master control borad CPU2 by network interface 6.Master control borad CPU2 then may be used
To identify the connection switching command received, and then it can control master control borad CPLD3 and the connection of serial ports switched over.
Alternatively, another master control borad serial ports (i.e. the second master control borad serial ports configured in preset interface 5 or master control borad 1
7), referring to Fig. 6.
In application embodiment, another serial ports different from the first master control borad serial ports 4 can be configured in master control borad 1
(i.e. the second master control borad serial ports 7).Second master control borad serial ports 7 can be connected with master control borad CPU2, and the second master control borad serial ports 7 is for connecing
Receive connection switching command.
For example, commissioning staff can input connection switching command, master control to master control borad CPU2 by the second master control borad serial ports 7
Plate CPU2 can then identify the connection switching command received, and then can control master control borad CPLD3 and carry out to the connection of serial ports
Switching.
From the foregoing, it will be observed that the embodiment of the present application will connect the coffret point of the coffret and debugging instruction of switching command
It opens, makes to connect switching command and debugging instruction is transmitted not by same interface.By the analysis to the prior art it is found that due to
Connection switching command is the switching for itself connection type of master control borad 1, so connection switching command will pass through master control borad CPU2
It identifies and controls master control borad CPLD3 and realize switching, if therefore connecting the coffret of switching command and the transmission of debugging instruction connects
It mouthful is same interface, then then there is a strong possibility receives debugging instruction for other boards by master control borad CPU2.The application is real
It applies example to separate the coffret for connecting switching command and the coffret of debugging instruction, makes to connect switching command and debugging instruction
It is transmitted not by same interface, then the debugging instruction avoided from source for other boards is transferred to master control borad CPU2
On.
S402: master control borad CPLD3 according to the mark of target CPU serial ports, by the connection end point of the first master control borad serial ports 4 from working as
Preceding tie point switches to the tie point being connected with target CPU serial ports.
In application embodiment, after master control borad CPLD3 receives control instruction, the available target of master control borad CPLD3
The mark of CPU serial ports, and the connection end point of the first master control borad serial ports 4 is switched to and target CPU serial ports phase from current attachment point
Tie point even, the first master control borad serial ports 4 is connected with target CPU serial ports.
Optionally, if the first master control borad serial ports 4 is gone here and there by the CPU in the CPU of master control borad CPLD3 and target board to be debugged
Mouth is connected, then current attachment point is the tie point being connected with the CPU serial ports in the CPU of target board to be debugged.
It include multiple tie points in master control borad CPLD3 in application embodiment, tie point is used for and each board to be debugged
CPU serial ports in CPU is connected.
Such as: master control borad CPLD3 includes the tie point for being connected with the CPU serial ports in master control borad CPU2, if first
Master control borad serial ports 4 is currently connected by master control borad CPLD3 with the target CPU serial ports in master control borad CPU2, then current attachment point is
The tie point being connected with the target CPU serial ports of master control borad CPU2.
In addition, serial ports usually may include serial ports TXD pin and serial ports RXD pin, then S402 may comprise steps of:
Master control borad CPLD3 is according to the mark of target CPU serial ports, by the serial ports TXD pin of the first master control borad serial ports 4 and target CPU serial ports
Serial ports RXD pin be connected, by the serial ports TXD pin phase of the serial ports RXD pin of the first master control borad serial ports 4 and target CPU serial ports
Even.
In application embodiment, the mark of the target CPU serial ports carried in control instruction is got in master control borad CPLD3
Afterwards, master control borad CPLD3 can be by the serial ports RXD pin phase of the serial ports TXD pin of the first master control borad serial ports 4 and target CPU serial ports
Even, and the serial ports RXD pin of the first master control borad serial ports 4 is connected with the serial ports TXD pin of target CPU serial ports, to realize first
Master control borad serial ports 4 is connected with target CPU serial ports.
In this step, master control borad CPLD3 can also disconnect the serial ports TXD pin of the first master control borad serial ports 4 with currently connect
CPU serial ports serial ports RXD pin connection, and disconnect the serial ports RXD pin of the first master control borad serial ports 4 with currently connect
The connection of the serial ports TXD pin of CPU serial ports, to disconnect the connection of the first master control borad serial ports 4 and the CPU serial ports currently connecting.
Wherein, the serial ports TXD pin of the first master control borad serial ports 4 can be used for receiving debugging instruction, the first master control borad serial ports 4
Serial ports RXD pin can be used for exporting the debugging result data that the CPU serial ports that currently connects returns.For example, commissioning staff can
To pass through the serial ports TXD pin of the first master control borad serial ports 4, to the master control borad CPU2's being currently connected with the first master control borad serial ports 4
CPU serial ports inputs debugging instruction, and master control borad CPU2 then can receive the debugging by the serial ports RXD pin of itself CPU serial ports
Instruction, and runs the debugging instruction, and then, master control borad CPU2 can be by the serial ports TXD pin of the CPU serial ports of itself, to the
The serial ports RXD pin of one master control borad serial ports 4 returns to debugging result data, and commissioning staff can then pass through the first master control borad serial ports 4
Serial ports RXD pin obtain the debugging result data.
As can be seen that the embodiment of the present application is by the route of the first master control borad serial ports 4 and master control borad CPU2 by the prior art
Always Innovation of Connection is optional connection.It is subsequent when by the first master control borad serial ports 4 to other boards transmit debugging instruction when, master control
Plate CPU2 controls master control borad CPLD3 again and disconnects the route of the first master control borad serial ports 4 and master control borad CPU2, then can be from transmission road
The debugging instruction for other boards is avoided to be transferred on master control borad CPU2 on line.
S403: when master control borad CPLD3 receives debugging instruction by the first master control borad serial ports 4, master control borad CPLD3 will be adjusted
Examination instruction is sent to target CPU serial ports, refers to so that the board to be debugged of the target including the affiliated CPU of target CPU serial ports receives debugging
It enables.
In application embodiment, when commissioning staff needs to the target board to be debugged including the affiliated CPU of target CPU serial ports
When being debugged, commissioning staff can input debugging instruction to the first master control borad serial ports 4.Correspondingly, master control borad CPLD3 can lead to
It crosses the first master control borad serial ports 4 and receives the debugging instruction, since current first master control borad serial ports 4 is connected with target CPU serial ports, because
This, which can be sent to target CPU serial ports by master control borad CPLD3, that is, target board to be debugged can receive tune
Examination instruction, and the debugging instruction is run, realize the debugging to target board to be debugged.
From the foregoing, it will be observed that the embodiment of the present application will connect the coffret point of the coffret and debugging instruction of switching command
It opens, makes to connect switching command and debugging instruction is transmitted not by same interface.By the analysis to the prior art it is found that due to
Connection switching command is the switching for itself connection type of master control borad 1, so connection switching command will pass through master control borad CPU2
It identifies and controls master control borad CPLD3 and realize switching, if therefore connecting the coffret of switching command and the transmission of debugging instruction connects
It mouthful is same interface, then then there is a strong possibility receives debugging instruction for other boards by master control borad CPU2.The application is real
It applies example to separate the coffret for connecting switching command and the coffret of debugging instruction, makes to connect switching command and debugging instruction
It is transmitted not by same interface, then the debugging instruction avoided from source for other boards is transferred to master control borad CPU2
On.
Further, the embodiment of the present application is by the route of the first master control borad serial ports 4 and master control borad CPU2 by the prior art
Always Innovation of Connection is optional connection.It is subsequent when by the first master control borad serial ports 4 to other boards transmit debugging instruction when, master control
Plate CPU2 controls master control borad CPLD3 again and disconnects the route of the first master control borad serial ports 4 and master control borad CPU2, then can be from transmission road
The debugging instruction for other boards is avoided to be transferred on master control borad CPU2 on line.
To sum up, the embodiment of the present application can make master control borad CPU2 control master control borad CPLD3 realize cutting for serial ports connection type
It changes, and can be when sending debugging instruction to the CPU of other boards in addition to master control borad CPU2, the transmission route of debugging instruction is simultaneously
Without master control borad CPU2, it is possible thereby to the debugging instruction for the CPU for avoiding master control borad CPU2 from receiving for other boards.
Referring to Fig. 7, the first master control borad serial ports 4 may include that serial ports TXD pin (is properly termed as the first master control borad serial ports TXD
Pin 8) and serial ports RXD pin (being properly termed as the first master control borad serial ports RXD pin 9).CPU serial ports is configured in master control borad CPU2
(being properly termed as master control borad CPU serial ports 10), master control borad CPU serial ports 10 may include that serial ports TXD pin (is properly termed as master control borad
CPU serial ports TXD pin 11) and serial ports RXD pin (being properly termed as master control borad CPU serial ports RXD pin 12).
In general, the default conditions after cabinet belonging to master control borad 1 powers on can be the first master control borad serial ports 4 and master control borad
CPU serial ports 10 is connected, i.e. in Fig. 7, the first master control borad serial ports TXD pin 8 is connected with master control borad CPU serial ports RXD pin 12, and first
Master control borad serial ports RXD pin 9 is connected with master control borad CPU serial ports TXD pin 11.
In addition, can be configured with line card in cabinet, it is configured with line card CPU13 in the line card, is configured in line card CPU13
CPU serial ports (is properly termed as line card CPU serial ports 14), and line card CPU serial ports 14 may include that serial ports TXD pin (is properly termed as line card
CPU serial ports TXD pin 15) and serial ports RXD pin (being properly termed as line card CPU serial ports RXD pin 16).
Based on Fig. 7, when needing to debug the line card, commissioning staff can be by preset interface 5 to master control borad
CPU2 input carries the connection switching command of the mark of line card CPU serial ports 14.Master control borad CPU2 receives connection switching command
Afterwards, it can determine that target CPU serial ports is line card CPU serial ports 14, and carry line card CPU serial ports 14 to master control borad CPLD3 transmission
Mark control instruction.
When master control borad CPLD3 receives control instruction, the mark of the available line card CPU serial ports 14 of master control borad CPLD3.
Master control borad CPLD3 can disconnect the connection of the first master control borad serial ports TXD pin 8 and master control borad CPU serial ports RXD pin 12, and break
Open the connection of the first master control borad serial ports RXD pin 9 and master control borad CPU serial ports TXD pin 11.
Then, master control borad CPLD3 can be by the first master control borad serial ports TXD pin 8 and 16 phase of line card CPU serial ports RXD pin
Even, and the first master control borad serial ports RXD pin 9 is connected with line card CPU serial ports TXD pin 15, obtains connection figure shown in Fig. 8.
Based on the connection of serial ports shown in Fig. 8, commissioning staff can be inputted by the first master control borad serial ports TXD pin 8 and be adjusted
Examination instruction, after master control borad CPLD3 receives debugging instruction, master control borad CPLD3 can by line card CPU serial ports RXD pin 16,
Debugging instruction is sent to line card CPU13, the line card comprising line card CPU13 then can receive and run debugging instruction, realization pair
The debugging of the line card.
It is understood that if the connection of current serial ports is shown in Fig. 8, if commissioning staff needs to carry out master control borad 1
Debugging, commissioning staff can carry the company of the mark of master control borad CPU serial ports 10 by preset interface 5 to master control borad CPU2 input
Connect switching command.After master control borad CPU2 receives connection switching command, it can determine that target CPU serial ports is master control borad CPU serial ports
10, and the control instruction for carrying the mark of master control borad CPU serial ports 10 is sent to master control borad CPLD3.
When master control borad CPLD3 receives control instruction, the mark of the available master control borad CPU serial ports 10 of master control borad CPLD3
Know.Master control borad CPLD3 can disconnect the connection of the first master control borad serial ports TXD pin 8 and line card CPU serial ports RXD pin 16, and break
Open the connection of the first master control borad serial ports RXD pin 9 and line card CPU serial ports TXD pin 15.
Then, master control borad CPLD3 can be by the first master control borad serial ports TXD pin 8 and master control borad CPU serial ports RXD pin 12
It is connected, and the first master control borad serial ports RXD pin 9 is connected with master control borad CPU serial ports TXD pin 11, and then obtains shown in Fig. 7
Connection figure.
As seen from the above, it is based on connection switching method provided by the embodiments of the present application, when master control borad CPU2 is connect by default
When mouth connects 5 and receives connection switching command, master control borad CPU2 is according to connection switching command, in the CPU for determining target board to be debugged
The target CPU serial ports being connected with the first master control borad serial ports 4, and the mark for carrying target CPU serial ports is sent to master control borad CPLD3
Control instruction.Master control borad CPLD3 is according to the mark of target CPU serial ports, by the connection end point of the first master control borad serial ports 4 from current
Tie point switches to the tie point being connected with target CPU serial ports, when master control borad CPLD3 is received by the first master control borad serial ports 4
When debugging instruction, debugging instruction is sent to target CPU serial ports by master control borad CPLD3, the mesh including the affiliated CPU of target CPU serial ports
Marking board to be debugged then can receive debugging instruction.That is, if the CPU of current first master control borad serial ports 4 and master control borad CPU2
Serial ports is connected, and needs to debug the board in addition to master control borad 1, and master control borad CPU2 can be received by preset interface 5
Switching command is connected, and then can control master control borad CPLD3, disconnects the CPU serial ports of the first master control borad serial ports 4 and master control borad CPU2
Connection, correspondingly, master control borad CPU2, which can't receive master control borad CPLD3, passes through the tune that receives of the first master control borad serial ports 4
Examination instruction can be largely avoided master control borad CPU2 operation error.
The embodiment of the present application also provides a kind of master control borads, and referring again to Fig. 3, master control borad 1 includes master control borad CPU2, master control
Plate CPLD3, the first master control borad serial ports 4 and preset interface 5, the first master control borad serial ports 4 can by master control borad CPLD3 with respectively wait adjust
CPU serial ports in the CPU of test plate (panel) card is connected, and master control borad CPU2 is connected with master control borad CPLD3, preset interface 5 and master control borad CPU2
It is connected, in which:
Master control borad CPU2, for when by preset interface 5 receive connection switching command when, according to connection switching command,
It determines the target CPU serial ports being connected in the CPU of target board to be debugged with the first master control borad serial ports 4, and is sent out to master control borad CPLD3
The control instruction for carrying the mark of target CPU serial ports is sent, control instruction is used to indicate master control borad CPLD3 for the first master control borad string
The connection end point of mouth 4 switches to the tie point being connected with target CPU serial ports from current attachment point；
Master control borad CPLD3, for the mark according to target CPU serial ports, by the connection end point of the first master control borad serial ports 4 from working as
Preceding tie point switches to the tie point being connected with target CPU serial ports；
Master control borad CPLD3 is also used to send out debugging instruction when receiving debugging instruction by the first master control borad serial ports 4
It send to target CPU serial ports, so that the board to be debugged of the target including the affiliated CPU of target CPU serial ports receives debugging instruction.
Optionally, if the first master control borad serial ports 4 is gone here and there by the CPU in the CPU of master control borad CPLD3 and target board to be debugged
Mouth is connected, then current attachment point is the tie point being connected with the CPU serial ports in the CPU of target board to be debugged.
Optionally, referring again to Fig. 7 and Fig. 8, master control borad CPLD3 will specifically for the mark according to target CPU serial ports
The serial data of first master control borad serial ports 4 sends TXD pin (i.e. the first master control borad serial ports TXD pin 8) and target CPU serial ports
Serial data receives RXD pin and is connected, by serial ports RXD pin (i.e. the first master control borad serial ports RXD pin of the first master control borad serial ports
9) it is connected with the serial ports TXD pin of target CPU serial ports.
Optionally, referring again to Fig. 5, preset interface 5 is the network interface 6 configured in master control borad 1.
Optionally, referring again to Fig. 6, preset interface 5 is the second master control borad serial ports 7 configured in master control borad 1.
As seen from the above, when master control borad CPU2, which connects 5 by preset interface, receives connection switching command, master control borad CPU2 root
According to connection switching command, the target CPU serial ports being connected in the CPU of target board to be debugged with the first master control borad serial ports 4 is determined, and
The control instruction for carrying the mark of target CPU serial ports is sent to master control borad CPLD3；Master control borad CPLD3 is according to target CPU serial ports
Mark, the connection end point of the first master control borad serial ports 4 is switched to the connection being connected with target CPU serial ports from current attachment point
Point；When master control borad CPLD3 receives debugging instruction by the first master control borad serial ports 4, master control borad CPLD3 sends debugging instruction
To target CPU serial ports, the target board to be debugged including the affiliated CPU of target CPU serial ports then can receive debugging instruction.That is,
If current first master control borad serial ports 4 is connected with the CPU serial ports of master control borad CPU2, and needs to the board in addition to master control borad 1
It being debugged, master control borad CPU2 can receive connection switching command by preset interface 5, and then can control master control borad CPLD3,
The connection for disconnecting the CPU serial ports of the first master control borad serial ports 4 and master control borad CPU2, correspondingly, master control borad CPU2 can't be received
Master control borad CPLD3 passes through the debugging instruction that the first master control borad serial ports 4 receives, and can be largely avoided master control borad CPU2
Operation error.
In the above-described embodiments, can come wholly or partly by software, hardware, firmware or any combination thereof real
It is existing.When implemented in software, it can entirely or partly realize in the form of a computer program product.The computer program
Product includes one or more computer instructions.When loading on computers and executing the computer program instructions, all or
It partly generates according to process or function described in the embodiment of the present application.The computer can be general purpose computer, dedicated meter
Calculation machine, computer network or other programmable devices.The computer instruction can store in computer readable storage medium
In, or from a computer readable storage medium to the transmission of another computer readable storage medium, for example, the computer
Instruction can pass through wired (such as coaxial cable, optical fiber, number from a web-site, computer, server or data center
User's line (DSL)) or wireless (such as infrared, wireless, microwave etc.) mode to another web-site, computer, server or
Data center is transmitted.The computer readable storage medium can be any usable medium that computer can access or
It is comprising data storage devices such as one or more usable mediums integrated server, data centers.The usable medium can be with
It is magnetic medium, (for example, floppy disk, hard disk, tape), optical medium (for example, DVD) or semiconductor medium (such as solid state hard disk
Solid State Disk (SSD)) etc..
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
Each embodiment in this specification is all made of relevant mode and describes, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for master control borad
For embodiment, since it is substantially similar to the method embodiment, so being described relatively simple, related place is implemented referring to method
The part explanation of example.
The foregoing is merely the preferred embodiments of the application, are not intended to limit the protection scope of the application.It is all
Any modification, equivalent replacement, improvement and so within spirit herein and principle are all contained in the protection scope of the application
It is interior.
Claims (10)
1. a kind of connection switching method, which is characterized in that the method is applied to master control borad, and the master control borad includes in master control borad
Central processor CPU, master control borad complex programmable logic device (CPLD), the first master control borad serial ports and preset interface, described first is main
Control plate serial ports can be connected by the master control borad CPLD with the CPU serial ports in the CPU of each board to be debugged, the master control borad
CPU is connected with the master control borad CPLD, and the preset interface is connected with the master control borad CPU, which comprises
When the master control borad CPU receives connection switching command by the preset interface, the master control borad CPU is according to
Switching command is connected, determines the target CPU serial ports being connected in the CPU of target board to be debugged with the first master control borad serial ports,
And the control instruction for carrying the mark of the target CPU serial ports is sent to the master control borad CPLD, the control instruction is used for
Indicate that the master control borad CPLD switches to the connection end point of the first master control borad serial ports and the target from current attachment point
The connected tie point of CPU serial ports；
The master control borad CPLD according to the mark of the target CPU serial ports, by the connection end point of the first master control borad serial ports from
Current attachment point switches to the tie point being connected with the target CPU serial ports；
When the master control borad CPLD receives debugging instruction by the first master control borad serial ports, the master control borad CPLD is by institute
It states debugging instruction and is sent to the target CPU serial ports, so as to include the target plate to be debugged of the affiliated CPU of target CPU serial ports
The debugging instruction is received in clamping.
2. the method according to claim 1, wherein if the first master control borad serial ports passes through the master control borad
CPLD is connected with the CPU serial ports in the CPU of target board to be debugged, then the current attachment point is to wait adjusting with the target
The tie point that CPU serial ports in the CPU of test plate (panel) card is connected.
3. method according to claim 1 or 2, which is characterized in that the master control borad CPLD is according to the target CPU serial ports
Mark, the connection end point of the first master control borad serial ports is switched to from current attachment point and is connected with the target CPU serial ports
Tie point, comprising:
The master control borad CPLD sends out the serial data of the first master control borad serial ports according to the mark of the target CPU serial ports
It send TXD pin to receive RXD pin with the serial data of the target CPU serial ports to be connected, by the string of the first master control borad serial ports
Mouth RXD pin is connected with the serial ports TXD pin of the target CPU serial ports.
4. the method according to claim 1, wherein the preset interface is the net configured in the master control borad
Mouthful.
5. the method according to claim 1, wherein the preset interface is second configured in the master control borad
Master control borad serial ports.
6. a kind of master control borad, which is characterized in that the master control borad includes that master control borad central processor CPU, master control borad complexity can be compiled
Journey logic device (CPLD), the first master control borad serial ports and preset interface, the first master control borad serial ports can pass through the master control borad
CPLD is connected with the CPU serial ports in the CPU of each board to be debugged, and the master control borad CPU is connected with the master control borad CPLD, described
Preset interface is connected with the master control borad CPU, in which:
The master control borad CPU, for being switched according to the connection when receiving connection switching command by the preset interface
Instruction, determines the target CPU serial ports being connected in the CPU of target board to be debugged with the first master control borad serial ports, and to described
Master control borad CPLD sends the control instruction for carrying the mark of the target CPU serial ports, and the control instruction is used to indicate described
Master control borad CPLD switches to the connection end point of the first master control borad serial ports and the target CPU serial ports phase from current attachment point
Tie point even；
The master control borad CPLD, for the mark according to the target CPU serial ports, by the connecting pin of the first master control borad serial ports
Point switches to the tie point being connected with the target CPU serial ports from current attachment point；
The master control borad CPLD is also used to when receiving debugging instruction by the first master control borad serial ports, by the debugging
Instruction is sent to the target CPU serial ports, so that the board to be debugged of the target including the affiliated CPU of target CPU serial ports receives
The debugging instruction.
7. master control borad according to claim 6, which is characterized in that if the first master control borad serial ports passes through the master control borad
CPLD is connected with the CPU serial ports in the CPU of target board to be debugged, then the current attachment point is to wait adjusting with the target
The tie point that CPU serial ports in the CPU of test plate (panel) card is connected.
8. master control borad according to claim 6 or 7, which is characterized in that the master control borad CPLD is specifically used for according to
The serial data of the first master control borad serial ports is sent TXD pin and the target CPU serial ports by the mark of target CPU serial ports
Serial data receive RXD pin be connected, by the serial ports RXD pin of the first master control borad serial ports and the target CPU serial ports
Serial ports TXD pin be connected.
9. master control borad according to claim 6, which is characterized in that the preset interface is the net configured in the master control borad
Mouthful.
10. master control borad according to claim 6, which is characterized in that configured in the preset interface master control borad
Second master control borad serial ports.
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Cited By (1)
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| CN113535494A (en) * | 2021-07-28 | 2021-10-22 | 杭州迪普科技股份有限公司 | Equipment debugging method and electronic equipment |
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