WO2020258200A1

WO2020258200A1 - Interrupt information storage device and removable platform

Info

Publication number: WO2020258200A1
Application number: PCT/CN2019/093496
Authority: WO
Inventors: 李飞
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2019-06-28
Filing date: 2019-06-28
Publication date: 2020-12-30
Also published as: CN111699474A

Abstract

Provided are an interrupt information storage device and a removable platform, when the preset interrupt signal in the multiple interrupt signals changes, the sampling circuit samples the status information of the multiple interrupt signals according to a first clock signal with relatively high frequency, and sends the status information of the multiple interrupt signals to the storage circuit, the storage circuit stores the status information of the multiple interrupt signals according to a second clock signal with relatively low frequency, so that the status information of the multiple interrupt signals can be latched when the preset interrupt signal changes, so as to analyze the sequence of each interrupt signal according to the status information of the multiple interrupt signals, improving the accuracy of the sequence acquisition of interrupt signals and avoiding the risk of incorrect sequence acquisition of interrupt signals.

Description

Interruption of information storage devices and removable platforms

Technical field

The embodiment of the present invention relates to the technical field of interrupt processing, in particular to an interrupt information storage device and a movable platform.

Background technique

When the interrupt source has multiple interrupt signal outputs, the interrupt sequence of the multiple interrupt signals is sometimes indispensable, and needs to be locked in the configuration register and read out through the software interface.

The existing method of obtaining interrupt signals in sequence usually uses multiple interrupt signals to share a counter. When each interrupt is latched, the counter value at this time is also latched together, and each interrupt latched counter value can be obtained by comparing each interrupt. The sequence of interrupt signal interruption.

The existing method for obtaining the interrupt signal sequence relies on the counter. If the counter count overflows, the sequence of the latch will not be the true sequence, resulting in an error in the sequence of the interrupt signal.

Summary of the invention

The embodiment of the present invention provides an interrupt information storage device and a movable platform to store state information of the plurality of interrupt signals when the preset interrupt signal of the plurality of interrupt signals changes, so as to be based on the state of the plurality of interrupt signals The information analyzes the sequence of the interrupt signal, improves the accuracy of the sequence acquisition of the interrupt signal, and avoids the risk of the sequence acquisition of the interrupt signal.

The first aspect of the embodiments of the present invention provides an interrupt information storage device, which includes a sampling circuit and a storage circuit connected to each other:

The sampling circuit is used to receive a plurality of interrupt signals and a first clock signal; when a preset interrupt signal in the plurality of interrupt signals changes, respond to the plurality of interrupt signals according to the first clock signal Sampling the status information of the multiple interrupt signals, and sending the status information of the multiple interrupt signals to the storage circuit;

The storage circuit is configured to receive a second clock signal; perform a storage operation on the state information of the multiple interrupt signals according to the second clock signal;

Wherein, the frequency of the first clock signal is greater than the frequency of the second clock signal.

A second aspect of the embodiments of the present invention provides a movable platform, including a sensor system, a power system, and the interrupt state storage device as described in the first aspect, and the sensor system is used to collect state information of the movable platform And/or environmental information; the power system is used to provide power for the movable platform;

The sensor system and the power system are also used to generate a plurality of interrupt signals to send to the interrupt state storage device;

The interrupted state storage device includes a sampling circuit and a storage circuit connected to each other;

The sampling circuit is configured to receive the plurality of interrupt signals and a first clock signal; when a preset interrupt signal in the plurality of interrupt signals changes, according to the first clock signal, the plurality of Sampling the status information of the interrupt signal, and sending the status information of the multiple interrupt signals to the storage circuit;

In the interrupt information storage device and the movable platform provided by the embodiment of the present invention, when the preset interrupt signal in the multiple interrupt signals changes, the sampling circuit responds to the multiple interrupt signals according to the first clock signal with a relatively high frequency. The status information of the multiple interrupt signals is sampled, and the status information of the multiple interrupt signals is sent to the storage circuit. The storage circuit stores the status information of the multiple interrupt signals according to the relatively low-frequency second clock signal, so as to realize the When the preset interrupt signal changes, the status information of the multiple interrupt signals is latched, so as to analyze the sequence of the interrupt signals according to the status information of the multiple interrupt signals, improve the accuracy of the sequence acquisition of the interrupt signals, and avoid the sequence of the interrupt signals Risk of getting errors.

Description of the drawings

In order to explain the technical solutions in the embodiments of the present invention more clearly, the following will briefly introduce the drawings used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative labor.

Figure 1 is a structural diagram of an interrupt information storage device provided by an embodiment of the present invention;

2 is a structural diagram of an interrupt information storage device provided by another embodiment of the present invention;

3 is a structural diagram of an interrupt information storage device provided by another embodiment of the present invention;

4 is a timing diagram of signals in an interrupt information storage device provided by an embodiment of the present invention;

Fig. 5 is a movable platform provided by an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

It should be noted that when a component is considered to be "connected" to another component, it may be directly connected to another component or a centered component may exist at the same time.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present invention. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The term "and/or" as used herein includes any and all combinations of one or more related listed items.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

The embodiment of the present invention provides an interrupt information storage device. FIG. 1 is a structural diagram of an interrupt information storage device provided by an embodiment of the present invention. As shown in FIG. 1, the interrupt information storage device includes a sampling circuit 10 and a storage circuit 20 connected to each other.

The sampling circuit 10 is used to receive multiple interrupt signals (for example, the multiple interrupt signals shown in FIG. 1 may include interrupt signals a, b, and c) and a first clock signal; among the multiple interrupt signals When a change occurs in the preset interrupt signal (in this embodiment, only the interrupt signal a is used as the preset terminal signal), the status information of the multiple interrupt signals is sampled according to the first clock signal, and the Sending the status information of the multiple interrupt signals to the storage circuit 20;

The storage circuit 20 is configured to receive a second clock signal; perform a storage operation on the state information of the multiple interrupt signals according to the second clock signal;

Wherein, the frequency of the first clock signal is greater than the frequency of the second clock signal. That is, the sampling circuit 10 works in the high-speed clock domain, and the storage circuit 20 works in the low-speed clock domain (the height of the clock domain in this embodiment is relative).

In this embodiment, when the preset interrupt signal a is interrupted, the sampling circuit 10 working in the high-speed clock domain can sample the status information of the interrupt signals a, b, and c according to the first clock signal, for example, the interrupt signal a is generated. When interrupted, and the interrupt signals b and c are not interrupted, the status information of the interrupt signals a, b, and c sampled by the sampling circuit 10 is 100, where 1 indicates that the interrupt has occurred, and 0 indicates that the interrupt has not occurred. Through the status information It can be known that the interrupt signal a has interrupted before the interrupt signals b and c; if the interrupt signal c has been interrupted and the interrupt signal b has not been interrupted, the status information of the interrupt signals a, b, and c obtained by the sampling circuit 10 is 101. Through the status information, it can be known that the interrupt signal a occurs after the interrupt signal c and before the interrupt signal b. Since the sampling circuit 10 works in the high-speed clock domain, its sampling time granularity is finer, and the status information of each interrupt signal can be collected more accurately when the preset interrupt signal is interrupted, so that each interrupt signal can be distinguished more accurately The order of precedence. Further, the sampling circuit 10 can also latch the status information.

The storage circuit 20 stores the state information of a plurality of interrupt signals according to the second clock signal. The storage circuit 20 in this embodiment can also provide an output port, and other analysis devices can read the status information of multiple interrupt signals latched in the storage circuit 20 through the output interface, and then can analyze the status information of the multiple interrupt signals , The sequence of acquiring the multiple interrupt signals, since the frequency of reading data by the analysis device is not high, the storage circuit 20 only needs to work in the low-speed clock domain. In this embodiment, the storage circuit 20 can realize the cross-domain crossing of multiple interrupt signal status information from the high-speed clock domain where the sampling circuit 10 is located to the low-speed clock domain where the storage circuit 20 is located, and lock it in the storage circuit 20 for analysis The device reads.

On the basis of any of the foregoing embodiments, the interruption status storage device may further include a processor; the processor is configured to access the storage circuit to obtain status information of the multiple interrupt signals. That is, the processor reads the status information of the multiple interrupt signals latched in the storage circuit 20 through the output port provided by the storage circuit 20, and then can analyze the status information of the multiple interrupt signals to obtain the information of the multiple interrupt signals. Priority.

In the interrupt information storage device provided in this embodiment, when the preset interrupt signal of the multiple interrupt signals changes through the sampling circuit 10, the sampling circuit 10 responds to the multiple interrupt signals according to the first clock signal with a relatively high frequency. The status information is sampled, and the status information of the multiple interrupt signals is sent to the storage circuit 20. The storage circuit 20 stores the status information of the multiple interrupt signals according to the relatively low-frequency second clock signal, so as to achieve When the preset interrupt signal changes, the status information of the multiple interrupt signals is latched, so as to analyze the sequence of each interrupt signal according to the status information of the multiple interrupt signals, improve the accuracy of the sequence acquisition of the interrupt signals, and avoid the interruption signal Risk of getting the wrong order.

Another embodiment of the present invention provides an interrupt information storage device. 2 is a structural diagram of interrupt information storage provided by another embodiment of the present invention; based on the technical solution provided by the embodiment shown in FIG. 1, the interrupt information storage device further includes a first enable signal generator 30, The first enable signal generator 30 is connected to the sampling circuit 10;

The first enable signal generator 30 is configured to receive the preset interrupt signal; when the preset interrupt signal has a state change, generate a first enable signal and send it to the sampling circuit 10;

The sampling circuit 10 is specifically configured to sample the status information of the multiple interrupt signals according to the first enable signal and the first clock signal.

In this embodiment, in order to realize that the sampling circuit 10 performs sampling and latching of the status information of the multiple interrupt signals only when the preset interrupt signal changes, the first user determines whether the preset interrupt signal changes. It can be realized by the signal generator 30. Specifically, by inputting the preset interrupt signal into the first enable signal generator 30, it is possible to determine whether the preset interrupt signal has changed according to the first enable signal generator 30, and when it is determined that the preset interrupt signal has changed At this time, the first enable signal is generated and sent to the sampling circuit 10, and the sampling circuit 10 samples the status information of the multiple interrupt signals according to the first enable signal and the first clock signal.

On the basis of the foregoing embodiment, the first enable signal generator 30 is configured to generate the first enable signal according to the transition edge of the preset interrupt signal.

In this embodiment, the transition of the preset interrupt signal is used as a sign of the change of the preset interrupt signal, and the first enable signal can generate the first enable signal according to the transition edge of the preset interrupt signal.

On the basis of the foregoing embodiment, as shown in FIG. 3, the first enable signal generator 30 may specifically include a first register 31, a first inverter 32, and a first AND circuit 33 connected in sequence;

The first register 31 is used to generate the preset interrupt signal after delay processing, and output the first delay signal to the first inverter 32;

The first inverter 32 is used to invert the first delay signal to generate a first inverted signal, and output to the first AND circuit 33 via the first inverted signal ；

The first AND circuit 33 is configured to receive the first reverse signal and the preset interrupt signal, perform a logical AND operation on the first reverse signal and the preset interrupt signal, and generate the The first enable signal, and the first enable signal is output to the sampling circuit 10.

In this embodiment, because the first register 31 delays the preset interrupt signal, when the preset interrupt signal transitions, for example, from 0→1, the output of the first register 31 is delayed due to the delay. The first delay signal has not yet become 1, so the first delay signal is 0 at this time. After being reversed by the first inverter 32, the first reverse signal is 1, and it is input to the first AND circuit 33 at this time. The signal includes: a preset interrupt signal and a first reverse signal, both of which are 1, so the first AND circuit 33 outputs 1 after performing a logical AND operation, that is, outputs the first enable signal.

On the basis of any of the foregoing embodiments, as shown in FIG. 3, the sampling circuit 10 includes a plurality of

first selectors

111, 112, 113 and a plurality of

second registers

121, 122, 123; A

selector

111, 112, 113 and a plurality of

second registers

121, 122, 123 are connected in a one-to-one correspondence, and the plurality of interrupt signals are input to the plurality of

first selectors

111, 112, 113 in a one-to-one correspondence; The first enable signal generator 30 is connected to the

first selectors

111, 112, and 113; in the following embodiments, only one set of corresponding first selectors and second registers is used for description, for example, the first selector 111 As with the second register 121, other corresponding first selectors and second registers have the same working principles.

The first selector 111 is configured to send the state information of the interrupt signal a to the second register 121 according to the first enable signal;

The second register 121 is used to receive the first clock signal, latch the state information of the interrupt signal a according to the first clock signal, and send the state information of the interrupt signal a to The storage circuit 20.

In this embodiment, when the first enable signal generator 30 outputs the first enable signal to each first selector 111, the first selector 111 responds to the first enable signal and responds to the input to the first selector 111 The interrupt signal 111 outputs the status information of the interrupt signal a to the second register 121, which is latched by the second register 121 and sent to the storage circuit 20.

The signal timing diagram of this embodiment can be seen in FIG. 4. When the interrupt signal a jumps, the state information of the interrupt signal b is 0, and the state information of the interrupt signal c is 1, through the

first selector

111, 112 and 113 sample the interrupt signals a, b, and c respectively, and obtain the status information of the interrupt signals a, b, and c as 101.

More specifically, the second register 121 is also used to send the state information currently stored in the second register 121 to the first selector 111;

The first selector 111 is also configured to select the state information of the interrupt signal a and the state information currently stored in the second register 121 according to the first enable signal, and output the interrupt signal Status information to the second register 121;

The second register 121 is also used to latch the state information of the interrupt signal according to the first clock signal.

In this embodiment, the first selector 111 is a one-of-two selector, and its two data input terminals respectively input an interrupt signal and the state information currently stored in the second register 121, and the first enable signal is input to the first selector After 111, the first selector 111 outputs the status information of the interrupt signal a to the second register 121; if the first selector 111 does not input the first enable signal, the first selector 111 selects the second register 121 to currently store The status information is output to the second register 121, that is, the data in the second register 121 has been kept unchanged, so that the first selector 111 after receiving the first enable signal, according to the first enable signal The status information of the interrupt signal a is sent to the second register 121 to change the status information currently stored in the second register 121.

On the basis of any of the foregoing embodiments, the interrupt information storage device further includes a plurality of interrupt signal registers 51, 52, 53, a plurality of the interrupt signal registers 51, 52, 53 and a plurality of the

first selectors

111, 112, 113 one-to-one correspondence connection;

The interrupt signal registers 51, 52, and 53 are used to receive the first clock signal and respectively output corresponding interrupt signals a, b, and c according to the first clock signal.

In this embodiment, multiple interrupt signals are provided by the interrupt signal register, and each interrupt signal register outputs an interrupt signal, and the interrupt signal in the interrupt signal register can be input into the interrupt signal register by one or more interrupt sources. Of course, if the interrupt source itself has an interrupt signal register, the interrupt information storage device of this embodiment may not set the interrupt signal register. It should be noted that the sampling circuit 10, the first enable signal generator 30 and the interrupt signal register can work under the same clock signal.

On the basis of any of the foregoing embodiments, as shown in FIG. 2, the interrupt information storage device may further include a second enable signal generator 40, and the second enable signal generator 40 and the storage circuit 20 connection;

The second enable signal generator 40 is configured to receive the preset interrupt signal; generate a second enable signal according to the preset interrupt signal, and send it to the storage circuit 20;

The storage circuit 20 is specifically configured to perform a storage operation on the state information of the multiple interrupt signals according to the second enable signal and the second clock signal.

In this embodiment, the storage circuit 20 needs to store the status information of the interrupt signal sent by the sampling circuit 10. Since the sampling circuit 10 and the storage circuit 20 are often connected, the sampling circuit 10 will continue to store the current information in the second register. The status information is sent to the storage circuit 20, and the storage circuit 20 is to latch the status information of each interrupt signal when the preset interrupt signal changes, so it is necessary to know the time when the preset interrupt signal changes. In this embodiment, the preset interrupt signal is input into the second enable signal generator 40, so that the second enable signal generator 40 determines the time when the preset interrupt signal changes according to the preset interrupt signal. After the change occurs, the second enable signal is generated, so that the storage circuit 20 stores the state information of the multiple interrupt signals according to the second enable signal and the second clock signal.

More specifically, the second enable signal generator 40 is used to:

The second enable signal is generated according to the transition edge of the preset interrupt signal.

In this embodiment, the transition of the preset interrupt signal is used as a sign of the change of the preset interrupt signal, and the second enable signal can generate the second enable signal according to the transition edge of the preset interrupt signal.

Further, the second enable signal generator 40 works under the second clock signal;

The second enable signal generator 40 is used for:

After the cross-clock domain operation is performed on the preset interrupt signal, the second enable signal is generated according to its transition edge.

In this embodiment, since the sampling circuit 10 works under the first clock signal and the storage circuit 20 works under the second clock signal, in order to enable the state information of the multiple interrupt signals sent by the sampling circuit 10 to be stored by the storage circuit 20 Receiving and storing are performed under the second clock signal, therefore the second enable signal generator 40 also needs to work in the same clock domain as the storage circuit 20, that is, the second enable signal generator 40 works under the second clock signal , And after performing the cross-clock domain operation on the preset interrupt signal, the transition edge of the preset interrupt signal after the cross-clock domain is determined, and the second enable signal is generated according to the transition edge.

On the basis of any of the foregoing embodiments, as shown in FIG. 3, the second enable signal generator 40 includes a third register 41, a fourth register 42, a second inverter 43, and a second and Gate circuit 44, and the third register 41 is also connected to the second AND gate circuit 44; wherein, the third register 41 and the fourth register 42 work in the second clock domain;

The third register 41 is used to perform a cross-clock domain operation on the preset interrupt signal, generate a first cross-domain signal, and output the first cross-domain signal to the fourth register 42 and the second Two AND gate circuit 44;

The fourth register 42 is used to generate a second delay signal after performing delay processing on the fourth register 42 and output the second delay signal to the second inverter 43;

The second inverter 43 is configured to invert the second delay signal to generate a second inverted signal, which is output to the second AND circuit 44 via the second inverted signal ；

The second AND circuit 44 is configured to receive the second inverted signal and the first cross-domain signal, and perform a logical AND operation on the second inverted signal and the first cross-domain signal to generate The second enable signal and output the second enable signal to the storage circuit 20.

In this embodiment, the third register 41 is used to implement the preset interrupt signal to cross clock domains, where the third register 41 can include more than two registers, and the preset interrupt signal is reduced by more than two tapping cross domains. The influence of metastability when crossing clock domains improves the stability of the preset interrupt signal (that is, the first cross-domain signal) after crossing domains.

In this embodiment, the functions of the fourth register 42, the second inverter 43, and the second AND circuit 44 are similar to those of the above-mentioned first register 31, the first inverter 32, and the first AND circuit 33. The specific , The fourth register 42 delays the first cross-domain signal. When the first cross-domain signal transitions, for example, from 0→1, the fourth register 42 has a second delay due to the delay. The signal has not changed to 1, so the second delay signal is 0 at this time. After being reversed by the second inverter 43, the second reverse signal is 1. At this time, the signal input to the second AND circuit 44 includes: The first cross-domain signal and the second inverted signal are both 1, so the second AND circuit 44 performs a logical AND operation and outputs 1, that is, outputs the second enable signal.

On the basis of any of the foregoing embodiments, as shown in FIG. 3, the storage circuit 20 includes a plurality of

second selectors

211, 212, 213 and a plurality of

fifth registers

221, 222, and 223; The two

selectors

211, 212, 213 and the plurality of

fifth registers

221, 222, 223 are connected in a one-to-one correspondence, and the state information of the plurality of interrupt signals sent by the sampling circuit 10 is input into the plurality of

second Selectors

211, 212, and 213; the second enable signal generator 40 is connected to the

second selectors

211, 212, and 213; in the following embodiments, only one set of the corresponding second selector and fifth The registers are described, for example, the second selector 211 and the fifth register 221, and other corresponding second selectors and the fifth register work in the same principle.

The second selector 211 is configured to send the state information of the interrupt signal to the fifth register 221 according to the second enable signal;

The fifth register 221 is configured to receive the second clock signal, and latch the state information of the interrupt signal a according to the second clock signal.

In this embodiment, when the second enable signal generator 40 outputs the second enable signal to the second selector 211, the second selector 211 responds to the second enable signal according to the input to the second selector 211 The interrupt signal is output to the fifth register 221 and the status information of the interrupt signal a is latched by the fifth register 221.

More specifically, the fifth register 221 is also used to send the status information currently stored in the fifth register 221 to the second selector 211;

The second selector 211 is further configured to select the status information of the interrupt signal a and the status information currently stored in the fifth register 221 according to the second enable signal, and output the interrupt State information of signal a to the fifth register 221;

The fifth register 221 is also used to latch the state information of the interrupt signal a according to the second clock signal.

In this embodiment, the second selector 211 is a one-of-two selector, and its two data input terminals respectively input the status information of the interrupt signal a sent by the sampling circuit 10 (that is, the interrupt signal sent by the second register 121). a) and the status information currently stored in the fifth register 221. After the second enable signal is input to the second selector 211, the second selector 211 outputs the status information of the interrupt signal a to the fifth register 221; If the second selector 211 does not input the second enable signal, the second selector 211 selects the state information currently stored in the fifth register 221 to output to the fifth register 221, that is, the data in the fifth register 221 remains unchanged. Thus, after receiving the second enable signal, the second selector 211 sends the status information of the interrupt signal a to the fifth register 221 according to the second enable signal, and changes the status information currently stored in the fifth register 221 .

The signal timing diagram of this embodiment can be seen in FIG. 4, the storage circuit can store the state information of the interrupt signal sent by the sampling circuit, and finally the state information of the interrupt signal a, b, c stored in the storage circuit is 101.

On the basis of the foregoing embodiment, the time when the

second selectors

211, 212, and 213 receive the status information of the interrupt signal sent by the sampling circuit 10 of the second register is earlier than that of the

second selector

211, 212, 213 time when the second enable signal is received.

In this embodiment, in order to prevent the sampling circuit 10 from transmitting the status information of the interrupt signal to the

second selectors

211, 212, 213 when the

second selectors

211, 212, and 213 receive the second enable signal, As a result, the

second selectors

211, 212, and 213 cannot send the status information of the interrupt signal to the

fifth registers

221, 222, and 223 according to the second enable signal, so that the storage circuit 20 cannot accurately store each preset interrupt signal when the interrupt signal changes. The status information of the interrupt signal. Therefore, this embodiment requires that the

second selectors

211, 212, 213 receive the status information of the interrupt signal sent by the sampling circuit 10 in the second register earlier than the

second selectors

211, 212, 213 The time when the second enable signal is received, that is, the state information that needs to interrupt the signal first reaches the

second selectors

211, 212, 213, and then the second enable signal reaches the

second selectors

211, 212, 213.

It should be noted that the interrupt information storage device shown in FIGS. 2 and 3 in the above embodiment only deals with the case where the preset interrupt signal is the interrupt signal a, the first enable signal generator 30 and the second enable signal generator 40 can only generate an enable signal when the state of the interrupt signal a changes. The sampling circuit 10 and the storage circuit 20 only sample and store the state information of the interrupt signals a, b, and c when the interrupt signal a changes state. The enable signal generator 30, the second enable signal generator 40, the sampling circuit 10, and the storage circuit 20 are not applicable to the situation where the interrupt signal b and the interrupt signal c undergo a state change. Therefore, if the preset interrupt signal is the interrupt signal b or c, a set of first enable signal generator, second enable signal generator, sampling circuit, and storage circuit need to be separately provided. That is, if you need to completely monitor the status information of each interrupt signal when the status of the three interrupt signals a, b, and c change, you need to set up three sets of the first enable signal generator, the second enable signal generator, and the sampling The circuit and the storage circuit respectively record the state information of each interrupt signal when the state of the interrupt signal a changes, the state information of each interrupt signal when the state of the interrupt signal b changes, and the state information of each interrupt signal when the state of the interrupt signal c changes. The specific working principles of the other two sets are the same as in the above-mentioned embodiment, and will not be repeated here.

The embodiment of the present invention provides a movable platform. FIG. 5 is a structural diagram of a movable platform provided by an embodiment of the present invention. As shown in FIG. 5, the movable platform 70 includes a sensor system 71, a power system 72, and an interruption state storage device 73 (as described in the above embodiment ), the sensor system 71 is used to collect status information and/or environmental information of the movable platform 70; the power system 72 is used to provide power for the movable platform 70;

The sensor system 71 and the power system 72 are also used to generate multiple interrupt signals and send them to the interrupt state storage device 73;

The interruption state storage device 73 includes a sampling circuit and a storage circuit connected to each other;

On the basis of the foregoing embodiment, the interruption state storage device 73 further includes a first enable signal generator, and the first enable signal generator is connected to the sampling circuit;

The first enable signal generator is configured to receive the preset interrupt signal; when the preset interrupt signal changes state, generate a first enable signal and send it to the sampling circuit;

The sampling circuit is specifically configured to sample the status information of the multiple interrupt signals according to the first enable signal and the first clock signal.

On the basis of any of the foregoing embodiments, the first enable signal generator is used for:

The first enable signal is generated according to the transition edge of the preset interrupt signal.

On the basis of any of the foregoing embodiments, the first enable signal generator includes a first register, a first inverter, and a first AND circuit connected in sequence;

The first register is used to generate a first delay signal after performing delay processing on the preset interrupt signal, and output the first delay signal to the first inverter;

The first inverter is used to invert the first delay signal to generate a first inverted signal, and output to the first AND circuit via the first inverted signal;

The first AND circuit is configured to receive the first reverse signal and the preset interrupt signal, perform a logical AND operation on the first reverse signal and the preset interrupt signal, and generate the first An enable signal, and output the first enable signal to the sampling circuit.

On the basis of any of the above embodiments, the sampling circuit includes multiple first selectors and multiple second registers; the multiple first selectors and multiple second registers are connected in a one-to-one correspondence, and the multiple One interrupt signal is inputted into the plurality of first selectors one by one; the first enable signal generator is connected to the first selector;

The first selector is configured to send the status information of the interrupt signal to the second register according to the first enable signal;

The second register is used to receive the first clock signal, latch the state information of the interrupt signal according to the first clock signal, and send the state information of the interrupt signal to the storage Circuit.

On the basis of any of the foregoing embodiments, the second register is also used to send the state information currently stored in the second register to the first selector;

The first selector is further configured to select the status information of the interrupt signal and the status information currently stored in the second register according to the first enable signal, and output the status information of the interrupt signal To the second register;

The second register is also used to latch the state information of the interrupt signal according to the first clock signal.

On the basis of any of the foregoing embodiments, the interrupt status storage device 73 further includes a plurality of interrupt signal registers, and the plurality of interrupt signal registers are connected to the plurality of first selectors in a one-to-one correspondence;

The interrupt signal register is used to receive the first clock signal and output a corresponding interrupt signal according to the first clock signal.

On the basis of any of the foregoing embodiments, the interrupt state storage device 73 further includes a second enable signal generator, and the second enable signal generator is connected to the storage circuit;

The second enable signal generator is configured to receive the preset interrupt signal; generate a second enable signal according to the preset interrupt signal, and send it to the storage circuit;

The storage circuit is specifically configured to store the state information of the multiple interrupt signals according to the second enable signal and the second clock signal.

On the basis of any of the foregoing embodiments, the second enable signal generator is used for:

On the basis of any of the foregoing embodiments, the second enable signal generator works under the second clock signal;

The second enable signal generator is used for:

On the basis of any of the foregoing embodiments, the second enable signal generator includes a third register, a fourth register, a second inverter, and a second AND circuit connected in sequence, and the third register is also Connected to the second AND circuit; wherein the third register and the fourth register work in the second clock domain;

The third register is used to perform cross-clock domain operations on the preset interrupt signal, generate a first cross-domain signal, and output the first cross-domain signal to the fourth register and the second AND Gate circuit

The fourth register is used to generate a second delay signal after performing delay processing on the fourth register, and output the second delay signal to the second inverter;

The second inverter is configured to invert the second delay signal to generate a second inverted signal, and output to the second AND circuit via the second inverted signal;

The second AND circuit is used to receive the second reverse signal and the first cross-domain signal, perform a logical AND operation on the second reverse signal and the first cross-domain signal, and generate the The second enable signal, and output the second enable signal to the storage circuit.

On the basis of any of the above embodiments, the storage circuit includes multiple second selectors and multiple fifth registers; the multiple second selectors and multiple fifth registers are connected in a one-to-one correspondence, and the sampling The state information of the multiple interrupt signals sent by the circuit is input into the multiple second selectors in a one-to-one correspondence;

The second enable signal generator is connected to the second selector;

The second selector is configured to send the status information of the interrupt signal to the fifth register according to the second enable signal;

The fifth register is used for receiving the second clock signal, and latching the state information of the interrupt signal according to the second clock signal.

On the basis of any of the foregoing embodiments, the fifth register is further configured to send the status information currently stored in the fifth register to the second selector;

The second selector is further configured to select the status information of the interrupt signal and the status information currently stored in the fifth register according to the second enable signal, and output the status of the interrupt signal Information to the fifth register;

The fifth register is also used to latch the state information of the interrupt signal according to the second clock signal.

On the basis of any of the foregoing embodiments, the time when the second selector receives the status information of the interrupt signal sent by the sampling circuit of the second register is earlier than when the second selector receives the second Time when the signal is enabled.

On the basis of any of the foregoing embodiments, the movable platform 70 further includes a processor 74;

The processor 74 is configured to access the storage circuit and obtain status information of the multiple interrupt signals.

On the basis of any of the foregoing embodiments, the movable platform 70 includes at least one of the following:

Unmanned aerial vehicles, remote control vehicles, robots.

The specific principles and implementation manners of the movable platform provided by the embodiment of the present invention are similar to the foregoing embodiment, and will not be repeated here.

In the mobile platform provided by the embodiment of the present invention, when the preset interrupt signal among the multiple interrupt signals generated by the sensor system and/or the power system changes, the sampling circuit in the interrupt state storage device is based on the relatively high frequency A clock signal samples the status information of the multiple interrupt signals, and sends the status information of the multiple interrupt signals to the storage circuit, and the storage circuit analyzes the status of the multiple interrupt signals according to the relatively low frequency second clock signal Information is stored, so that the status information of the multiple interrupt signals can be latched when the preset interrupt signal changes, so as to analyze the sequence of each interrupt signal according to the status information of the multiple interrupt signals, and improve the sequence acquisition of interrupt signals The accuracy of the signal is avoided to avoid the risk of obtaining the wrong sequence of interrupted signals.

In the several embodiments provided by the present invention, it should be understood that the disclosed device and method may be implemented in other ways. For example, the device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in the various embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware, or may be implemented in the form of hardware plus software functional units.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand: It is still possible to modify the technical solutions described in the foregoing embodiments, or equivalently replace some or all of the technical features; these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention range.

Claims

An interrupt information storage device, characterized in that it comprises a sampling circuit and a storage circuit connected to each other;

The sampling circuit is used to receive a plurality of interrupt signals and a first clock signal; when a preset interrupt signal in the plurality of interrupt signals changes, respond to the plurality of interrupt signals according to the first clock signal Sampling the status information of the multiple interrupt signals, and sending the status information of the multiple interrupt signals to the storage circuit;

The storage circuit is configured to receive a second clock signal; perform a storage operation on the state information of the multiple interrupt signals according to the second clock signal;

Wherein, the frequency of the first clock signal is greater than the frequency of the second clock signal.
The device according to claim 1, further comprising a first enabling signal generator, the first enabling signal generator being connected to the sampling circuit;

The first enable signal generator is configured to receive the preset interrupt signal; when the preset interrupt signal changes state, generate a first enable signal and send it to the sampling circuit;

The sampling circuit is specifically configured to sample the status information of the multiple interrupt signals according to the first enable signal and the first clock signal.
The device according to claim 2, wherein the first enable signal generator is used for:

The first enable signal is generated according to the transition edge of the preset interrupt signal.
The device according to claim 2 or 3, wherein the first enable signal generator comprises a first register, a first inverter, and a first AND circuit connected in sequence;

The first register is used to generate a first delay signal after performing delay processing on the preset interrupt signal, and output the first delay signal to the first inverter;

The first inverter is used to invert the first delay signal to generate a first inverted signal, and output to the first AND circuit via the first inverted signal;

The first AND circuit is configured to receive the first reverse signal and the preset interrupt signal, perform a logical AND operation on the first reverse signal and the preset interrupt signal, and generate the first An enable signal, and output the first enable signal to the sampling circuit.
The device according to any one of claims 2-4, wherein the sampling circuit comprises a plurality of first selectors and a plurality of second registers; the plurality of first selectors and a plurality of second registers One-to-one correspondence connection, the multiple interrupt signals are input to the multiple first selectors one-to-one correspondence; the first enable signal generator is connected to the first selector;

The first selector is configured to send the status information of the interrupt signal to the second register according to the first enable signal;

The second register is used to receive the first clock signal, latch the state information of the interrupt signal according to the first clock signal, and send the state information of the interrupt signal to the storage Circuit.
The device according to claim 5, wherein the second register is further configured to send the status information currently stored in the second register to the first selector;

The first selector is further configured to select the status information of the interrupt signal and the status information currently stored in the second register according to the first enable signal, and output the status information of the interrupt signal To the second register;

The second register is also used to latch the state information of the interrupt signal according to the first clock signal.
The device according to claim 5 or 6, further comprising a plurality of interrupt signal registers, and the plurality of interrupt signal registers and the plurality of first selectors are connected in a one-to-one correspondence;

The interrupt signal register is used to receive the first clock signal and output a corresponding interrupt signal according to the first clock signal.
7. The device according to any one of claims 1-7, further comprising a second enabling signal generator, the second enabling signal generator being connected to the storage circuit;

The second enable signal generator is configured to receive the preset interrupt signal; generate a second enable signal according to the preset interrupt signal, and send it to the storage circuit;

The storage circuit is specifically configured to store the state information of the multiple interrupt signals according to the second enable signal and the second clock signal.
The device according to claim 8, wherein the second enable signal generator is used for:

The second enable signal is generated according to the transition edge of the preset interrupt signal.
The device according to claim 9, wherein the second enable signal generator works under the second clock signal;

The second enable signal generator is used for:

After the cross-clock domain operation is performed on the preset interrupt signal, the second enable signal is generated according to its transition edge.
The device according to claim 10, wherein the second enable signal generator comprises a third register, a fourth register, a second inverter, and a second AND circuit connected in sequence, and the first The third register is also connected with the second AND circuit; wherein, the third register and the fourth register work in the second clock domain;

The third register is used to perform cross-clock domain operations on the preset interrupt signal, generate a first cross-domain signal, and output the first cross-domain signal to the fourth register and the second AND Gate circuit

The fourth register is used to generate a second delay signal after performing delay processing on the fourth register, and output the second delay signal to the second inverter;

The second inverter is configured to invert the second delay signal to generate a second inverted signal, and output to the second AND circuit via the second inverted signal;

The second AND circuit is used to receive the second reverse signal and the first cross-domain signal, perform a logical AND operation on the second reverse signal and the first cross-domain signal, and generate the The second enable signal, and output the second enable signal to the storage circuit.
The device according to any one of claims 8-11, wherein the storage circuit comprises a plurality of second selectors and a plurality of fifth registers; the plurality of second selectors and a plurality of fifth registers One-to-one correspondence connection, the state information of the multiple interrupt signals sent by the sampling circuit is input into the multiple second selectors one-to-one;

The second enable signal generator is connected to the second selector;

The second selector is configured to send the status information of the interrupt signal to the fifth register according to the second enable signal;

The fifth register is used for receiving the second clock signal, and latching the state information of the interrupt signal according to the second clock signal.
The device according to claim 12, wherein the fifth register is further configured to send state information currently stored in the fifth register to the second selector;

The second selector is further configured to select the status information of the interrupt signal and the status information currently stored in the fifth register according to the second enable signal, and output the status of the interrupt signal Information to the fifth register;

The fifth register is also used to latch the state information of the interrupt signal according to the second clock signal.
The device of claim 13, wherein:

The time when the second selector receives the state information of the interrupt signal sent by the sampling circuit of the second register is earlier than the time when the second selector receives the second enable signal.
The device according to any one of claims 1-14, further comprising a processor;

The processor is configured to access the storage circuit to obtain status information of the multiple interrupt signals.
A movable platform, characterized by comprising a sensor system, a power system, and the interrupt state storage device according to any one of claims 1-14, and the sensor system is used to collect state information of the movable platform And/or environmental information; the power system is used to provide power for the movable platform;

The sensor system and the power system are also used to generate a plurality of interrupt signals to send to the interrupt state storage device;

The interrupted state storage device includes a sampling circuit and a storage circuit connected to each other;

The sampling circuit is configured to receive the plurality of interrupt signals and a first clock signal; when a preset interrupt signal in the plurality of interrupt signals changes, according to the first clock signal, the plurality of Sampling the status information of the interrupt signal, and sending the status information of the multiple interrupt signals to the storage circuit;

The storage circuit is configured to receive a second clock signal; perform a storage operation on the state information of the multiple interrupt signals according to the second clock signal;

Wherein, the frequency of the first clock signal is greater than the frequency of the second clock signal.
The mobile platform according to claim 16, wherein the interrupt state storage device further comprises a first enable signal generator, and the first enable signal generator is connected to the sampling circuit;

The first enable signal generator is configured to receive the preset interrupt signal; when the preset interrupt signal changes state, generate a first enable signal and send it to the sampling circuit;

The sampling circuit is specifically configured to sample the status information of the multiple interrupt signals according to the first enable signal and the first clock signal.
The movable platform according to claim 17, wherein the first enabling signal generator is used for:

The first enable signal is generated according to the transition edge of the preset interrupt signal.
The movable platform according to claim 17 or 18, wherein the first enable signal generator comprises a first register, a first inverter, and a first AND circuit connected in sequence;

The first register is used to generate a first delay signal after performing delay processing on the preset interrupt signal, and output the first delay signal to the first inverter;

The first inverter is used to invert the first delay signal to generate a first inverted signal, and output to the first AND circuit via the first inverted signal;

The first AND circuit is configured to receive the first reverse signal and the preset interrupt signal, perform a logical AND operation on the first reverse signal and the preset interrupt signal, and generate the first An enable signal, and output the first enable signal to the sampling circuit.
The movable platform according to any one of claims 17-19, wherein the sampling circuit includes a plurality of first selectors and a plurality of second registers; the plurality of first selectors and a plurality of second registers; The two registers are connected in a one-to-one correspondence, the multiple interrupt signals are input to the multiple first selectors in a one-to-one correspondence; the first enable signal generator is connected to the first selector;

The first selector is configured to send the status information of the interrupt signal to the second register according to the first enable signal;

The second register is used to receive the first clock signal, latch the state information of the interrupt signal according to the first clock signal, and send the state information of the interrupt signal to the storage Circuit.
The movable platform according to claim 20, wherein the second register is also used to send the status information currently stored in the second register to the first selector;

The first selector is further configured to select the status information of the interrupt signal and the status information currently stored in the second register according to the first enable signal, and output the status information of the interrupt signal To the second register;

The second register is also used to latch the state information of the interrupt signal according to the first clock signal.
The mobile platform according to claim 20 or 21, wherein the interrupt state storage device further comprises a plurality of interrupt signal registers, and the plurality of interrupt signal registers correspond to the plurality of first selectors one to one connection;

The interrupt signal register is used to receive the first clock signal and output a corresponding interrupt signal according to the first clock signal.
The movable platform according to any one of claims 16-22, wherein the interruption state storage device further comprises a second enable signal generator, and the second enable signal generator and the storage circuit connection;

The second enable signal generator is configured to receive the preset interrupt signal; generate a second enable signal according to the preset interrupt signal, and send it to the storage circuit;

The storage circuit is specifically configured to store the state information of the multiple interrupt signals according to the second enable signal and the second clock signal.
The movable platform of claim 23, wherein the second enable signal generator is used for:

The second enable signal is generated according to the transition edge of the preset interrupt signal.
The movable platform of claim 24, wherein the second enable signal generator works under the second clock signal;

The second enable signal generator is used for:

After the cross-clock domain operation is performed on the preset interrupt signal, the second enable signal is generated according to its transition edge.
The movable platform of claim 25, wherein the second enable signal generator includes a third register, a fourth register, a second inverter, and a second AND circuit connected in sequence, and The third register is also connected to the second AND circuit; wherein, the third register and the fourth register work in the second clock domain;

The third register is used to perform cross-clock domain operations on the preset interrupt signal, generate a first cross-domain signal, and output the first cross-domain signal to the fourth register and the second AND Gate circuit

The fourth register is used to generate a second delay signal after performing delay processing on the fourth register, and output the second delay signal to the second inverter;

The second inverter is configured to invert the second delay signal to generate a second inverted signal, and output to the second AND circuit via the second inverted signal;

The second AND circuit is used to receive the second reverse signal and the first cross-domain signal, perform a logical AND operation on the second reverse signal and the first cross-domain signal, and generate the The second enable signal, and output the second enable signal to the storage circuit.
The movable platform according to any one of claims 23-26, wherein the storage circuit includes a plurality of second selectors and a plurality of fifth registers; the plurality of second selectors and a plurality of first Five registers are connected in one-to-one correspondence, and the state information of the multiple interrupt signals sent by the sampling circuit is input into the multiple second selectors in a one-to-one correspondence;

The second enable signal generator is connected to the second selector;

The second selector is configured to send the status information of the interrupt signal to the fifth register according to the second enable signal;

The fifth register is used for receiving the second clock signal, and latching the state information of the interrupt signal according to the second clock signal.
The movable platform according to claim 27, wherein the fifth register is further used to send the status information currently stored in the fifth register to the second selector;

The second selector is further configured to select the status information of the interrupt signal and the status information currently stored in the fifth register according to the second enable signal, and output the status of the interrupt signal Information to the fifth register;

The fifth register is also used to latch the state information of the interrupt signal according to the second clock signal.
The movable platform according to claim 28, wherein:

The time when the second selector receives the state information of the interrupt signal sent by the sampling circuit of the second register is earlier than the time when the second selector receives the second enable signal.
The movable platform according to any one of claims 16-29, wherein the movable platform further comprises a processor;

The processor is configured to access the storage circuit to obtain status information of the multiple interrupt signals.
The movable platform according to any one of claims 16-30, wherein the movable platform comprises at least one of the following:

Unmanned aerial vehicles, remote control vehicles, robots.
A method for storing interruption information is characterized in that it comprises the steps:

Receiving a plurality of interrupt signals and a first clock signal; when a preset interrupt signal of the plurality of interrupt signals changes, sampling the status information of the plurality of interrupt signals according to the first clock signal;

Receiving a second clock signal; storing the state information of the plurality of interrupt signals according to the second clock signal; wherein the frequency of the first clock signal is greater than the frequency of the second clock signal.