CN101276292A - Interrupt synthetic method and apparatus as well as modularization host computer system - Google Patents
Interrupt synthetic method and apparatus as well as modularization host computer system Download PDFInfo
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Abstract
The present invention provides an interruption synthesis method. Firstly, the interruption signal of each card module output is processed with wave-shaping, even if the interruption signal has been in an effective state, the effective part of the interruption signal after wave-shaped only retains the same limit length of the preestablished significant period; then the interruption signal after wave-shaped is processed with sampling, the interruption effective state obtained by sampling is recorded, CPU is informed to read recorded interruption effective state, since the effective part length of the interruption signal is limited, the times of sampling and recording the interruption effective states are limited, and CPU clears all the recorded interruption effective state after reading the record, so CPU can not continuously read the interruption effective state and process the interruption of the card module, avoiding the dead of the modularization host system, improving the credibility of the interruption synthesis. The invention also provides an interruption device, and a modularization host system.
Description
Technical field
The present invention relates to interrupt processing technology, particularly a kind of interruption synthetic method, a kind of interruption synthesizer and a kind of modularization host computer system.
Background technology
The modularization host computer system comprises central processing unit (CPU) and a plurality of card slots position, and the card slot position can peg graft and have the module card of various functions, thereby is convenient to the function expansion of modularization host computer system.
In order to realize the incident in the CPU real-time response module card, each module card is handled to the CPU request event by look-at-me, but because the interrupt pin of CPU is limited, can not be corresponding one by one with each module card, so be reported to CPU again after needing to synthesize from the look-at-me of each module card, the synthetic of look-at-me can be realized by programmable logic device (PLD).In the practical application, interrupt being divided into effective two kinds of edge triggering and level, in order to ensure not losing interruption, what generally adopt at present is the level effective means.
Fig. 1 is the existing structural representation that can realize the modularization host computer system of interrupting synthesizing.As shown in Figure 1, be the level effective means and effectively be example when being low level with 8 module cards, look-at-me, look-at-me 1～8 is respectively the look-at-me of module card 1～8 (not shown) output, and inputs to 8 input pins of programmable logic device (PLD) respectively.In Fig. 1, as comprise in the programmable logic device (PLD) of interrupting synthesizer interrupt status register and with door.
Look-at-me 1～8 inputs to interrupt status register, and each in this interrupt status register is respectively applied for the current level value of record look-at-me 1～8.Because whether different level values reflection look-at-me is effective, thereby whether effective, promptly whether reported interruption if can regard the interruption status that has write down 8 module cards in the interrupt status register as.
Look-at-me 1～8 also inputs to and door, like this, as long as a low level of interrupting effective status for expression is arranged in the look-at-me 1～8, then the signal that exports CPU to interrupt request (IRQ) pin of door just is low level, make that the IRQ pin is effective, promptly report interruption to read the interruption effective status that is write down with notice CPU to CPU.
As long as and that CPU detects IRQ is effective, then read the interruption status of 8 module cards that interrupt status register write down in the FPGA (Field Programmable Gate Array), from the module card that interrupts effective status, read interrupting information, and carry out events corresponding and handle.
In addition, as long as the level value of look-at-me 1～8 becomes the invalid high level of expression, then the interruption status of the corresponding module card that writes down in the interrupt status register also can become thereupon invalid; Simultaneously, the IRQ pin of programmable logic device (PLD) correspondingly also become invalid.
After this, programmable logic device (PLD) continues the look-at-me 1～8 from 8 module cards is synthesized, and reports to CPU in the manner described above once more when having look-at-me effective.
From as can be known shown in Figure 1, if the module card abnormal interruption is arranged, for example, the look-at-me of this module card output is in effective status always, then correspondingly, the IRQ pin of programmable logic device (PLD) is effectively with the interruption status that also writes down this module card in continuously effective, the interrupt status register always also, thereby makes CPU constantly read interrupt status register, also handle the interruption of this module card always, and then it is dead to cause the modularization host computer system to be hung.
As seen, the interruption synthesis mode in the existing modularization host computer system can't be avoided because the extension that the abnormal interruption of module card causes is dead, thereby makes that to interrupt the reliability of synthesizing not high.
Summary of the invention
In view of this, the invention provides a kind of interruption synthetic method, a kind of interruption synthesizer and a kind of modularization host computer system, can improve the reliability of modularization host computer system interrupting synthesizing.
A kind of interruption synthetic method provided by the invention is applied to comprise the modularization host computer system of central processor CPU and a plurality of module cards, and this method comprises:
Respectively the look-at-me of each module card output is carried out wave shaping, make after the wave shaping each look-at-me at every turn from invalid become effectively after, the length of its live part equates with default interruption effective period;
Respectively each look-at-me after the wave shaping is sampled continuously, the interruption effective status of the corresponding module card that the record sampling obtains, and notify described CPU to read the interruption effective status that is write down;
Default the reading of at every turn finishing after reading at described CPU empties all interruption effective statuses that write down in the cycle clearly.
Described look-at-me from invalid become effectively after, this method further comprises: the live part to this look-at-me postpones a system clock cycle, makes that the zero hour of this live part and system clock are synchronous.
Described look-at-me after the wave shaping is sampled continuously comprises: with described system clock is sampling clock, and the look-at-me after the wave shaping is sampled continuously.
CPU finish at every turn read after, empty before all that write down interrupt effective statuses, this method further comprises: will read system clock cycle of cycle delay clearly, and make that described to read clearly cycle and system clock synchronous.
Read clearly in the cycle described, this method further comprises: forbid the execution of described sampling.
Described interruption effective period and describedly read that the cycle is satisfied following condition clearly:
In the look-at-me after the wave shaping, length equals the described live part sampling of effective period and the interruption status of record of interrupting, if do not read by CPU before the cycle clearly described reading, then this live part still can be obtained by sampling once more after reading clearly the cycle described.
Described interruption is 4 described system clock cycles, describedly reads clearly that the cycle is 1 described system clock cycle effective period.
A kind of interruption synthesizer provided by the invention, be applied to comprise the modularization host computer system of central processor CPU and a plurality of module cards, and this device links to each other with a plurality of module cards with described CPU respectively, described interruption synthesizer comprises: wave shaping unit, state sampling unit, state storage unit, interruption report the unit, read control module clearly, wherein
Described wave shaping unit carries out wave shaping to the look-at-me of each module card output respectively, make after the wave shaping each look-at-me at every turn from invalid become effectively after, the length of its live part equates with default interruption effective period;
Described state sampling unit is sampled continuously to each look-at-me after the wave shaping respectively, and the interruption effective status of the corresponding module card that sampling is obtained is recorded in described state storage unit;
Described interruption reports the unit, records in described state storage unit when interrupting effective status, notifies the interruption effective status of described CPU reading and recording in described state storage unit;
The described control module clearly of reading is finished all interruption statuss that default after reading reads to empty in cycle clearly described state storage unit at described CPU at every turn.
Described wave shaping unit further described look-at-me from invalid become effectively after, the live part of this look-at-me is postponed a system clock cycle, makes the zero hour of this live part and system clock synchronous.
Described state sampling unit is a sampling clock with described system clock, and the look-at-me after the wave shaping is sampled continuously.
Described read clearly control module further described CPU finish at every turn read after, will read system clock cycle of cycle delay clearly, make that described to read clearly cycle and system clock synchronous.
The described control module of reading clearly further reads clearly to forbid in the cycle that described described state sampling unit carries out described sampling.
Described interruption effective period and describedly read that the cycle is satisfied following condition clearly: in the look-at-me after the wave shaping, length equals the described live part sampling of effective period and the interruption effective status of record of interrupting, if do not read by CPU before the cycle clearly described reading, then this live part still can be obtained by sampling once more after reading clearly the cycle described.
Described interruption is 4 described system clock cycles, describedly reads clearly that the cycle is 1 described system clock cycle effective period.
A kind of modularization host computer system provided by the invention comprises: central processor CPU, interruption synthesizer and a plurality of module card,
Described interruption synthesizer carries out wave shaping to the look-at-me of each module card output, make after the wave shaping look-at-me at every turn from invalid become effectively after, the length of its live part equates with default interruption effective period; Respectively each look-at-me after the wave shaping is sampled continuously, the interruption effective status of the corresponding module card that the record sampling obtains, and notify described CPU to read the interruption effective status that is write down; Default the reading of at every turn finishing after reading at described CPU empties all interruption effective statuses that write down in the cycle clearly.
Described interruption synthesizer further forbids carrying out described sampling in the cycle clearly described reading;
And described interruption effective period and describedly read that the cycle is satisfied following condition clearly: in the look-at-me after the wave shaping, length equals the described live part sampling of effective period and the interruption effective status of record of interrupting, if do not read by CPU before the cycle clearly described reading, then this live part still can be obtained by sampling once more after reading clearly the cycle described.
As seen from the above technical solution, the present invention carries out wave shaping to the look-at-me of each module card output earlier, like this, even if the module card abnormal interruption is arranged, causes the look-at-me of its output to be in effective status always, but through this look-at-me after the wave shaping from invalid become effectively after, its live part also only can keep the finite length that equates effective period with default interruption; Then, again sample interruption effective status that obtains and the interruption effective status of notifying the CPU reading and recording are sampled, write down to the look-at-me after the wave shaping, because the live part limited length of look-at-me, it also is limited that sampling and record interrupt the effective status number of times, and promptly can empty all interruption effective statuses that write down after the CPU reading and recording, thereby CPU can break and reads the interruption of interrupting effective status and can not handling this module card always, thereby can avoid the extension of modularization host computer system dead, improved and interrupted synthetic reliability.
Further, the present invention can also forbid the execution of sampling emptying in the cycle clearly of reading of record, and be set effective period and read that the cycle is satisfied following condition clearly: length in the look-at-me is equaled the live part sampling of described effective period and the interruption status of record, if do not read by CPU before the cycle clearly described reading, then this live part still can be obtained by sampling once more after reading clearly the cycle described.Like this, can also guarantee that the many newspapers of not meeting or not failed to report when reporting interruption yet, interrupt synthetic reliability thereby further improved.
Description of drawings
Fig. 1 is the existing structural representation that can realize the modularization host computer system of interrupting synthesizing.
Fig. 2 interrupts the exemplary process diagram of synthetic method for the embodiment of the invention.
Fig. 3 is the structural representation of modularization host computer system in the embodiment of the invention.
Fig. 4 is the look-at-me waveform synoptic diagram after wave shaping in the embodiment of the invention.
Fig. 5 reads the waveform synoptic diagram of control signal clearly in the embodiment of the invention.
Fig. 6 is the waveform synoptic diagram of different each look-at-me constantly in the embodiment of the invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
Fig. 2 interrupts the exemplary process diagram of synthetic method for the embodiment of the invention.As shown in Figure 2, this method is applied to comprise the modularization host computer system of CPU and a plurality of module cards, and this method comprises:
Step 201 is carried out wave shaping to the look-at-me of each module card output respectively, make after the wave shaping each look-at-me at every turn from invalid become effectively after, the length of its live part equates with default interruption effective period.
Specifically, in this step, can look-at-me from invalid become effectively after, with a system clock cycle in this look-at-me live part Postponement module host computer system, in order to realize the synchronous of look-at-me live part and this system clock, be starting point the zero hour with this interruption live part then, the part that equates with default interruption effective cycle length in the intercepting live part.
Specifically, in this step, can with the system clock sampling clock directly, the look-at-me after the wave shaping is sampled continuously.Certainly, the system clock after also can frequency multiplication is a sampling clock.
Specifically, in this step, can CPU finish at every turn read after, postpone earlier a system clock cycle, and then begin to read the cycle clearly.
In the practical application, in order to guarantee to read can not report more and fail to report interruption before and after the cycle clearly to CPU, this step can be in default execution of reading to forbid in cycle clearly sampling in the step 202, and guarantee effective period and read that the cycle is satisfied following condition clearly: in the look-at-me after the wave shaping, length equals to interrupt the live part sampling of effective period and the interruption status of record, if do not read by CPU before the cycle clearly reading, then this live part still can be obtained by sampling once more after reading clearly the cycle.
So far, this flow process finishes.
Need to prove that step 201 in the above-mentioned flow process and step 202 are the processing procedure of executed in real time.
By above-mentioned flow process as seen, the present invention carries out wave shaping to the look-at-me of each module card output earlier, like this, even if the module card abnormal interruption is arranged, causes the look-at-me of its output to be in effective status always, but through this look-at-me after the wave shaping from invalid become effectively after, its live part also only can keep the finite length that equates effective period with default interruption; Then, again sample interruption effective status that obtains and the interruption effective status of notifying the CPU reading and recording are sampled, write down to the look-at-me after the wave shaping, because the live part limited length of look-at-me, it also is limited that sampling and record interrupt the effective status number of times, and promptly can empty all interruption effective statuses that write down after the CPU reading and recording, thereby CPU can break and reads the interruption of interrupting effective status and can not handling this module card always, thereby can avoid the extension of modularization host computer system dead, improved and interrupted synthetic reliability.
In addition, in above-mentioned flow process, if in the cycle clearly of reading of step 203, forbid the execution of sampling in the step 202 and guarantee effective period and read that the cycle satisfies as the described condition of step 203 clearly, can also guarantee that the many newspapers of not meeting or not failed to report when reporting interruption yet, interrupt synthetic reliability thereby further improved.
In the practical application, the cycle of reading clearly just is meant reads the live part length of control signal clearly, for how to read forbidding that the execution of sampling can have multiple implementation in the cycle clearly.For example, can will read the enable signal as sampling of control signal clearly, sampling just can be carried out when reading clearly invalidating signal.Again for example, the operation that empties record in the cycle clearly of reading is set has the high priority sampling and then have lower priority, like this, just can't carry out sampling as long as carry out the operation that empties record.
Fig. 3 is the structural representation of modularization host computer system in the embodiment of the invention.As shown in Figure 3, this system comprises: CPU, interruption synthesizer, systematic clock generator and a plurality of module card (not shown).In Fig. 3, be that the level effective means is an example with 8 module cards, interrupt mode.
Wherein, interrupting synthesizer can be realized by programmable logic device (PLD), link to each other with a plurality of module cards with CPU respectively, comprising: wave shaping unit, state sampling unit, state storage unit, interruption report the unit, read control module clearly.
The wave shaping unit, respectively to the look-at-me 1～8 of each module card output, promptly look-at-me 1～8 is as shown in Figure 3 carried out wave shaping, make look-at-me 1～8 at every turn from invalid become effectively after, the length of its live part equates with default interruption effective period.
Preferably, the wave shaping unit look-at-me from invalid become effectively after, can be earlier the live part of this look-at-me be postponed a system clock cycle synchronous in order to the live part of realizing this look-at-me and system clock, be starting point the zero hour with this interruption live part then, intercept one section that equates with default interruption effective cycle length in the live part, to realize wave shaping to the look-at-me of each module card output.
In the practical application, realize by programmable logic device (PLD), thereby then can determine the function of multiple different concrete logical organization realization wave shaping unit by hardware programming language correspondingly if interrupt synthesizer.For example, the logical organization that includes two triggers can be set realize being used for synchronous delay, change trigger condition as strobe interrupt signal live part with the level of system clock and look-at-me; The logical organization that includes a counter and a trigger can also be set realize wave shaping, with counter to the count results of system clock trigger condition as intercepting look-at-me live part.
The state sampling unit is sampled continuously to the look-at-me after the wave shaping 1～8 respectively, and the interruption effective status of the corresponding module card that sampling is obtained is recorded in state storage unit.
Preferably, the state sampling unit can be sampling clock with the system clock directly, and the look-at-me after the wave shaping is sampled continuously; Certainly, the system clock after also can frequency multiplication is a sampling clock.
In the practical application, state storage unit still can realize by register, and its each be respectively applied for the interruption status of a module card of record, for example 1 expression is invalid, 0 expression effectively.
Interruption reports the unit, when state storage unit records the interruption effective status, reports interruption to notify the CPU reading and recording in the interruption effective status of state storage unit by the IRQ pin to CPU.
In the practical application,, then interrupt reporting the unit can be by realizing with door if effective when look-at-me is low level; If look-at-me is effective when being high level, then interrupt reporting the unit can by or door realize.
Read control module clearly, finish default after reading at CPU at every turn and read clearly in the cycle, all that empty state storage unit are interrupted effective statuses, be about to wherein the interruption status of each module card of record all be changed to invalid.
Preferably, CPU can read control module clearly finishing can notify after reading at every turn; Read clearly control module CPU finish at every turn read after, that earlier expression is read cycle clearly reads clearly that the live part of control signal postpones a system clock cycle, in order to realize reading the synchronous of cycle and system clock clearly.
In the practical application, realize by programmable logic device (PLD), thereby then can determine that multiple different concrete logical organization realization reads the function of control module clearly by hardware programming language correspondingly if interrupt synthesizer.For example, the logical organization that includes two triggers can be set realize being used for synchronous delay, change with system clock and the level of reading control signal clearly and read the trigger condition of control signal live part clearly as gating.
Like this, even if the module card abnormal interruption is arranged, causes the look-at-me of its output to be in effective status always, but through this look-at-me after the wave shaping from invalid become effectively after, its live part also only can keep the finite length that equates effective period with default interruption; Then, again sample interruption effective status that obtains and the interruption effective status of notifying the CPU reading and recording are sampled, write down to the look-at-me after the wave shaping, because the live part limited length of look-at-me, it also is limited that sampling and record interrupt the effective status number of times, and promptly can empty all interruption effective statuses that write down after the CPU reading and recording, thereby CPU can break and reads the interruption of interrupting effective status and can not handling this module card always, thereby can avoid the extension of modularization host computer system dead, improved and interrupted synthetic reliability.
In the above-mentioned modularization host computer system, guarantee if desired reading clearly can not report more and fail to report interruption before and after the cycle, then read clearly control module and can carry out sampling at the default illegal state sampling unit of reading clearly in the cycle to CPU.Meanwhile, also need effective period and read that the cycle is satisfied following condition clearly: in the look-at-me after the wave shaping, length equals the live part sampling of effective period and the interruption status of record, if do not read by CPU before the cycle clearly reading, then this live part still can be obtained by sampling once more after reading clearly the cycle.
Below, in conjunction with an instantiation, the course of work of the above-mentioned modularization host computer system in the present embodiment is further specified.
Suppose that be 4 system clock cycles, read clearly that the cycle is that 1 system clock cycle, look-at-me are that low level is effective effective period.
Fig. 4 is the look-at-me waveform synoptic diagram after wave shaping in the embodiment of the invention.As shown in Figure 4, the look-at-me of arbitrary module card output is after the time-delay that descends is carved into, in order to realize the synchronous of look-at-me and system clock, decline system clock cycle of delay (shown in the dotted portion among Fig. 4) with this look-at-me carries out wave shaping then earlier, and the live part of the look-at-me after wave shaping is 4 system clock cycles.If a system cycle that will be used to postpone is included, then the live part of the look-at-me after wave shaping also can be seen 5 system clock cycles as.
Like this, be that the look-at-me of sampling period after to wave shaping sampled with the system clock, can sample low level in the moment as shown in Figure 4 to shown in the upward arrow, promptly sample effective interruption status.
At this moment, can report interruption to CPU, and by CPU all interruption statuss according to the read control signal reading and recording.
Fig. 5 reads the waveform synoptic diagram of control signal clearly in the embodiment of the invention.As shown in Figure 5, the operating cycle that CPU reads, be the effective period of the read control signal of CPU, corresponding to this section of T1～Tn system clock cycle.In this section of T1～Tn system clock cycle, at the rising edge of each system clock (read control signal of CPU in this section of T1～Tn system clock cycle to the upward arrow place), the interruption status of record all can be read by CPU.But at rising edge clock Tn, the interruption status that CPU reads can cover its interruption status that is read at the Tn-1 rising edge, therefore, only consider that hereinafter Tn rising time-delay CPU reads interruption status, and T1～Tn-1 does not consider constantly.
Still referring to Fig. 5, read the back that finishes (i.e. read control signal rising is as shown in Figure 5 prolonged) at CPU, for realize reading control signal and system clock clearly synchronously, earlier the read control signal of CPU being risen postpones a system clock cycle (shown in the dotted portion among Fig. 5), and then produces reading control signal clearly and will reading clearly that control signal becomes effectively (promptly as shown in Figure 5 read the low level part of control signal clearly) and begin to read the cycle clearly of 1 system clock cycle.Then, read in cycle clearly the system clock rising edge (read control signal clearly corresponding Tn+2 rise prolong to the upward arrow place), empty all interruption statuss that write down, and forbidding sampling.
In the practical application, read that control module is exportable clearly reads control signal clearly, be and read the cycle clearly and read clearly the live part length of control signal.For how to read forbidding that the execution of sampling can have multiple implementation in the cycle clearly.
For example, can will read clearly control signal as the enable signal of state sampling unit, when reading clearly invalidating signal, the enabled state sampling unit is carried out sampling; When reading that signal is effective clearly, the state sampling unit is not enabled and can't carries out sampling.
Again for example, one normally closed on-off circuit can be set between wave shaping unit and state sampling unit, when reading that signal is effective clearly, this on-off circuit disconnects, and makes the state sampling unit because the look-at-me after can't receiving wave shaping and can't realize effective sampling.
Also for example, be provided with and read priority that control module clearly empties state storage unit and be higher than the state sampling unit and carry out sampling, like this, carry out the operation, the state sampling unit that empty record and just can't carry out sampling as long as read clearly control module.Wherein, because above-mentioned interruption synthesizer can be realized by programmable logic device (PLD), thereby the various operations of carrying out for above-mentioned each unit can be realized that the setting of priority then can utilize the syntactic property of " if ... else ... " statement in the hardware language to realize by hardware language.
Below, why the look-at-mes that produce 8 different moment at same module card can be avoided reporting more and failing to report interruption to above-mentioned modularization host computer system and be elaborated again.
Fig. 6 is the waveform synoptic diagram of different each look-at-me constantly in the embodiment of the invention.As shown in Figure 6, the read control signal of CPU and read control signal clearly, all after interrupting effective status and notifying CPU, produce at module card 0, the read control signal of CPU is at T[-(n-1)]～this section of T4 system clock cycle in effectively, n is positive integer, reads clearly control signal at T6 effectively constantly.
Below, in this section of T0～T10 system clock cycle, the look-at-me that produces under 8 kinds of situations at module card 1 describes respectively.
In Fig. 6, the look-at-me that module card 1 produces is through after the wave shaping, live part length is 5 system clock cycles, 1 system clock cycle that comprises 4 clock period being used for sampling (sampled point of 4 clock period for figure to the upward arrow place) and be used for postponing synchronously.And module card 1 is at the T0～T7 of the corresponding system clock of first sampled point difference of the live part correspondence of the look-at-me of the 1st～8 kind of situation generation.
1) for the look-at-me that produces the 1st kind of situation:
In this section of T0～T3 system clock cycle, the live part of this look-at-me that module card 1 produces is sampled, and the interruption effective status of the module card 1 that obtains of sampling is recorded; Simultaneously, owing to record the interruption effective status this moment, thereby the IRQ pin effectively and to CPU reports interruption.
At the T4 of system clock constantly, CPU reads the interruption effective status of the module card 1 that T3 writes down constantly, and the interruption effective status of the module card 0 that has write down is before also read for the last time by CPU.That is to say, length in the look-at-me of module card 1 is equaled to interrupt the live part sampling of effective period and the interruption effective status of record, read once by CPU before the cycle clearly reading.Need to prove that reading and hereinafter described once is meant at the read control signal of CPU in effective period here.
At the T6 of system clock constantly, remove all module cards of being write down, be the interruption effective status of module card 0 and module card 1, IRQ pin inactive and forbid sampling.
As seen, the once effective look-at-me that produces the 1st kind of situation for module card 1 can report once to CPU before the cycle clearly reading, and neither can interrupt also can not failing to report interruption by many newspapers.
2) for the look-at-me that produces the 2nd kind of situation:
In this section of T1～T3 system clock cycle, the live part of this look-at-me that module card 1 produces is sampled, and the interruption effective status of the module card 1 that obtains of sampling is recorded; Simultaneously, owing to record the interruption effective status this moment, thereby the IRQ pin effectively and to CPU reports interruption.
At the T4 of system clock constantly, CPU reads the interruption effective status of the module card 1 that T3 writes down constantly, and the interruption effective status of the module card 0 that has write down is before also read for the last time by CPU.Though the live part of this look-at-me that module card 1 produces is sampled at T4 constantly once more, but because the transmission delay characteristic of programmable logic device (PLD), sample the constantly interruption effective status of the module card 1 that obtains of T4 can be read at T5 constantly, and that the read control signal of CPU has constantly become at T5 is invalid, thereby sample the constantly interruption effective status of the module card 1 that obtains of T4 can not read by CPU before the cycle clearly once more reading.That is to say, length in the look-at-me of module card 1 is equaled to interrupt the live part sampling of effective period and the interruption effective status of record, read once by CPU before the cycle clearly reading.
At the T6 of system clock constantly, remove all module cards of being write down, be the interruption effective status of module card 0 and module card 1, IRQ pin inactive and forbid sampling.
As seen, the once effective look-at-me that produces the 2nd kind of situation for this module card 1 can report once to CPU before the cycle clearly reading, and neither can interrupt also can not failing to report interruption by many newspapers.
3) for the look-at-me that produces the 3rd kind of situation:
In this section of T2～T3 system clock cycle, the live part of this look-at-me that module card 1 produces is sampled, and the interruption effective status of the module card 1 that obtains of sampling is recorded; Simultaneously, owing to record the interruption effective status this moment, thereby the IRQ pin effectively and to CPU reports interruption.
At the T4 of system clock constantly, CPU reads the interruption effective status of the module card 1 that T3 writes down constantly, and the interruption effective status of the module card 0 that has write down is before also read for the last time by CPU.Though the live part of this look-at-me that module card 1 produces is sampled at T4 and T5 constantly once more, but because the transmission delay characteristic of programmable logic device (PLD), sample the constantly interruption effective status of the module card 1 that obtains of T4 and T5, constantly can be read at T5 and T6 respectively, and that the read control signal of CPU has become at T5 and T6 constantly is invalid, thereby sample the constantly interruption effective status of the module card 1 that obtains of T4 and T5 can not read by CPU before the cycle clearly once more reading.That is to say, length in the look-at-me of module card 1 is equaled to interrupt the live part sampling of effective period and the interruption effective status of record, read once by CPU before the cycle clearly reading.
At the T6 of system clock constantly, remove all module cards of being write down, be the interruption effective status of module card 0 and module card 1, IRQ pin inactive and forbid sampling.
As seen, the once effective look-at-me that produces the 3rd kind of situation for this module card 1 can report once to CPU before the cycle clearly reading, and neither can interrupt also can not failing to report interruption by many newspapers.
4) for the look-at-me that produces the 4th kind of situation:
At system clock T3 constantly, the live part of this look-at-me that module card 1 produces is sampled, and the interruption effective status of the module card 1 that obtains of sampling is recorded; Simultaneously, owing to record the interruption effective status this moment, thereby the IRQ pin effectively and to CPU reports interruption.
At the T4 of system clock constantly, CPU reads the interruption effective status of the module card 1 that T3 writes down constantly, and the interruption effective status of the module card 0 that has write down is before also read for the last time by CPU.Though the live part of this look-at-me that module card 1 produces is sampled at T4 and T5 constantly once more, but because the transmission delay characteristic of programmable logic device (PLD), sample the constantly interruption effective status of the module card 1 that obtains of T4 and T5, constantly can be read at T5 and T6 respectively, and that the read control signal of CPU has become at T5 and T6 constantly is invalid, thereby sample the constantly interruption effective status of the module card 1 that obtains of T4 and T5 can not read by CPU before the cycle clearly once more reading.That is to say, length in the look-at-me of module card 1 is equaled to interrupt the live part sampling of effective period and the interruption effective status of record, read once by CPU before the cycle clearly reading.
At the T6 of system clock constantly, remove all module cards of being write down, be the interruption effective status of module card 0 and module card 1, IRQ pin inactive and forbid sampling.
As seen, the once effective look-at-me that produces the 4th kind of situation for this module card 1 can report once to CPU before the cycle clearly reading, thereby can not fail to report interruption; And, though this look-at-me in T6 constantly, promptly reads clearly the cycle still for effectively, but owing to read not sample in the cycle clearly (referring to have among the figure " x " pattern to upward arrow), thereby, interrupt thereby do not understand many newspapers in that read clearly in the cycle not can the same interruption effective status of duplicate record.
5) for the look-at-me that produces the 5th kind of situation:
In the T4 and the T5 moment, though the live part of this look-at-me that module card 1 produces is sampled, but because the transmission delay characteristic of programmable logic device (PLD), sample the constantly interruption effective status of the module card 1 that obtains of T4 and T5, constantly can be read at T5 and T6 respectively, and that the read control signal of CPU has become at T5 and T6 constantly is invalid, thereby is reading can not read by CPU before the cycle clearly at sample the constantly interruption effective status of the module card 1 that obtains of T4 and T5, the interruption effective status of the module card 0 that has write down before to be CPU only can read before reading cycle clearly.That is to say, length in the look-at-me of module card 1 is equaled to interrupt the live part sampling of effective period and the interruption effective status of record, do not read before the cycle clearly reading by CPU.
In the T6 of system clock constantly, promptly reads clearly the cycle, remove all module cards of being write down, be the interruption effective status of module card 0, IRQ pin inactive and forbid sampling.
At the T7 of system clock constantly, the live part of this look-at-me that module card 1 produces is sampled, and the interruption effective status of the module card 1 that obtains of sampling is recorded; Simultaneously, owing to record the interruption effective status this moment, thereby the IRQ pin is effective and report interruption to CPU, afterwards, can waiting for CPU read.That is to say that length equals to interrupt the live part sampling of effective period and the interruption status of record in the look-at-me that module card 1 is produced, do not read before the cycle clearly reading, obtained but after reading clearly the cycle, can sample once more by CPU.
As seen, the once effective look-at-me that produces the 5th kind of situation for this module card 1 can report once to CPU after the cycle clearly reading, thereby can not fail to report interruption; And, though this look-at-me is in this section of T4～T5 system clock cycle and read clearly in the cycle effectively, but since in this section of T4～T5 system clock cycle effective interruption status of sampling and record do not read and read not sample in the cycle clearly by CPU (referring to have among the figure " x " pattern to upward arrow), thereby do not understand many newspapers and interrupt.
6) for the look-at-me that produces the 6th kind of situation:
In the T5 moment of system clock, though the live part of this look-at-me that module card 1 produces is sampled, but because the transmission delay characteristic of programmable logic device (PLD), sample the constantly interruption effective status of the module card 1 that obtains of T5 can be read at T6 constantly, and that the read control signal of CPU has become at T5 and T6 constantly is invalid, thereby sample the constantly interruption effective status of the module card 1 that obtains of T5 can not read by CPU before the cycle clearly reading, i.e. the interruption effective status of the module card 0 that write down before only can reading before reading cycle clearly of CPU.That is to say, length in the look-at-me of module card 1 is equaled to interrupt the live part sampling of effective period and the interruption effective status of record, do not read before the cycle clearly reading by CPU.
In the T6 of system clock constantly, promptly reads clearly the cycle, remove all module cards of being write down, be the interruption effective status of module card 0 and module card 1, IRQ pin inactive and forbid sampling.
At T7 and T8 constantly, the live part of this look-at-me that module card 1 produces is sampled, and the interruption effective status of the module card 1 that obtains of sampling is recorded; Simultaneously, owing to record the interruption effective status this moment, thereby the IRQ pin is effective and report interruption to CPU, afterwards, can waiting for CPU read.That is to say that length equals to interrupt the live part sampling of effective period and the interruption status of record in the look-at-me that module card 1 is produced, do not read before the cycle clearly reading, obtained but after reading clearly the cycle, can sample once more by CPU.
As seen, the once effective look-at-me that produces the 6th kind of situation for this module card 1 can report once to CPU after the cycle clearly reading, thereby can not fail to report interruption; And, though this look-at-me at system clock T5 constantly and read clearly in the cycle effectively, but because system clock T5 samples constantly and effective interruption status of writing down is not read and read by CPU not sample in the cycle clearly (referring to have among the figure " x " pattern to upward arrow), thereby do not understand many newspapers and interrupt.
7) for the look-at-me that produces the 7th kind of situation:
In the T6 of system clock constantly, promptly reads clearly the cycle, remove all module cards of being write down, be the interruption effective status of module card 0, IRQ pin inactive and forbid sampling.
At T7, T8 and T9 constantly, the live part of this look-at-me is by continuous sampling, and the interruption effective status of the module card 1 that obtains of sampling is recorded; Simultaneously, owing to record the interruption effective status this moment, thereby the IRQ pin is effective and report interruption to CPU, afterwards, can waiting for CPU read.That is to say that length equals to interrupt the live part sampling of effective period and the interruption effective status of record in the look-at-me that module card 1 is produced, do not read before the cycle clearly reading, obtained but after reading clearly the cycle, can sample once more by CPU.
As seen, the once effective look-at-me that produces the 7th kind of situation for this module card 1 can report once to CPU after the cycle clearly reading, thereby can not fail to report interruption; And, though this look-at-me reading clearly in the cycle effectively owing to read not sample in the cycle clearly (referring to have among the figure " x " pattern to upward arrow), thereby do not understand many newspapers and interrupt.
8) for the look-at-me that produces in the 8th moment:
In the T6 of system clock constantly, promptly reads clearly the cycle, remove all module cards of being write down, be the interruption effective status of module card 0, IRQ pin inactive and forbid sampling.
At T7～T10 constantly, the live part of this look-at-me that module card 1 produces is by continuous sampling, and the interruption effective status of the module card 1 that obtains of sampling is recorded; Simultaneously, owing to record the interruption effective status this moment, thereby the IRQ pin is effective and report interruption to CPU, afterwards, can waiting for CPU read.That is to say that length equals to interrupt the live part sampling of effective period and the interruption effective status of record in the look-at-me that module card 1 is produced, do not read before the cycle clearly reading, obtained but after reading clearly the cycle, can sample once more by CPU.
As seen, the once effective look-at-me that produces the 8th kind of situation for this module card 1 can report once to CPU after the cycle clearly reading, thereby can not fail to report interruption; And, this look-at-me read clearly in the cycle and before invalid, thereby do not understand many newspapers and interrupt.
As seen from the above-described embodiment, the present invention has avoided the CPU that causes owing to abnormal interruption to hang extremely by the wave shaping to look-at-me, has improved and has interrupted synthetic reliability.And the present invention can also be by the reliability of reading in cycle clearly the forbidding and read clearly that the condition restriction of cycle and look-at-me effective period guarantees seldom to report and fail to report interruption of sampling, further improving to interrupt to synthesize.
Though all be to be example with the effective interrupt mode of level in the foregoing description, based on identical principle, the scheme that the foregoing description provided also is applicable to simultaneously along interrupt mode that triggers and level effectively with along triggering mixes interrupt mode.
In the practical application, the waveform of look-at-me may there are differences, but can be according to scheme that the foregoing description provided and flexible.
In order to guarantee seldom to report and fail to report interruption, need the effective period of look-at-me and be no less than 5 system clock cycles.If look-at-me does not satisfy this condition, then can carry out respective handling to it, for example:
1, comes the effective cycle length of configure interrupt signal by the register of hardware inside;
2, under the prerequisite of duration greater than 1 system clock cycle of any level state of look-at-me, the level state of look-at-me is prolonged processing.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (16)
1, a kind of interruption synthetic method is applied to comprise the modularization host computer system of central processor CPU and a plurality of module cards it is characterized in that this method comprises:
Respectively the look-at-me of each module card output is carried out wave shaping, make after the wave shaping each look-at-me at every turn from invalid become effectively after, the length of its live part equates with default interruption effective period;
Respectively each look-at-me after the wave shaping is sampled continuously, the interruption effective status of the corresponding module card that the record sampling obtains, and notify described CPU to read the interruption effective status that is write down;
Default the reading of at every turn finishing after reading at described CPU empties all interruption effective statuses that write down in the cycle clearly.
2, the method for claim 1, it is characterized in that, described look-at-me from invalid become effectively after, this method further comprises: the live part to this look-at-me postpones a system clock cycle, makes that the zero hour of this live part and system clock are synchronous.
3, method as claimed in claim 2 is characterized in that, described look-at-me after the wave shaping is sampled continuously comprises: with described system clock is sampling clock, and the look-at-me after the wave shaping is sampled continuously.
4, as any described method in the claim 1 to 3, it is characterized in that, CPU finish at every turn read after, empty before all that write down interrupt effective statuses, this method further comprises: will read system clock cycle of cycle delay clearly, and make that described to read clearly cycle and system clock synchronous.
5, method as claimed in claim 4 is characterized in that, reads clearly in the cycle described, and this method further comprises: forbid the execution of described sampling.
6, method as claimed in claim 5 is characterized in that, described interruption effective period and describedly read that the cycle is satisfied following condition clearly:
In the look-at-me after the wave shaping, length equals the described live part sampling of effective period and the interruption status of record of interrupting, if do not read by CPU before the cycle clearly described reading, then this live part still can be obtained by sampling once more after reading clearly the cycle described.
7, method as claimed in claim 6 is characterized in that, described interruption is 4 described system clock cycles, describedly reads clearly that the cycle is 1 described system clock cycle effective period.
8, a kind of interruption synthesizer is applied to comprise the modularization host computer system of central processor CPU and a plurality of module cards, and this device links to each other with a plurality of module cards with described CPU respectively,
It is characterized in that described interruption synthesizer comprises: wave shaping unit, state sampling unit, state storage unit, interruption report the unit, read control module clearly, wherein,
Described wave shaping unit carries out wave shaping to the look-at-me of each module card output respectively, make after the wave shaping each look-at-me at every turn from invalid become effectively after, the length of its live part equates with default interruption effective period;
Described state sampling unit is sampled continuously to each look-at-me after the wave shaping respectively, and the interruption effective status of the corresponding module card that sampling is obtained is recorded in described state storage unit;
Described interruption reports the unit, records in described state storage unit when interrupting effective status, notifies the interruption effective status of described CPU reading and recording in described state storage unit;
The described control module clearly of reading is finished all interruption statuss that default after reading reads to empty in cycle clearly described state storage unit at described CPU at every turn.
9, device as claimed in claim 8, it is characterized in that, described wave shaping unit further described look-at-me from invalid become effectively after, the live part of this look-at-me is postponed a system clock cycle, makes the zero hour of this live part and system clock synchronous.
10, device as claimed in claim 9 is characterized in that, described state sampling unit is a sampling clock with described system clock, and the look-at-me after the wave shaping is sampled continuously.
11, as any described device in the claim 8 to 10, it is characterized in that, described read clearly control module further described CPU finish at every turn read after, will read system clock cycle of cycle delay clearly, make that described to read clearly cycle and system clock synchronous.
12, device as claimed in claim 11 is characterized in that, the described control module of reading clearly further reads clearly to forbid in the cycle that described described state sampling unit carries out described sampling.
13, device as claimed in claim 12, it is characterized in that, described interruption effective period and describedly read that the cycle is satisfied following condition clearly: in the look-at-me after the wave shaping, length equals the described live part sampling of effective period and the interruption effective status of record of interrupting, if do not read by CPU before the cycle clearly described reading, then this live part still can be obtained by sampling once more after reading clearly the cycle described.
14, device as claimed in claim 13 is characterized in that, described interruption is 4 described system clock cycles, describedly reads clearly that the cycle is 1 described system clock cycle effective period.
15, a kind of modularization host computer system comprises: central processor CPU, interruption synthesizer and a plurality of module card,
It is characterized in that,
Described interruption synthesizer carries out wave shaping to the look-at-me of each module card output, make after the wave shaping look-at-me at every turn from invalid become effectively after, the length of its live part equates with default interruption effective period; Respectively each look-at-me after the wave shaping is sampled continuously, the interruption effective status of the corresponding module card that the record sampling obtains, and notify described CPU to read the interruption effective status that is write down; Default the reading of at every turn finishing after reading at described CPU empties all interruption effective statuses that write down in the cycle clearly.
16, system as claimed in claim 15 is characterized in that, described interruption synthesizer further forbids carrying out described sampling in the cycle clearly described reading;
And described interruption effective period and describedly read that the cycle is satisfied following condition clearly: in the look-at-me after the wave shaping, length equals the described live part sampling of effective period and the interruption effective status of record of interrupting, if do not read by CPU before the cycle clearly described reading, then this live part still can be obtained by sampling once more after reading clearly the cycle described.
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| CN1310146C (en) * | 2004-02-09 | 2007-04-11 | 中兴通讯股份有限公司 | Modular implement method for operating system of single-chip microcomputer |
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| WO2020258200A1 (en) * | 2019-06-28 | 2020-12-30 | 深圳市大疆创新科技有限公司 | Interrupt information storage device and removable platform |
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