KR100386601B1 - Apparatus for interrupt generation - Google Patents

Abstract

The present invention relates to an interrupt generating apparatus, comprising: a digital signal processor using a built-in timer for generating an interrupt indication signal by receiving the same reference clock and the same count clock, and an interrupt handler for generating an interrupt signal by the interrupt indication signal. And a host processing the digital signal processor and data by the interrupt signal output from the interrupt handler, and generating an interrupt in sequence using a timer of each digital signal processor. There is an effect to free up system space.

Description

Interrupt Generation Device {APPARATUS FOR INTERRUPT GENERATION}

The present invention relates to interrupts, and more particularly, to an interrupt generator using a built-in timer of a digital signal processor (DSP).

In general, it means sending a signal to the CPU to suspend a running program and inserting another program to execute.

When a condition that causes such an interruption occurs, the program being executed is interrupted and the control is forcibly transferred to a specific address, the prepared interrupt processing program is executed, and when the processing is completed, the program returns to the original program and continues to run.

The above interrupt processing means that the CPU (or host) does not need to waste time checking whether the input / output (I / O) device is in a ready state, and an interrupt operation requires several input / outputs (I) that require asynchronous service. / O) This is very useful when the device is connected to a CPU.

In this way, interrupts can improve the efficiency of program processing and simultaneous operation online processing of input / output devices.

To generate such an interrupt, a commercial timer is usually used.

Hereinafter, an interrupt generating apparatus using a commercial timer of the related art will be described with reference to the accompanying drawings.

1 is a view showing an interrupt generating device using a commercial timer of the prior art.

As shown in FIG. 1, an interrupt generator according to the related art includes a host 1, a digital signal processor 2 connected to the host 1 to read and write data, and a reference clock. It is composed of a receiving timer (3) and an interrupt handler (4) for receiving a timer tick of the timer (3) and generating an interrupt in sequence.

In the conventional interrupt generation apparatus configured as described above, when the data to be interfaced is voice data, the interface between the digital signal processor 2 and the host 1 should be guaranteed in real time. The same interrupt must be generated for a certain time to guarantee real time.

In addition, by using a reference clock (Timer) (3) to drive the interrupt for a certain time.

There is a method of driving the timer using a commercial timer chip or a field programmable gate array (FPGA) logic.

As described above, in the prior art, when the data of the digital signal processor 2 and the host 1 is voice data, the interface is an FPGA that functions as a commercial timer chip or timer with the digital signal processor 2 and the host 1. Contains logic.

When the timer chip or the FPGA logic is used to generate an interrupt every predetermined time to notify the host 1, the host 1 reads or writes data from the digital signal processor 2 from this point onward, and then interrupts. Will process the next data, so the software operation must be completed before the next interrupt.

The interrupt generated as described above is used for real-time data interface.

However, the interrupt generator of the prior art is inefficient due to insufficient space of the system when using a commercial timer, and the cost burden is large depending on the number of FPGA logic used when using the FPGA logic.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an interrupt generator suitable for generating an interrupt using a built-in timer of a plurality of digital signal processors receiving the same reference clock and the same counter clock. .

An interrupt generating apparatus according to the present invention for achieving the above object is a digital signal processor using a built-in timer to generate an interrupt instruction signal by receiving the same reference clock and the same count clock, and an interrupt signal by the interrupt instruction signal And an interrupt handler for generating a digital signal processor and a host for processing data by the interrupt signal output from the interrupt handler.

1 is a diagram illustrating an interrupt generator using a conventional commercial timer (or FPGA).

2 is a diagram illustrating an interrupt generator using a timer of a DSP according to an exemplary embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

11: Host 12: Digital Signal Processor (DSP)

13: interrupt handler

Hereinafter, an interrupt generating apparatus according to an embodiment of the present invention will be described.

2 is a diagram illustrating an interrupt generator according to an exemplary embodiment of the present invention.

That is, the interrupt generating apparatus according to the embodiment of the present invention receives a digital signal processor 12 that uses a built-in timer to generate an interrupt instruction signal by receiving the same reference clock and the same count clock, and an interrupt signal by the interrupt instruction signal. An interrupt handler 13 to generate, and the digital signal processor 12 and the host 11 to process data by the interrupt signal output from the interrupt handler.

The interrupt generation of the interrupt generating apparatus according to the embodiment of the present invention configured as described above will be described in detail as follows.

First, when the interface between the digital signal processor 12 and the host 11 is voice data, an interrupt instruction signal according to priority is generated using the built-in timer of the digital signal processor 12.

A plurality of such digital signal processors 12 are provided so that the digital signal processors 12 are supplied with the same reference clock and the same counter clock.

Each digital signal processor 12 then drives each timer based on the reference clock in the order it is to be used.

Subsequently, the interrupt handler 13 generates interrupt signals in sequence by driving the timer, and such interrupt signals sequentially process data with the host 11.

In this way, the same reference clock and the same counter clock are supplied to the general signal input / output ports (I / O ports) of the digital signal processor 12 to the plurality of digital signal processors 12.

Each digital signal processor 12 drives timers and counters based on a reference clock in order of priority to generate an interrupt instruction signal using a general input / output port.

At this time, the number to be countered by each of the digital signal processors 12 is different for each channel capacity.

In this way, the interrupt signal is generated using the timer of the digital signal processor 12. Since the data is negative, a signal of 20 ms per channel must be generated. Therefore, the reference clock is 50 Hz and the count clock is 8 kHz. do.

Since the general voice channel is 16 channels per board, the number of counts can be described by using the equation. Since 20ms = 0.125ms × 16 × n, n = 10, 8kHz must be counted 10 times to generate one interrupt signal. 16 interrupt signals can be used within the same time.

Here, 0.125ms means a period for the count clock of 8kHz.

That is, 16 interrupt signals are required at the transmitting end (Tx) and the receiving end (Rx). The first channel generates a counter interrupt signal after counting the counter clock 10 times, and generates a receiving end interrupt signal by counting 20 times.

If there are 20 channels and the reference clock is the same at 50Hz, the counter clock is counted five times and then an interrupt signal is sequentially generated.

Then, when the interrupt handler 13 has control as a result of the interrupt generation, it is checked whether the interrupt is generated by reading the contents of the status register of the digital signal processor 12.

If the interrupt instruction signal is generated by the timer of the digital signal processor 12, the interrupt handler 13 processes the interrupt signal and writes an interrupt to the host 11.

Then prepare the interrupt hardware again and write to a certain address.

The above-described interrupt generating apparatus according to the present invention generates an interrupt using a system timer and a counter of a digital signal processor without having to separately provide hardware for generating an interrupt signal, and thus is more efficient in terms of space and operating cost of the system. to be.

Claims (2)

A digital signal processor using a built-in timer to receive the same reference clock and the same count clock and generate an interrupt indication signal, An interrupt handler for generating an interrupt signal by the interrupt indication signal; And a host processing the digital signal processor and data by the interrupt signal output from the interrupt handler. The method of claim 1, And the number of digital signal processors increases as the number of channels increases.