JPH02127787A - External ready circuit - Google Patents

Abstract

PURPOSE:To control a machine cycle by dividing a clock pulse with a counter, defining the divided clock pulse as a system clock and stopping the counter. CONSTITUTION:The invert of WAIT signal line is connected to enable terminals P and T of a counter 2 and a clock pulse CP (24MHz, for example) is added to a clock terminal CP. Then, pulse width is double divided and the system clock of 12MHz is outputted from an output QA and given to a CPU 1. When the inverse of WAIT signal goes to be 'L', the system clock of 12MHz is stopped and when the inverse of WAIT signal goes to be 'H', the system clock is operated. Accordingly, this operation goes to be the same as ready control. Thus, the ready control of the CPU (DSP) 1 can be executed by a simple external circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applicable to a macro computer system, for example, where there is a lack of access time for memory and input/output (110) circuits, and when multiple CPUs (central Waiting time (WAIT) for the CPU due to simultaneous access by processing circuits)
Although the need to apply multiple CPUs frequently changes, some CPUs do not take these matters into consideration. Therefore, the present invention relates to a ready circuit provided outside the CPU that appropriately processes the clock pulse (CP) to such a CPU.

[Conventional technology]

Conventionally, as this type of device, for example, 80C51 [C-M2S version of Intel's 8051...product name...] and T
MS320C25 [manufactured by Texas Instruments Co., Ltd.]
...Product name: This is a 1-chip DSP (digital signal processing processor) with further improved calculation speed and increased built-in memory capacity.

The former 80C51 does not have a ready terminal that introduces a ready signal to determine whether the memory or peripheral chip is ready to send or receive data during a read or write cycle. , In FIG. 5 showing the circuit configuration of this first conventional example, the clock pulse CP is transmitted to the CPU via a NAND gate 51.
The clock pulse CP that is applied to the input terminal XTALI of I and further inverted via the inverter 3 is applied to the input terminal XTALI.
Added to L2.

Then, calculations are performed with the WAIT signal (not shown), and data is transferred by the memory and the input/output (I10) circuit.

Furthermore, the latter 7MS320C25 [second conventional example] is provided with a ready terminal.

Furthermore, as a third conventional example, Japanese Patent Application Laid-Open No. 63-121916
You can see the number.

This clock has a basic clock and one or more types of divided clocks obtained by dividing the basic clock, and has an asynchronous stop signal that is not synchronized with the clock to stop all the types of clocks. In the system, a synchronization circuit consisting of a plurality of stages of flip-flops receives the asynchronous stop signal as an input, and a stop timing signal output from the synchronization circuit and one or more timing signals generated by the divided clock are input. This clock control method is characterized in that it is comprised of a stop signal generation circuit that generates a stop signal only when the conditions of the output of the synchronization circuit and all the timing signals are met. In other words, in this third conventional example, the original oscillation is stopped and then the frequency is divided.

[Problem to be solved by the invention]

However, in the first conventional example, as is clear from the timing chart showing its operation in FIG. 6, when attempting to control the system clock pulse using a gate, there is a risk that an abnormally short abnormal pulse 61 may be generated. Yes, but as far as I know, it has not been put into practical use.

In addition, in the second conventional example, since the machine cycle is repeated one more time, there is a problem that the speed decreases abnormally, and when the memory access time is insufficient, the system clock is lowered to cope with it. was.

Furthermore, the third conventional example is a synchronization circuit consisting of multiple stages of flip-flops that receives an asynchronous stop signal as input, and a stop signal that generates a stop signal only when the conditions of the output of the synchronization circuit and all timing signals are met. This is an extremely complicated circuit configuration that requires a signal generation circuit, and is also problematic in terms of cost.

Here, the present invention overcomes the difficulties of these conventional examples and can control the machine cycle by not only using a simple gate circuit but also by dividing the clock pulse by a counter and using it as a system clock. The purpose is to provide a ready circuit provided outside the CPU.

[Means to solve the problem]

The present invention eliminates the need for a CPU or machine cycle that is abnormally long without a ready terminal that introduces a ready signal to determine whether a memory or peripheral chip is ready to send or receive data during a read or write cycle. In many digital signal processing processors, a machine cycle can be started by inputting a clock pulse several times the system clock pulse into a counter, using the divided output of this counter as the system clock pulse, and stopping the counter from counting. This is an external ready circuit for control.

[For production]

With the above configuration, the clock pulse input to the counter provided in the front stage of the CPU is divided into clock pulse widths that are integral multiples, the clock pulse width is geared to match the system clock, and the clock pulse width is The machine cycle can be freely controlled by stopping the counter. That is, the present invention allows the counter to freely start and stop the division period.

〔Example〕

A block diagram showing the circuit configuration of an embodiment of the present invention is shown in FIG.

The same reference numerals represent the same parts in all drawings.

F161 [product name, same as TTL interface type number 5N74161 manufactured by Texas Instruments] is installed in the counter 2 provided in the front stage of the CPUI. A functional block diagram of the 5N74161 is shown in FIG. Each element illustrated here is depicted as a universal graphic symbol, so a description thereof will be omitted.

In FIG. 1, the ENABLE of counter 2 is
) The WAIT signal line is connected to terminals P and T,
A clock pulse CP [for example, 24 MHz] from the oscillator O8C is applied to the clock terminal CP, and the load terminal C3 [chip select terminal] and the DC voltage terminal CC are turned on, and the first The output QA of the flip-flop at the J- stage outputs a system Φ clock of 12 mega Φ hertz with the pulse width divided by twice.

This 12 MHz system clock is CPU
is applied to the input terminal XTALI of the CPU, and its inverted signal is applied to the input terminal XTALI of the CPU via the inverter 3.
Added to L2.

The on/off of the 12 MHz system clock is freely controlled by the WAIT signal.
Since it is obtained as the output from the output QA of the flip ?

That is, the circuit configuration (Fig. 1) of this embodiment is 80
WA I 7 circuit for C51 (CPUI), WA
When IT becomes "L", the clock stops, and when it becomes 'H', the clock starts operating. This makes it the same as ready control.

FIG. 3 is a circuit diagram of another embodiment of the present invention.

This other embodiment is a CPU with two counters.
It constitutes the MS320G 25/3 WAIT circuit.

A time chart showing this operation is shown in FIG.

In FIG. 3, 4 is the same counter as 2, 5 is an inverter, and 6 is an OR circuit.

The data input terminals A, B, C, and D of counter 2 are all grounded, the DC voltage terminal CC is turned on, and the load terminal C5 [chip select terminal] is connected to the line that transmits the chip select signal C8. A chip select signal C3 is introduced from the inverter 3 through the inverter 3, and a clock pulse of 80 megabytes from an oscillator (not shown) is applied to the clock terminal CP.

This ripple carry terminal [RIPPLE CARRY 0UTPUT (15) in Figure 2]
IRC is connected to one input terminal of OR circuit 6, and ripple carry terminal RC is connected to enable terminal P via inverter 5.

They are also connected to T respectively.

Further, the line transmitting the chip select signal C5 is connected to the other input terminal of the OR circuit 6, and the output terminal of the OR circuit 6 is connected to the enable (ENABLE) terminal of the counter 4.
) are connected to terminals P and T, and the terminal connections of this counter 4 are as shown in FIG.

With this configuration, the chip select signal C8 becomes “
During Hm, the 80 MHz clock pulse is used as the 40 MHz help clock for the CPUI's TMS320C.
It is given to 25.

At this time, counter 2 is not working. Then, when the chip select signal C8 becomes "Ll", the counter 2 starts counting, the ripple carry output from the ripple carry terminal RC becomes "H", the counter 2 stops its operation, and the counter 4 starts counting. starts, and after one cycle of the 80 MHz clock pulse, output terminal QA of counter 4
The output from is derived. In other words, after the chip select signal C8 goes low, the CPU's 7MS320
A ready signal is given to C25.

As such, a delay of 37.5 nanoseconds is created.

This makes it possible to extend the clock φ pulse only at the memory ◆ access timing.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to perform ready control of a CPU (DSP) with a simple external circuit, and to control data transfer to memory or peripheral chips during read or write cycles of this type of general-purpose CPU. Preparations for sending or receiving can be made smoothly without any trouble, and it is possible to bring about a remarkable effect that contributes to improving the calculation speed and reliability of the CPU (DSP).

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention, FIG. 2 is a functional block diagram inside the counter, and FIG.
FIG. 4 is a circuit configuration diagram of another embodiment of the present invention, FIG. 4 is a time chart showing its operation, and FIGS. 5 and 6 are explanatory diagrams of the first conventional example. 1...CPU (central processing unit) 2.4...Counter 3.5...Inverter 6...OR circuit 51...NAND gate 61...Abnormal pulse.

Claims (1)

[Claims] 1. A CPU or machine cycle without a ready terminal that introduces a ready signal to determine whether a memory or peripheral chip is ready to send or receive data during a read or write cycle. In a digital signal processing processor that is abnormally long, it is possible to input a clock pulse several times the system clock pulse into a counter, use the divided output of this counter as the system clock pulse, and stop the counter from counting. , an external ready circuit characterized by controlling the machine cycle.